Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates
4 * Copyright (c) 2023 Intel and affiliates
5 */
6
7#ifndef __DPLL_H__
8#define __DPLL_H__
9
10#include <uapi/linux/dpll.h>
11#include <linux/device.h>
12#include <linux/netlink.h>
13#include <linux/netdevice.h>
14#include <linux/rtnetlink.h>
15
16struct dpll_device;
17struct dpll_pin;
18struct dpll_pin_esync;
19
20struct dpll_device_ops {
21 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,
22 enum dpll_mode *mode, struct netlink_ext_ack *extack);
23 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,
24 enum dpll_lock_status *status,
25 enum dpll_lock_status_error *status_error,
26 struct netlink_ext_ack *extack);
27 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
28 s32 *temp, struct netlink_ext_ack *extack);
29};
30
31struct dpll_pin_ops {
32 int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv,
33 const struct dpll_device *dpll, void *dpll_priv,
34 const u64 frequency,
35 struct netlink_ext_ack *extack);
36 int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv,
37 const struct dpll_device *dpll, void *dpll_priv,
38 u64 *frequency, struct netlink_ext_ack *extack);
39 int (*direction_set)(const struct dpll_pin *pin, void *pin_priv,
40 const struct dpll_device *dpll, void *dpll_priv,
41 const enum dpll_pin_direction direction,
42 struct netlink_ext_ack *extack);
43 int (*direction_get)(const struct dpll_pin *pin, void *pin_priv,
44 const struct dpll_device *dpll, void *dpll_priv,
45 enum dpll_pin_direction *direction,
46 struct netlink_ext_ack *extack);
47 int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv,
48 const struct dpll_pin *parent_pin,
49 void *parent_pin_priv,
50 enum dpll_pin_state *state,
51 struct netlink_ext_ack *extack);
52 int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv,
53 const struct dpll_device *dpll,
54 void *dpll_priv, enum dpll_pin_state *state,
55 struct netlink_ext_ack *extack);
56 int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv,
57 const struct dpll_pin *parent_pin,
58 void *parent_pin_priv,
59 const enum dpll_pin_state state,
60 struct netlink_ext_ack *extack);
61 int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv,
62 const struct dpll_device *dpll,
63 void *dpll_priv,
64 const enum dpll_pin_state state,
65 struct netlink_ext_ack *extack);
66 int (*prio_get)(const struct dpll_pin *pin, void *pin_priv,
67 const struct dpll_device *dpll, void *dpll_priv,
68 u32 *prio, struct netlink_ext_ack *extack);
69 int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
70 const struct dpll_device *dpll, void *dpll_priv,
71 const u32 prio, struct netlink_ext_ack *extack);
72 int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
73 const struct dpll_device *dpll, void *dpll_priv,
74 s64 *phase_offset,
75 struct netlink_ext_ack *extack);
76 int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
77 const struct dpll_device *dpll, void *dpll_priv,
78 s32 *phase_adjust,
79 struct netlink_ext_ack *extack);
80 int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
81 const struct dpll_device *dpll, void *dpll_priv,
82 const s32 phase_adjust,
83 struct netlink_ext_ack *extack);
84 int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv,
85 const struct dpll_device *dpll, void *dpll_priv,
86 s64 *ffo, struct netlink_ext_ack *extack);
87 int (*esync_set)(const struct dpll_pin *pin, void *pin_priv,
88 const struct dpll_device *dpll, void *dpll_priv,
89 u64 freq, struct netlink_ext_ack *extack);
90 int (*esync_get)(const struct dpll_pin *pin, void *pin_priv,
91 const struct dpll_device *dpll, void *dpll_priv,
92 struct dpll_pin_esync *esync,
93 struct netlink_ext_ack *extack);
94};
95
96struct dpll_pin_frequency {
97 u64 min;
98 u64 max;
99};
100
101#define DPLL_PIN_FREQUENCY_RANGE(_min, _max) \
102 { \
103 .min = _min, \
104 .max = _max, \
105 }
106
107#define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val)
108#define DPLL_PIN_FREQUENCY_1PPS \
109 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ)
110#define DPLL_PIN_FREQUENCY_10MHZ \
111 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ)
112#define DPLL_PIN_FREQUENCY_IRIG_B \
113 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ)
114#define DPLL_PIN_FREQUENCY_DCF77 \
115 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
116
117struct dpll_pin_phase_adjust_range {
118 s32 min;
119 s32 max;
120};
121
122struct dpll_pin_esync {
123 u64 freq;
124 const struct dpll_pin_frequency *range;
125 u8 range_num;
126 u8 pulse;
127};
128
129struct dpll_pin_properties {
130 const char *board_label;
131 const char *panel_label;
132 const char *package_label;
133 enum dpll_pin_type type;
134 unsigned long capabilities;
135 u32 freq_supported_num;
136 struct dpll_pin_frequency *freq_supported;
137 struct dpll_pin_phase_adjust_range phase_range;
138};
139
140#if IS_ENABLED(CONFIG_DPLL)
141void dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin);
142void dpll_netdev_pin_clear(struct net_device *dev);
143
144size_t dpll_netdev_pin_handle_size(const struct net_device *dev);
145int dpll_netdev_add_pin_handle(struct sk_buff *msg,
146 const struct net_device *dev);
147#else
148static inline void
149dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin) { }
150static inline void dpll_netdev_pin_clear(struct net_device *dev) { }
151
152static inline size_t dpll_netdev_pin_handle_size(const struct net_device *dev)
153{
154 return 0;
155}
156
157static inline int
158dpll_netdev_add_pin_handle(struct sk_buff *msg, const struct net_device *dev)
159{
160 return 0;
161}
162#endif
163
164struct dpll_device *
165dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module);
166
167void dpll_device_put(struct dpll_device *dpll);
168
169int dpll_device_register(struct dpll_device *dpll, enum dpll_type type,
170 const struct dpll_device_ops *ops, void *priv);
171
172void dpll_device_unregister(struct dpll_device *dpll,
173 const struct dpll_device_ops *ops, void *priv);
174
175struct dpll_pin *
176dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module,
177 const struct dpll_pin_properties *prop);
178
179int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,
180 const struct dpll_pin_ops *ops, void *priv);
181
182void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin,
183 const struct dpll_pin_ops *ops, void *priv);
184
185void dpll_pin_put(struct dpll_pin *pin);
186
187int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin,
188 const struct dpll_pin_ops *ops, void *priv);
189
190void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin,
191 const struct dpll_pin_ops *ops, void *priv);
192
193int dpll_device_change_ntf(struct dpll_device *dpll);
194
195int dpll_pin_change_ntf(struct dpll_pin *pin);
196
197#endif