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linux
1#
2# EDAC Kconfig
3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4# Licensed and distributed under the GPL
5
6config EDAC_ATOMIC_SCRUB
7 bool
8
9config EDAC_SUPPORT
10 bool
11
12menuconfig EDAC
13 tristate "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
15 help
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
18 in the CPU or supporting chipset or other subsystems:
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
21
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
23
24if EDAC
25
26config EDAC_LEGACY_SYSFS
27 bool "EDAC legacy sysfs"
28 default y
29 help
30 Enable the compatibility sysfs nodes.
31 Use 'Y' if your edac utilities aren't ported to work with the newer
32 structures.
33
34config EDAC_DEBUG
35 bool "Debugging"
36 select DEBUG_FS
37 help
38 This turns on debugging information for the entire EDAC subsystem.
39 You do so by inserting edac_module with "edac_debug_level=x." Valid
40 levels are 0-4 (from low to high) and by default it is set to 2.
41 Usually you should select 'N' here.
42
43config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
45 depends on CPU_SUP_AMD && X86_MCE_AMD
46 default y
47 help
48 Enable this option if you want to decode Machine Check Exceptions
49 occurring on your machine in human-readable form.
50
51 You should definitely say Y here in case you want to decode MCEs
52 which occur really early upon boot, before the module infrastructure
53 has been initialized.
54
55config EDAC_GHES
56 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC"
57 depends on ACPI_APEI_GHES
58 select UEFI_CPER
59 help
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
62 APEI/GHES driver. By enabling this option, the error reports provided
63 by GHES are sent to userspace via the EDAC API.
64
65 When this option is enabled, it will disable the hardware-driven
66 mechanisms, if a GHES BIOS is detected, entering into the
67 "Firmware First" mode.
68
69 It should be noticed that keeping both GHES and a hardware-driven
70 error mechanism won't work well, as BIOS will race with OS, while
71 reading the error registers. So, if you want to not use "Firmware
72 first" GHES error mechanism, you should disable GHES either at
73 compilation time or by passing "ghes.disable=1" Kernel parameter
74 at boot time.
75
76 In doubt, say 'Y'.
77
78config EDAC_AMD64
79 tristate "AMD64 (Opteron, Athlon64)"
80 depends on AMD_NB && EDAC_DECODE_MCE
81 imply AMD_ATL
82 help
83 Support for error detection and correction of DRAM ECC errors on
84 the AMD64 families (>= K8) of memory controllers.
85
86 When EDAC_DEBUG is enabled, hardware error injection facilities
87 through sysfs are available:
88
89 AMD CPUs up to and excluding family 0x17 provide for Memory
90 Error Injection into the ECC detection circuits. The amd64_edac
91 module allows the operator/user to inject Uncorrectable and
92 Correctable errors into DRAM.
93
94 When enabled, in each of the respective memory controller directories
95 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
96
97 - inject_section (0..3, 16-byte section of 64-byte cacheline),
98 - inject_word (0..8, 16-bit word of 16-byte section),
99 - inject_ecc_vector (hex ecc vector: select bits of inject word)
100
101 In addition, there are two control files, inject_read and inject_write,
102 which trigger the DRAM ECC Read and Write respectively.
103
104config EDAC_AL_MC
105 tristate "Amazon's Annapurna Lab Memory Controller"
106 depends on (ARCH_ALPINE || COMPILE_TEST)
107 help
108 Support for error detection and correction for Amazon's Annapurna
109 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
110
111config EDAC_AMD76X
112 tristate "AMD 76x (760, 762, 768)"
113 depends on PCI && X86_32
114 help
115 Support for error detection and correction on the AMD 76x
116 series of chipsets used with the Athlon processor.
117
118config EDAC_E7XXX
119 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
120 depends on PCI && X86_32
121 help
122 Support for error detection and correction on the Intel
123 E7205, E7500, E7501 and E7505 server chipsets.
124
125config EDAC_E752X
126 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
127 depends on PCI && X86
128 help
129 Support for error detection and correction on the Intel
130 E7520, E7525, E7320 server chipsets.
131
132config EDAC_I82443BXGX
133 tristate "Intel 82443BX/GX (440BX/GX)"
134 depends on PCI && X86_32
135 depends on BROKEN
136 help
137 Support for error detection and correction on the Intel
138 82443BX/GX memory controllers (440BX/GX chipsets).
139
140config EDAC_I82875P
141 tristate "Intel 82875p (D82875P, E7210)"
142 depends on PCI && X86_32
143 help
144 Support for error detection and correction on the Intel
145 DP82785P and E7210 server chipsets.
146
147config EDAC_I82975X
148 tristate "Intel 82975x (D82975x)"
149 depends on PCI && X86
150 help
151 Support for error detection and correction on the Intel
152 DP82975x server chipsets.
153
154config EDAC_I3000
155 tristate "Intel 3000/3010"
156 depends on PCI && X86
157 help
158 Support for error detection and correction on the Intel
159 3000 and 3010 server chipsets.
160
161config EDAC_I3200
162 tristate "Intel 3200"
163 depends on PCI && X86
164 help
165 Support for error detection and correction on the Intel
166 3200 and 3210 server chipsets.
167
168config EDAC_IE31200
169 tristate "Intel e312xx"
170 depends on PCI && X86
171 help
172 Support for error detection and correction on the Intel
173 E3-1200 based DRAM controllers.
174
175config EDAC_X38
176 tristate "Intel X38"
177 depends on PCI && X86
178 help
179 Support for error detection and correction on the Intel
180 X38 server chipsets.
181
182config EDAC_I5400
183 tristate "Intel 5400 (Seaburg) chipsets"
184 depends on PCI && X86
185 help
186 Support for error detection and correction the Intel
187 i5400 MCH chipset (Seaburg).
188
189config EDAC_I7CORE
190 tristate "Intel i7 Core (Nehalem) processors"
191 depends on PCI && X86 && X86_MCE_INTEL
192 help
193 Support for error detection and correction the Intel
194 i7 Core (Nehalem) Integrated Memory Controller that exists on
195 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
196 and Xeon 55xx processors.
197
198config EDAC_I82860
199 tristate "Intel 82860"
200 depends on PCI && X86_32
201 help
202 Support for error detection and correction on the Intel
203 82860 chipset.
204
205config EDAC_R82600
206 tristate "Radisys 82600 embedded chipset"
207 depends on PCI && X86_32
208 help
209 Support for error detection and correction on the Radisys
210 82600 embedded chipset.
211
212config EDAC_I5000
213 tristate "Intel Greencreek/Blackford chipset"
214 depends on X86 && PCI
215 depends on BROKEN
216 help
217 Support for error detection and correction the Intel
218 Greekcreek/Blackford chipsets.
219
220config EDAC_I5100
221 tristate "Intel San Clemente MCH"
222 depends on X86 && PCI
223 help
224 Support for error detection and correction the Intel
225 San Clemente MCH.
226
227config EDAC_I7300
228 tristate "Intel Clarksboro MCH"
229 depends on X86 && PCI
230 help
231 Support for error detection and correction the Intel
232 Clarksboro MCH (Intel 7300 chipset).
233
234config EDAC_SBRIDGE
235 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
236 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
237 help
238 Support for error detection and correction the Intel
239 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
240
241config EDAC_SKX
242 tristate "Intel Skylake server Integrated MC"
243 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
244 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
245 select DMI
246 select ACPI_ADXL
247 help
248 Support for error detection and correction the Intel
249 Skylake server Integrated Memory Controllers. If your
250 system has non-volatile DIMMs you should also manually
251 select CONFIG_ACPI_NFIT.
252
253config EDAC_I10NM
254 tristate "Intel 10nm server Integrated MC"
255 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
256 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
257 select DMI
258 select ACPI_ADXL
259 help
260 Support for error detection and correction the Intel
261 10nm server Integrated Memory Controllers. If your
262 system has non-volatile DIMMs you should also manually
263 select CONFIG_ACPI_NFIT.
264
265config EDAC_PND2
266 tristate "Intel Pondicherry2"
267 depends on PCI && X86_64 && X86_MCE_INTEL
268 select P2SB if X86
269 help
270 Support for error detection and correction on the Intel
271 Pondicherry2 Integrated Memory Controller. This SoC IP is
272 first used on the Apollo Lake platform and Denverton
273 micro-server but may appear on others in the future.
274
275config EDAC_IGEN6
276 tristate "Intel client SoC Integrated MC"
277 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
278 depends on X86_64 && X86_MCE_INTEL
279 help
280 Support for error detection and correction on the Intel
281 client SoC Integrated Memory Controller using In-Band ECC IP.
282 This In-Band ECC is first used on the Elkhart Lake SoC but
283 may appear on others in the future.
284
285config EDAC_MPC85XX
286 bool "Freescale MPC83xx / MPC85xx"
287 depends on FSL_SOC && EDAC=y
288 help
289 Support for error detection and correction on the Freescale
290 MPC8349, MPC8560, MPC8540, MPC8548, T4240
291
292config EDAC_LAYERSCAPE
293 tristate "Freescale Layerscape DDR"
294 depends on ARCH_LAYERSCAPE || SOC_LS1021A
295 help
296 Support for error detection and correction on Freescale memory
297 controllers on Layerscape SoCs.
298
299config EDAC_PASEMI
300 tristate "PA Semi PWRficient"
301 depends on PPC_PASEMI && PCI
302 help
303 Support for error detection and correction on PA Semi
304 PWRficient.
305
306config EDAC_CELL
307 tristate "Cell Broadband Engine memory controller"
308 depends on PPC_CELL_COMMON
309 help
310 Support for error detection and correction on the
311 Cell Broadband Engine internal memory controller
312 on platform without a hypervisor
313
314config EDAC_AMD8131
315 tristate "AMD8131 HyperTransport PCI-X Tunnel"
316 depends on PCI && PPC_MAPLE
317 help
318 Support for error detection and correction on the
319 AMD8131 HyperTransport PCI-X Tunnel chip.
320 Note, add more Kconfig dependency if it's adopted
321 on some machine other than Maple.
322
323config EDAC_AMD8111
324 tristate "AMD8111 HyperTransport I/O Hub"
325 depends on PCI && PPC_MAPLE
326 help
327 Support for error detection and correction on the
328 AMD8111 HyperTransport I/O Hub chip.
329 Note, add more Kconfig dependency if it's adopted
330 on some machine other than Maple.
331
332config EDAC_CPC925
333 tristate "IBM CPC925 Memory Controller (PPC970FX)"
334 depends on PPC64
335 help
336 Support for error detection and correction on the
337 IBM CPC925 Bridge and Memory Controller, which is
338 a companion chip to the PowerPC 970 family of
339 processors.
340
341config EDAC_HIGHBANK_MC
342 tristate "Highbank Memory Controller"
343 depends on ARCH_HIGHBANK
344 help
345 Support for error detection and correction on the
346 Calxeda Highbank memory controller.
347
348config EDAC_HIGHBANK_L2
349 tristate "Highbank L2 Cache"
350 depends on ARCH_HIGHBANK
351 help
352 Support for error detection and correction on the
353 Calxeda Highbank memory controller.
354
355config EDAC_OCTEON_PC
356 tristate "Cavium Octeon Primary Caches"
357 depends on CPU_CAVIUM_OCTEON
358 help
359 Support for error detection and correction on the primary caches of
360 the cnMIPS cores of Cavium Octeon family SOCs.
361
362config EDAC_OCTEON_L2C
363 tristate "Cavium Octeon Secondary Caches (L2C)"
364 depends on CAVIUM_OCTEON_SOC
365 help
366 Support for error detection and correction on the
367 Cavium Octeon family of SOCs.
368
369config EDAC_OCTEON_LMC
370 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
371 depends on CAVIUM_OCTEON_SOC
372 help
373 Support for error detection and correction on the
374 Cavium Octeon family of SOCs.
375
376config EDAC_OCTEON_PCI
377 tristate "Cavium Octeon PCI Controller"
378 depends on PCI && CAVIUM_OCTEON_SOC
379 help
380 Support for error detection and correction on the
381 Cavium Octeon family of SOCs.
382
383config EDAC_THUNDERX
384 tristate "Cavium ThunderX EDAC"
385 depends on ARM64
386 depends on PCI
387 help
388 Support for error detection and correction on the
389 Cavium ThunderX memory controllers (LMC), Cache
390 Coherent Processor Interconnect (CCPI) and L2 cache
391 blocks (TAD, CBC, MCI).
392
393config EDAC_ALTERA
394 bool "Altera SOCFPGA ECC"
395 depends on EDAC=y && ARCH_INTEL_SOCFPGA
396 help
397 Support for error detection and correction on the
398 Altera SOCs. This is the global enable for the
399 various Altera peripherals.
400
401config EDAC_ALTERA_SDRAM
402 bool "Altera SDRAM ECC"
403 depends on EDAC_ALTERA=y
404 help
405 Support for error detection and correction on the
406 Altera SDRAM Memory for Altera SoCs. Note that the
407 preloader must initialize the SDRAM before loading
408 the kernel.
409
410config EDAC_ALTERA_L2C
411 bool "Altera L2 Cache ECC"
412 depends on EDAC_ALTERA=y && CACHE_L2X0
413 help
414 Support for error detection and correction on the
415 Altera L2 cache Memory for Altera SoCs. This option
416 requires L2 cache.
417
418config EDAC_ALTERA_OCRAM
419 bool "Altera On-Chip RAM ECC"
420 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
421 help
422 Support for error detection and correction on the
423 Altera On-Chip RAM Memory for Altera SoCs.
424
425config EDAC_ALTERA_ETHERNET
426 bool "Altera Ethernet FIFO ECC"
427 depends on EDAC_ALTERA=y
428 help
429 Support for error detection and correction on the
430 Altera Ethernet FIFO Memory for Altera SoCs.
431
432config EDAC_ALTERA_NAND
433 bool "Altera NAND FIFO ECC"
434 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
435 help
436 Support for error detection and correction on the
437 Altera NAND FIFO Memory for Altera SoCs.
438
439config EDAC_ALTERA_DMA
440 bool "Altera DMA FIFO ECC"
441 depends on EDAC_ALTERA=y && PL330_DMA=y
442 help
443 Support for error detection and correction on the
444 Altera DMA FIFO Memory for Altera SoCs.
445
446config EDAC_ALTERA_USB
447 bool "Altera USB FIFO ECC"
448 depends on EDAC_ALTERA=y && USB_DWC2
449 help
450 Support for error detection and correction on the
451 Altera USB FIFO Memory for Altera SoCs.
452
453config EDAC_ALTERA_QSPI
454 bool "Altera QSPI FIFO ECC"
455 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
456 help
457 Support for error detection and correction on the
458 Altera QSPI FIFO Memory for Altera SoCs.
459
460config EDAC_ALTERA_SDMMC
461 bool "Altera SDMMC FIFO ECC"
462 depends on EDAC_ALTERA=y && MMC_DW
463 help
464 Support for error detection and correction on the
465 Altera SDMMC FIFO Memory for Altera SoCs.
466
467config EDAC_SIFIVE
468 bool "Sifive platform EDAC driver"
469 depends on EDAC=y && SIFIVE_CCACHE
470 help
471 Support for error detection and correction on the SiFive SoCs.
472
473config EDAC_ARMADA_XP
474 bool "Marvell Armada XP DDR and L2 Cache ECC"
475 depends on MACH_MVEBU_V7
476 help
477 Support for error correction and detection on the Marvell Aramada XP
478 DDR RAM and L2 cache controllers.
479
480config EDAC_SYNOPSYS
481 tristate "Synopsys DDR Memory Controller"
482 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC
483 help
484 Support for error detection and correction on the Synopsys DDR
485 memory controller.
486
487config EDAC_XGENE
488 tristate "APM X-Gene SoC"
489 depends on (ARM64 || COMPILE_TEST)
490 help
491 Support for error detection and correction on the
492 APM X-Gene family of SOCs.
493
494config EDAC_TI
495 tristate "Texas Instruments DDR3 ECC Controller"
496 depends on ARCH_KEYSTONE || SOC_DRA7XX
497 help
498 Support for error detection and correction on the TI SoCs.
499
500config EDAC_QCOM
501 tristate "QCOM EDAC Controller"
502 depends on ARCH_QCOM && QCOM_LLCC
503 help
504 Support for error detection and correction on the
505 Qualcomm Technologies, Inc. SoCs.
506
507 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
508 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
509 of Tag RAM and Data RAM.
510
511 For debugging issues having to do with stability and overall system
512 health, you should probably say 'Y' here.
513
514config EDAC_ASPEED
515 tristate "Aspeed AST BMC SoC"
516 depends on ARCH_ASPEED
517 help
518 Support for error detection and correction on the Aspeed AST BMC SoC.
519
520 First, ECC must be configured in the bootloader. Then, this driver
521 will expose error counters via the EDAC kernel framework.
522
523config EDAC_BLUEFIELD
524 tristate "Mellanox BlueField Memory ECC"
525 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
526 help
527 Support for error detection and correction on the
528 Mellanox BlueField SoCs.
529
530config EDAC_DMC520
531 tristate "ARM DMC-520 ECC"
532 depends on ARM64
533 help
534 Support for error detection and correction on the
535 SoCs with ARM DMC-520 DRAM controller.
536
537config EDAC_ZYNQMP
538 tristate "Xilinx ZynqMP OCM Controller"
539 depends on ARCH_ZYNQMP || COMPILE_TEST
540 help
541 This driver supports error detection and correction for the
542 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be
543 built as a module. In that case it will be called zynqmp_edac.
544
545config EDAC_NPCM
546 tristate "Nuvoton NPCM DDR Memory Controller"
547 depends on (ARCH_NPCM || COMPILE_TEST)
548 help
549 Support for error detection and correction on the Nuvoton NPCM DDR
550 memory controller.
551
552 The memory controller supports single bit error correction, double bit
553 error detection (in-line ECC in which a section 1/8th of the memory
554 device used to store data is used for ECC storage).
555
556config EDAC_VERSAL
557 tristate "Xilinx Versal DDR Memory Controller"
558 depends on ARCH_ZYNQMP || COMPILE_TEST
559 help
560 Support for error detection and correction on the Xilinx Versal DDR
561 memory controller.
562
563 Report both single bit errors (CE) and double bit errors (UE).
564 Support injecting both correctable and uncorrectable errors
565 for debugging purposes.
566
567
568endif # EDAC