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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012 Regents of the University of California
4 */
5
6#ifndef _ASM_RISCV_PROCESSOR_H
7#define _ASM_RISCV_PROCESSOR_H
8
9#include <linux/const.h>
10#include <linux/cache.h>
11#include <linux/prctl.h>
12
13#include <vdso/processor.h>
14
15#include <asm/ptrace.h>
16
17#define arch_get_mmap_end(addr, len, flags) \
18({ \
19 STACK_TOP_MAX; \
20})
21
22#define arch_get_mmap_base(addr, base) \
23({ \
24 base; \
25})
26
27#ifdef CONFIG_64BIT
28#define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1))
29#define STACK_TOP_MAX TASK_SIZE_64
30#else
31#define DEFAULT_MAP_WINDOW TASK_SIZE
32#define STACK_TOP_MAX TASK_SIZE
33#endif
34#define STACK_ALIGN 16
35
36#define STACK_TOP DEFAULT_MAP_WINDOW
37
38#ifdef CONFIG_MMU
39#define user_max_virt_addr() arch_get_mmap_end(ULONG_MAX, 0, 0)
40#else
41#define user_max_virt_addr() 0
42#endif /* CONFIG_MMU */
43
44/*
45 * This decides where the kernel will search for a free chunk of vm
46 * space during mmap's.
47 */
48#ifdef CONFIG_64BIT
49#define TASK_UNMAPPED_BASE PAGE_ALIGN((UL(1) << MMAP_MIN_VA_BITS) / 3)
50#else
51#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
52#endif
53
54#ifndef __ASSEMBLY__
55#include <linux/cpumask.h>
56
57struct task_struct;
58struct pt_regs;
59
60/*
61 * We use a flag to track in-kernel Vector context. Currently the flag has the
62 * following meaning:
63 *
64 * - bit 0: indicates whether the in-kernel Vector context is active. The
65 * activation of this state disables the preemption. On a non-RT kernel, it
66 * also disable bh.
67 * - bits 8: is used for tracking preemptible kernel-mode Vector, when
68 * RISCV_ISA_V_PREEMPTIVE is enabled. Calling kernel_vector_begin() does not
69 * disable the preemption if the thread's kernel_vstate.datap is allocated.
70 * Instead, the kernel set this bit field. Then the trap entry/exit code
71 * knows if we are entering/exiting the context that owns preempt_v.
72 * - 0: the task is not using preempt_v
73 * - 1: the task is actively using preempt_v. But whether does the task own
74 * the preempt_v context is decided by bits in RISCV_V_CTX_DEPTH_MASK.
75 * - bit 16-23 are RISCV_V_CTX_DEPTH_MASK, used by context tracking routine
76 * when preempt_v starts:
77 * - 0: the task is actively using, and own preempt_v context.
78 * - non-zero: the task was using preempt_v, but then took a trap within.
79 * Thus, the task does not own preempt_v. Any use of Vector will have to
80 * save preempt_v, if dirty, and fallback to non-preemptible kernel-mode
81 * Vector.
82 * - bit 30: The in-kernel preempt_v context is saved, and requries to be
83 * restored when returning to the context that owns the preempt_v.
84 * - bit 31: The in-kernel preempt_v context is dirty, as signaled by the
85 * trap entry code. Any context switches out-of current task need to save
86 * it to the task's in-kernel V context. Also, any traps nesting on-top-of
87 * preempt_v requesting to use V needs a save.
88 */
89#define RISCV_V_CTX_DEPTH_MASK 0x00ff0000
90
91#define RISCV_V_CTX_UNIT_DEPTH 0x00010000
92#define RISCV_KERNEL_MODE_V 0x00000001
93#define RISCV_PREEMPT_V 0x00000100
94#define RISCV_PREEMPT_V_DIRTY 0x80000000
95#define RISCV_PREEMPT_V_NEED_RESTORE 0x40000000
96
97/* CPU-specific state of a task */
98struct thread_struct {
99 /* Callee-saved registers */
100 unsigned long ra;
101 unsigned long sp; /* Kernel mode stack */
102 unsigned long s[12]; /* s[0]: frame pointer */
103 struct __riscv_d_ext_state fstate;
104 unsigned long bad_cause;
105 u32 riscv_v_flags;
106 u32 vstate_ctrl;
107 struct __riscv_v_ext_state vstate;
108 unsigned long align_ctl;
109 struct __riscv_v_ext_state kernel_vstate;
110#ifdef CONFIG_SMP
111 /* Flush the icache on migration */
112 bool force_icache_flush;
113 /* A forced icache flush is not needed if migrating to the previous cpu. */
114 unsigned int prev_cpu;
115#endif
116};
117
118/* Whitelist the fstate from the task_struct for hardened usercopy */
119static inline void arch_thread_struct_whitelist(unsigned long *offset,
120 unsigned long *size)
121{
122 *offset = offsetof(struct thread_struct, fstate);
123 *size = sizeof_field(struct thread_struct, fstate);
124}
125
126#define INIT_THREAD { \
127 .sp = sizeof(init_stack) + (long)&init_stack, \
128 .align_ctl = PR_UNALIGN_NOPRINT, \
129}
130
131#define task_pt_regs(tsk) \
132 ((struct pt_regs *)(task_stack_page(tsk) + THREAD_SIZE \
133 - ALIGN(sizeof(struct pt_regs), STACK_ALIGN)))
134
135#define KSTK_EIP(tsk) (task_pt_regs(tsk)->epc)
136#define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp)
137
138
139/* Do necessary setup to start up a newly executed thread. */
140extern void start_thread(struct pt_regs *regs,
141 unsigned long pc, unsigned long sp);
142
143extern unsigned long __get_wchan(struct task_struct *p);
144
145
146static inline void wait_for_interrupt(void)
147{
148 __asm__ __volatile__ ("wfi");
149}
150
151extern phys_addr_t dma32_phys_limit;
152
153struct device_node;
154int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);
155int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid);
156int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
157
158extern void riscv_fill_hwcap(void);
159extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
160
161extern unsigned long signal_minsigstksz __ro_after_init;
162
163#ifdef CONFIG_RISCV_ISA_V
164/* Userspace interface for PR_RISCV_V_{SET,GET}_VS prctl()s: */
165#define RISCV_V_SET_CONTROL(arg) riscv_v_vstate_ctrl_set_current(arg)
166#define RISCV_V_GET_CONTROL() riscv_v_vstate_ctrl_get_current()
167extern long riscv_v_vstate_ctrl_set_current(unsigned long arg);
168extern long riscv_v_vstate_ctrl_get_current(void);
169#endif /* CONFIG_RISCV_ISA_V */
170
171extern int get_unalign_ctl(struct task_struct *tsk, unsigned long addr);
172extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
173
174#define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr))
175#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
176
177#define RISCV_SET_ICACHE_FLUSH_CTX(arg1, arg2) riscv_set_icache_flush_ctx(arg1, arg2)
178extern int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long per_thread);
179
180#endif /* __ASSEMBLY__ */
181
182#endif /* _ASM_RISCV_PROCESSOR_H */