tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Last Level Cache Controller
8
9maintainers:
10 - Bjorn Andersson <andersson@kernel.org>
11
12description: |
13 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
14 that can be shared by multiple clients. Clients here are different cores in the
15 SoC, the idea is to minimize the local caches at the clients and migrate to
16 common pool of memory. Cache memory is divided into partitions called slices
17 which are assigned to clients. Clients can query the slice details, activate
18 and deactivate them.
19
20properties:
21 compatible:
22 enum:
23 - qcom,qdu1000-llcc
24 - qcom,sa8775p-llcc
25 - qcom,sc7180-llcc
26 - qcom,sc7280-llcc
27 - qcom,sc8180x-llcc
28 - qcom,sc8280xp-llcc
29 - qcom,sdm845-llcc
30 - qcom,sm6350-llcc
31 - qcom,sm7150-llcc
32 - qcom,sm8150-llcc
33 - qcom,sm8250-llcc
34 - qcom,sm8350-llcc
35 - qcom,sm8450-llcc
36 - qcom,sm8550-llcc
37 - qcom,sm8650-llcc
38 - qcom,x1e80100-llcc
39
40 reg:
41 minItems: 2
42 maxItems: 9
43
44 reg-names:
45 minItems: 2
46 maxItems: 9
47
48 interrupts:
49 maxItems: 1
50
51 nvmem-cells:
52 items:
53 - description: Reference to an nvmem node for multi channel DDR
54
55 nvmem-cell-names:
56 items:
57 - const: multi-chan-ddr
58
59required:
60 - compatible
61 - reg
62 - reg-names
63
64allOf:
65 - if:
66 properties:
67 compatible:
68 contains:
69 enum:
70 - qcom,sc7180-llcc
71 - qcom,sm6350-llcc
72 then:
73 properties:
74 reg:
75 items:
76 - description: LLCC0 base register region
77 - description: LLCC broadcast base register region
78 reg-names:
79 items:
80 - const: llcc0_base
81 - const: llcc_broadcast_base
82
83 - if:
84 properties:
85 compatible:
86 contains:
87 enum:
88 - qcom,sa8775p-llcc
89 then:
90 properties:
91 reg:
92 items:
93 - description: LLCC0 base register region
94 - description: LLCC1 base register region
95 - description: LLCC2 base register region
96 - description: LLCC3 base register region
97 - description: LLCC4 base register region
98 - description: LLCC5 base register region
99 - description: LLCC broadcast base register region
100 reg-names:
101 items:
102 - const: llcc0_base
103 - const: llcc1_base
104 - const: llcc2_base
105 - const: llcc3_base
106 - const: llcc4_base
107 - const: llcc5_base
108 - const: llcc_broadcast_base
109
110 - if:
111 properties:
112 compatible:
113 contains:
114 enum:
115 - qcom,sc7280-llcc
116 then:
117 properties:
118 reg:
119 items:
120 - description: LLCC0 base register region
121 - description: LLCC1 base register region
122 - description: LLCC broadcast base register region
123 reg-names:
124 items:
125 - const: llcc0_base
126 - const: llcc1_base
127 - const: llcc_broadcast_base
128
129 - if:
130 properties:
131 compatible:
132 contains:
133 enum:
134 - qcom,qdu1000-llcc
135 - qcom,sc8180x-llcc
136 - qcom,sc8280xp-llcc
137 - qcom,x1e80100-llcc
138 then:
139 properties:
140 reg:
141 items:
142 - description: LLCC0 base register region
143 - description: LLCC1 base register region
144 - description: LLCC2 base register region
145 - description: LLCC3 base register region
146 - description: LLCC4 base register region
147 - description: LLCC5 base register region
148 - description: LLCC6 base register region
149 - description: LLCC7 base register region
150 - description: LLCC broadcast base register region
151 reg-names:
152 items:
153 - const: llcc0_base
154 - const: llcc1_base
155 - const: llcc2_base
156 - const: llcc3_base
157 - const: llcc4_base
158 - const: llcc5_base
159 - const: llcc6_base
160 - const: llcc7_base
161 - const: llcc_broadcast_base
162
163 - if:
164 properties:
165 compatible:
166 contains:
167 enum:
168 - qcom,sdm845-llcc
169 - qcom,sm8150-llcc
170 - qcom,sm8250-llcc
171 - qcom,sm8350-llcc
172 then:
173 properties:
174 reg:
175 items:
176 - description: LLCC0 base register region
177 - description: LLCC1 base register region
178 - description: LLCC2 base register region
179 - description: LLCC3 base register region
180 - description: LLCC broadcast base register region
181 reg-names:
182 items:
183 - const: llcc0_base
184 - const: llcc1_base
185 - const: llcc2_base
186 - const: llcc3_base
187 - const: llcc_broadcast_base
188
189 - if:
190 properties:
191 compatible:
192 contains:
193 enum:
194 - qcom,sm8450-llcc
195 - qcom,sm8550-llcc
196 - qcom,sm8650-llcc
197 then:
198 properties:
199 reg:
200 items:
201 - description: LLCC0 base register region
202 - description: LLCC1 base register region
203 - description: LLCC2 base register region
204 - description: LLCC3 base register region
205 - description: LLCC broadcast OR register region
206 - description: LLCC broadcast AND register region
207 reg-names:
208 items:
209 - const: llcc0_base
210 - const: llcc1_base
211 - const: llcc2_base
212 - const: llcc3_base
213 - const: llcc_broadcast_base
214 - const: llcc_broadcast_and_base
215
216additionalProperties: false
217
218examples:
219 - |
220 #include <dt-bindings/interrupt-controller/arm-gic.h>
221
222 soc {
223 #address-cells = <2>;
224 #size-cells = <2>;
225
226 system-cache-controller@1100000 {
227 compatible = "qcom,sdm845-llcc";
228 reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,
229 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
230 <0 0x01300000 0 0x50000>;
231 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
232 "llcc3_base", "llcc_broadcast_base";
233 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
234 };
235 };