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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2013-2014, Linaro Ltd.
4 * Author: Al Stone <al.stone@linaro.org>
5 * Author: Graeme Gregory <graeme.gregory@linaro.org>
6 * Author: Hanjun Guo <hanjun.guo@linaro.org>
7 */
8
9#ifndef _ASM_ACPI_H
10#define _ASM_ACPI_H
11
12#include <linux/cpuidle.h>
13#include <linux/efi.h>
14#include <linux/memblock.h>
15#include <linux/psci.h>
16#include <linux/stddef.h>
17
18#include <asm/cputype.h>
19#include <asm/io.h>
20#include <asm/ptrace.h>
21#include <asm/smp_plat.h>
22#include <asm/tlbflush.h>
23
24/* Macros for consistency checks of the GICC subtable of MADT */
25
26/*
27 * MADT GICC minimum length refers to the MADT GICC structure table length as
28 * defined in the earliest ACPI version supported on arm64, ie ACPI 5.1.
29 *
30 * The efficiency_class member was added to the
31 * struct acpi_madt_generic_interrupt to represent the MADT GICC structure
32 * "Processor Power Efficiency Class" field, added in ACPI 6.0 whose offset
33 * is therefore used to delimit the MADT GICC structure minimum length
34 * appropriately.
35 */
36#define ACPI_MADT_GICC_MIN_LENGTH offsetof( \
37 struct acpi_madt_generic_interrupt, efficiency_class)
38
39#define BAD_MADT_GICC_ENTRY(entry, end) \
40 (!(entry) || (entry)->header.length < ACPI_MADT_GICC_MIN_LENGTH || \
41 (unsigned long)(entry) + (entry)->header.length > (end))
42
43#define ACPI_MADT_GICC_SPE (offsetof(struct acpi_madt_generic_interrupt, \
44 spe_interrupt) + sizeof(u16))
45
46#define ACPI_MADT_GICC_TRBE (offsetof(struct acpi_madt_generic_interrupt, \
47 trbe_interrupt) + sizeof(u16))
48/*
49 * Arm® Functional Fixed Hardware Specification Version 1.2.
50 * Table 2: Arm Architecture context loss flags
51 */
52#define CPUIDLE_CORE_CTXT BIT(0) /* Core context Lost */
53
54static inline unsigned int arch_get_idle_state_flags(u32 arch_flags)
55{
56 if (arch_flags & CPUIDLE_CORE_CTXT)
57 return CPUIDLE_FLAG_TIMER_STOP;
58
59 return 0;
60}
61#define arch_get_idle_state_flags arch_get_idle_state_flags
62
63#define CPUIDLE_TRACE_CTXT BIT(1) /* Trace context loss */
64#define CPUIDLE_GICR_CTXT BIT(2) /* GICR */
65#define CPUIDLE_GICD_CTXT BIT(3) /* GICD */
66
67/* Basic configuration for ACPI */
68#ifdef CONFIG_ACPI
69pgprot_t __acpi_get_mem_attribute(phys_addr_t addr);
70
71/* ACPI table mapping after acpi_permanent_mmap is set */
72void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size);
73#define acpi_os_ioremap acpi_os_ioremap
74
75typedef u64 phys_cpuid_t;
76#define PHYS_CPUID_INVALID INVALID_HWID
77
78#define acpi_strict 1 /* No out-of-spec workarounds on ARM64 */
79extern int acpi_disabled;
80extern int acpi_noirq;
81extern int acpi_pci_disabled;
82
83static inline void disable_acpi(void)
84{
85 acpi_disabled = 1;
86 acpi_pci_disabled = 1;
87 acpi_noirq = 1;
88}
89
90static inline void enable_acpi(void)
91{
92 acpi_disabled = 0;
93 acpi_pci_disabled = 0;
94 acpi_noirq = 0;
95}
96
97/*
98 * The ACPI processor driver for ACPI core code needs this macro
99 * to find out this cpu was already mapped (mapping from CPU hardware
100 * ID to CPU logical ID) or not.
101 */
102#define cpu_physical_id(cpu) cpu_logical_map(cpu)
103
104/*
105 * It's used from ACPI core in kdump to boot UP system with SMP kernel,
106 * with this check the ACPI core will not override the CPU index
107 * obtained from GICC with 0 and not print some error message as well.
108 * Since MADT must provide at least one GICC structure for GIC
109 * initialization, CPU will be always available in MADT on ARM64.
110 */
111static inline bool acpi_has_cpu_in_madt(void)
112{
113 return true;
114}
115
116struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu);
117static inline u32 get_acpi_id_for_cpu(unsigned int cpu)
118{
119 return acpi_cpu_get_madt_gicc(cpu)->uid;
120}
121
122static inline int get_cpu_for_acpi_id(u32 uid)
123{
124 int cpu;
125
126 for (cpu = 0; cpu < nr_cpu_ids; cpu++)
127 if (acpi_cpu_get_madt_gicc(cpu) &&
128 uid == get_acpi_id_for_cpu(cpu))
129 return cpu;
130
131 return -EINVAL;
132}
133
134static inline void arch_fix_phys_package_id(int num, u32 slot) { }
135void __init acpi_init_cpus(void);
136int apei_claim_sea(struct pt_regs *regs);
137#else
138static inline void acpi_init_cpus(void) { }
139static inline int apei_claim_sea(struct pt_regs *regs) { return -ENOENT; }
140#endif /* CONFIG_ACPI */
141
142#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL
143bool acpi_parking_protocol_valid(int cpu);
144void __init
145acpi_set_mailbox_entry(int cpu, struct acpi_madt_generic_interrupt *processor);
146#else
147static inline bool acpi_parking_protocol_valid(int cpu) { return false; }
148static inline void
149acpi_set_mailbox_entry(int cpu, struct acpi_madt_generic_interrupt *processor)
150{}
151#endif
152
153static inline const char *acpi_get_enable_method(int cpu)
154{
155 if (acpi_psci_present())
156 return "psci";
157
158 if (acpi_parking_protocol_valid(cpu))
159 return "parking-protocol";
160
161 return NULL;
162}
163
164#ifdef CONFIG_ACPI_APEI
165/*
166 * acpi_disable_cmcff is used in drivers/acpi/apei/hest.c for disabling
167 * IA-32 Architecture Corrected Machine Check (CMC) Firmware-First mode
168 * with a kernel command line parameter "acpi=nocmcoff". But we don't
169 * have this IA-32 specific feature on ARM64, this definition is only
170 * for compatibility.
171 */
172#define acpi_disable_cmcff 1
173static inline pgprot_t arch_apei_get_mem_attribute(phys_addr_t addr)
174{
175 return __acpi_get_mem_attribute(addr);
176}
177#endif /* CONFIG_ACPI_APEI */
178
179#ifdef CONFIG_ACPI_NUMA
180int arm64_acpi_numa_init(void);
181int acpi_numa_get_nid(unsigned int cpu);
182void acpi_map_cpus_to_nodes(void);
183#else
184static inline int arm64_acpi_numa_init(void) { return -ENOSYS; }
185static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; }
186static inline void acpi_map_cpus_to_nodes(void) { }
187#endif /* CONFIG_ACPI_NUMA */
188
189#define ACPI_TABLE_UPGRADE_MAX_PHYS MEMBLOCK_ALLOC_ACCESSIBLE
190
191#endif /*_ASM_ACPI_H*/