Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel
os
linux
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __AMDGPU_UCODE_H__
24#define __AMDGPU_UCODE_H__
25
26#include "amdgpu_socbb.h"
27
28struct common_firmware_header {
29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
30 uint32_t header_size_bytes; /* size of just the header in bytes */
31 uint16_t header_version_major; /* header version */
32 uint16_t header_version_minor; /* header version */
33 uint16_t ip_version_major; /* IP version */
34 uint16_t ip_version_minor; /* IP version */
35 uint32_t ucode_version;
36 uint32_t ucode_size_bytes; /* size of ucode in bytes */
37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
38 uint32_t crc32; /* crc32 checksum of the payload */
39};
40
41/* version_major=1, version_minor=0 */
42struct mc_firmware_header_v1_0 {
43 struct common_firmware_header header;
44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */
45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
46};
47
48/* version_major=1, version_minor=0 */
49struct smc_firmware_header_v1_0 {
50 struct common_firmware_header header;
51 uint32_t ucode_start_addr;
52};
53
54/* version_major=2, version_minor=0 */
55struct smc_firmware_header_v2_0 {
56 struct smc_firmware_header_v1_0 v1_0;
57 uint32_t ppt_offset_bytes; /* soft pptable offset */
58 uint32_t ppt_size_bytes; /* soft pptable size */
59};
60
61struct smc_soft_pptable_entry {
62 uint32_t id;
63 uint32_t ppt_offset_bytes;
64 uint32_t ppt_size_bytes;
65};
66
67/* version_major=2, version_minor=1 */
68struct smc_firmware_header_v2_1 {
69 struct smc_firmware_header_v1_0 v1_0;
70 uint32_t pptable_count;
71 uint32_t pptable_entry_offset;
72};
73
74struct psp_fw_legacy_bin_desc {
75 uint32_t fw_version;
76 uint32_t offset_bytes;
77 uint32_t size_bytes;
78};
79
80/* version_major=1, version_minor=0 */
81struct psp_firmware_header_v1_0 {
82 struct common_firmware_header header;
83 struct psp_fw_legacy_bin_desc sos;
84};
85
86/* version_major=1, version_minor=1 */
87struct psp_firmware_header_v1_1 {
88 struct psp_firmware_header_v1_0 v1_0;
89 struct psp_fw_legacy_bin_desc toc;
90 struct psp_fw_legacy_bin_desc kdb;
91};
92
93/* version_major=1, version_minor=2 */
94struct psp_firmware_header_v1_2 {
95 struct psp_firmware_header_v1_0 v1_0;
96 struct psp_fw_legacy_bin_desc res;
97 struct psp_fw_legacy_bin_desc kdb;
98};
99
100/* version_major=1, version_minor=3 */
101struct psp_firmware_header_v1_3 {
102 struct psp_firmware_header_v1_1 v1_1;
103 struct psp_fw_legacy_bin_desc spl;
104 struct psp_fw_legacy_bin_desc rl;
105 struct psp_fw_legacy_bin_desc sys_drv_aux;
106 struct psp_fw_legacy_bin_desc sos_aux;
107};
108
109struct psp_fw_bin_desc {
110 uint32_t fw_type;
111 uint32_t fw_version;
112 uint32_t offset_bytes;
113 uint32_t size_bytes;
114};
115
116enum psp_fw_type {
117 PSP_FW_TYPE_UNKOWN,
118 PSP_FW_TYPE_PSP_SOS,
119 PSP_FW_TYPE_PSP_SYS_DRV,
120 PSP_FW_TYPE_PSP_KDB,
121 PSP_FW_TYPE_PSP_TOC,
122 PSP_FW_TYPE_PSP_SPL,
123 PSP_FW_TYPE_PSP_RL,
124 PSP_FW_TYPE_PSP_SOC_DRV,
125 PSP_FW_TYPE_PSP_INTF_DRV,
126 PSP_FW_TYPE_PSP_DBG_DRV,
127 PSP_FW_TYPE_PSP_RAS_DRV,
128 PSP_FW_TYPE_PSP_IPKEYMGR_DRV,
129 PSP_FW_TYPE_MAX_INDEX,
130};
131
132/* version_major=2, version_minor=0 */
133struct psp_firmware_header_v2_0 {
134 struct common_firmware_header header;
135 uint32_t psp_fw_bin_count;
136 struct psp_fw_bin_desc psp_fw_bin[];
137};
138
139/* version_major=2, version_minor=1 */
140struct psp_firmware_header_v2_1 {
141 struct common_firmware_header header;
142 uint32_t psp_fw_bin_count;
143 uint32_t psp_aux_fw_bin_index;
144 struct psp_fw_bin_desc psp_fw_bin[];
145};
146
147/* version_major=1, version_minor=0 */
148struct ta_firmware_header_v1_0 {
149 struct common_firmware_header header;
150 struct psp_fw_legacy_bin_desc xgmi;
151 struct psp_fw_legacy_bin_desc ras;
152 struct psp_fw_legacy_bin_desc hdcp;
153 struct psp_fw_legacy_bin_desc dtm;
154 struct psp_fw_legacy_bin_desc securedisplay;
155};
156
157enum ta_fw_type {
158 TA_FW_TYPE_UNKOWN,
159 TA_FW_TYPE_PSP_ASD,
160 TA_FW_TYPE_PSP_XGMI,
161 TA_FW_TYPE_PSP_RAS,
162 TA_FW_TYPE_PSP_HDCP,
163 TA_FW_TYPE_PSP_DTM,
164 TA_FW_TYPE_PSP_RAP,
165 TA_FW_TYPE_PSP_SECUREDISPLAY,
166 TA_FW_TYPE_MAX_INDEX,
167};
168
169/* version_major=2, version_minor=0 */
170struct ta_firmware_header_v2_0 {
171 struct common_firmware_header header;
172 uint32_t ta_fw_bin_count;
173 struct psp_fw_bin_desc ta_fw_bin[];
174};
175
176/* version_major=1, version_minor=0 */
177struct gfx_firmware_header_v1_0 {
178 struct common_firmware_header header;
179 uint32_t ucode_feature_version;
180 uint32_t jt_offset; /* jt location */
181 uint32_t jt_size; /* size of jt */
182};
183
184/* version_major=2, version_minor=0 */
185struct gfx_firmware_header_v2_0 {
186 struct common_firmware_header header;
187 uint32_t ucode_feature_version;
188 uint32_t ucode_size_bytes;
189 uint32_t ucode_offset_bytes;
190 uint32_t data_size_bytes;
191 uint32_t data_offset_bytes;
192 uint32_t ucode_start_addr_lo;
193 uint32_t ucode_start_addr_hi;
194};
195
196/* version_major=1, version_minor=0 */
197struct mes_firmware_header_v1_0 {
198 struct common_firmware_header header;
199 uint32_t mes_ucode_version;
200 uint32_t mes_ucode_size_bytes;
201 uint32_t mes_ucode_offset_bytes;
202 uint32_t mes_ucode_data_version;
203 uint32_t mes_ucode_data_size_bytes;
204 uint32_t mes_ucode_data_offset_bytes;
205 uint32_t mes_uc_start_addr_lo;
206 uint32_t mes_uc_start_addr_hi;
207 uint32_t mes_data_start_addr_lo;
208 uint32_t mes_data_start_addr_hi;
209};
210
211/* version_major=1, version_minor=0 */
212struct rlc_firmware_header_v1_0 {
213 struct common_firmware_header header;
214 uint32_t ucode_feature_version;
215 uint32_t save_and_restore_offset;
216 uint32_t clear_state_descriptor_offset;
217 uint32_t avail_scratch_ram_locations;
218 uint32_t master_pkt_description_offset;
219};
220
221/* version_major=2, version_minor=0 */
222struct rlc_firmware_header_v2_0 {
223 struct common_firmware_header header;
224 uint32_t ucode_feature_version;
225 uint32_t jt_offset; /* jt location */
226 uint32_t jt_size; /* size of jt */
227 uint32_t save_and_restore_offset;
228 uint32_t clear_state_descriptor_offset;
229 uint32_t avail_scratch_ram_locations;
230 uint32_t reg_restore_list_size;
231 uint32_t reg_list_format_start;
232 uint32_t reg_list_format_separate_start;
233 uint32_t starting_offsets_start;
234 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
235 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
236 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
237 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
238 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
239 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
240 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
241 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
242};
243
244/* version_major=2, version_minor=1 */
245struct rlc_firmware_header_v2_1 {
246 struct rlc_firmware_header_v2_0 v2_0;
247 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
248 uint32_t save_restore_list_cntl_ucode_ver;
249 uint32_t save_restore_list_cntl_feature_ver;
250 uint32_t save_restore_list_cntl_size_bytes;
251 uint32_t save_restore_list_cntl_offset_bytes;
252 uint32_t save_restore_list_gpm_ucode_ver;
253 uint32_t save_restore_list_gpm_feature_ver;
254 uint32_t save_restore_list_gpm_size_bytes;
255 uint32_t save_restore_list_gpm_offset_bytes;
256 uint32_t save_restore_list_srm_ucode_ver;
257 uint32_t save_restore_list_srm_feature_ver;
258 uint32_t save_restore_list_srm_size_bytes;
259 uint32_t save_restore_list_srm_offset_bytes;
260};
261
262/* version_major=2, version_minor=2 */
263struct rlc_firmware_header_v2_2 {
264 struct rlc_firmware_header_v2_1 v2_1;
265 uint32_t rlc_iram_ucode_size_bytes;
266 uint32_t rlc_iram_ucode_offset_bytes;
267 uint32_t rlc_dram_ucode_size_bytes;
268 uint32_t rlc_dram_ucode_offset_bytes;
269};
270
271/* version_major=2, version_minor=3 */
272struct rlc_firmware_header_v2_3 {
273 struct rlc_firmware_header_v2_2 v2_2;
274 uint32_t rlcp_ucode_version;
275 uint32_t rlcp_ucode_feature_version;
276 uint32_t rlcp_ucode_size_bytes;
277 uint32_t rlcp_ucode_offset_bytes;
278 uint32_t rlcv_ucode_version;
279 uint32_t rlcv_ucode_feature_version;
280 uint32_t rlcv_ucode_size_bytes;
281 uint32_t rlcv_ucode_offset_bytes;
282};
283
284/* version_major=2, version_minor=4 */
285struct rlc_firmware_header_v2_4 {
286 struct rlc_firmware_header_v2_3 v2_3;
287 uint32_t global_tap_delays_ucode_size_bytes;
288 uint32_t global_tap_delays_ucode_offset_bytes;
289 uint32_t se0_tap_delays_ucode_size_bytes;
290 uint32_t se0_tap_delays_ucode_offset_bytes;
291 uint32_t se1_tap_delays_ucode_size_bytes;
292 uint32_t se1_tap_delays_ucode_offset_bytes;
293 uint32_t se2_tap_delays_ucode_size_bytes;
294 uint32_t se2_tap_delays_ucode_offset_bytes;
295 uint32_t se3_tap_delays_ucode_size_bytes;
296 uint32_t se3_tap_delays_ucode_offset_bytes;
297};
298
299/* version_major=1, version_minor=0 */
300struct sdma_firmware_header_v1_0 {
301 struct common_firmware_header header;
302 uint32_t ucode_feature_version;
303 uint32_t ucode_change_version;
304 uint32_t jt_offset; /* jt location */
305 uint32_t jt_size; /* size of jt */
306};
307
308/* version_major=1, version_minor=1 */
309struct sdma_firmware_header_v1_1 {
310 struct sdma_firmware_header_v1_0 v1_0;
311 uint32_t digest_size;
312};
313
314/* version_major=2, version_minor=0 */
315struct sdma_firmware_header_v2_0 {
316 struct common_firmware_header header;
317 uint32_t ucode_feature_version;
318 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */
319 uint32_t ctx_jt_offset; /* context thread jt location */
320 uint32_t ctx_jt_size; /* context thread size of jt */
321 uint32_t ctl_ucode_offset;
322 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */
323 uint32_t ctl_jt_offset; /* control thread jt location */
324 uint32_t ctl_jt_size; /* control thread size of jt */
325};
326
327/* version_major=1, version_minor=0 */
328struct vpe_firmware_header_v1_0 {
329 struct common_firmware_header header;
330 uint32_t ucode_feature_version;
331 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */
332 uint32_t ctx_jt_offset; /* context thread jt location */
333 uint32_t ctx_jt_size; /* context thread size of jt */
334 uint32_t ctl_ucode_offset;
335 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */
336 uint32_t ctl_jt_offset; /* control thread jt location */
337 uint32_t ctl_jt_size; /* control thread size of jt */
338};
339
340/* version_major=1, version_minor=0 */
341struct umsch_mm_firmware_header_v1_0 {
342 struct common_firmware_header header;
343 uint32_t umsch_mm_ucode_version;
344 uint32_t umsch_mm_ucode_size_bytes;
345 uint32_t umsch_mm_ucode_offset_bytes;
346 uint32_t umsch_mm_ucode_data_version;
347 uint32_t umsch_mm_ucode_data_size_bytes;
348 uint32_t umsch_mm_ucode_data_offset_bytes;
349 uint32_t umsch_mm_irq_start_addr_lo;
350 uint32_t umsch_mm_irq_start_addr_hi;
351 uint32_t umsch_mm_uc_start_addr_lo;
352 uint32_t umsch_mm_uc_start_addr_hi;
353 uint32_t umsch_mm_data_start_addr_lo;
354 uint32_t umsch_mm_data_start_addr_hi;
355};
356
357/* version_major=3, version_minor=0 */
358struct sdma_firmware_header_v3_0 {
359 struct common_firmware_header header;
360 uint32_t ucode_feature_version;
361 uint32_t ucode_offset_bytes;
362 uint32_t ucode_size_bytes;
363};
364
365/* gpu info payload */
366struct gpu_info_firmware_v1_0 {
367 uint32_t gc_num_se;
368 uint32_t gc_num_cu_per_sh;
369 uint32_t gc_num_sh_per_se;
370 uint32_t gc_num_rb_per_se;
371 uint32_t gc_num_tccs;
372 uint32_t gc_num_gprs;
373 uint32_t gc_num_max_gs_thds;
374 uint32_t gc_gs_table_depth;
375 uint32_t gc_gsprim_buff_depth;
376 uint32_t gc_parameter_cache_depth;
377 uint32_t gc_double_offchip_lds_buffer;
378 uint32_t gc_wave_size;
379 uint32_t gc_max_waves_per_simd;
380 uint32_t gc_max_scratch_slots_per_cu;
381 uint32_t gc_lds_size;
382};
383
384struct gpu_info_firmware_v1_1 {
385 struct gpu_info_firmware_v1_0 v1_0;
386 uint32_t num_sc_per_sh;
387 uint32_t num_packer_per_sc;
388};
389
390/* gpu info payload
391 * version_major=1, version_minor=1 */
392struct gpu_info_firmware_v1_2 {
393 struct gpu_info_firmware_v1_1 v1_1;
394 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
395};
396
397/* version_major=1, version_minor=0 */
398struct gpu_info_firmware_header_v1_0 {
399 struct common_firmware_header header;
400 uint16_t version_major; /* version */
401 uint16_t version_minor; /* version */
402};
403
404/* version_major=1, version_minor=0 */
405struct dmcu_firmware_header_v1_0 {
406 struct common_firmware_header header;
407 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
408 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */
409};
410
411/* version_major=1, version_minor=0 */
412struct dmcub_firmware_header_v1_0 {
413 struct common_firmware_header header;
414 uint32_t inst_const_bytes; /* size of instruction region, in bytes */
415 uint32_t bss_data_bytes; /* size of bss/data region, in bytes */
416};
417
418/* version_major=1, version_minor=0 */
419struct imu_firmware_header_v1_0 {
420 struct common_firmware_header header;
421 uint32_t imu_iram_ucode_size_bytes;
422 uint32_t imu_iram_ucode_offset_bytes;
423 uint32_t imu_dram_ucode_size_bytes;
424 uint32_t imu_dram_ucode_offset_bytes;
425};
426
427/* header is fixed size */
428union amdgpu_firmware_header {
429 struct common_firmware_header common;
430 struct mc_firmware_header_v1_0 mc;
431 struct smc_firmware_header_v1_0 smc;
432 struct smc_firmware_header_v2_0 smc_v2_0;
433 struct psp_firmware_header_v1_0 psp;
434 struct psp_firmware_header_v1_1 psp_v1_1;
435 struct psp_firmware_header_v1_3 psp_v1_3;
436 struct psp_firmware_header_v2_0 psp_v2_0;
437 struct psp_firmware_header_v2_0 psp_v2_1;
438 struct ta_firmware_header_v1_0 ta;
439 struct ta_firmware_header_v2_0 ta_v2_0;
440 struct gfx_firmware_header_v1_0 gfx;
441 struct gfx_firmware_header_v2_0 gfx_v2_0;
442 struct rlc_firmware_header_v1_0 rlc;
443 struct rlc_firmware_header_v2_0 rlc_v2_0;
444 struct rlc_firmware_header_v2_1 rlc_v2_1;
445 struct rlc_firmware_header_v2_2 rlc_v2_2;
446 struct rlc_firmware_header_v2_3 rlc_v2_3;
447 struct rlc_firmware_header_v2_4 rlc_v2_4;
448 struct sdma_firmware_header_v1_0 sdma;
449 struct sdma_firmware_header_v1_1 sdma_v1_1;
450 struct sdma_firmware_header_v2_0 sdma_v2_0;
451 struct sdma_firmware_header_v3_0 sdma_v3_0;
452 struct gpu_info_firmware_header_v1_0 gpu_info;
453 struct dmcu_firmware_header_v1_0 dmcu;
454 struct dmcub_firmware_header_v1_0 dmcub;
455 struct imu_firmware_header_v1_0 imu;
456 uint8_t raw[0x100];
457};
458
459#define UCODE_MAX_PSP_PACKAGING (((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) * 2)
460
461/*
462 * fw loading support
463 */
464enum AMDGPU_UCODE_ID {
465 AMDGPU_UCODE_ID_CAP = 0,
466 AMDGPU_UCODE_ID_SDMA0,
467 AMDGPU_UCODE_ID_SDMA1,
468 AMDGPU_UCODE_ID_SDMA2,
469 AMDGPU_UCODE_ID_SDMA3,
470 AMDGPU_UCODE_ID_SDMA4,
471 AMDGPU_UCODE_ID_SDMA5,
472 AMDGPU_UCODE_ID_SDMA6,
473 AMDGPU_UCODE_ID_SDMA7,
474 AMDGPU_UCODE_ID_SDMA_UCODE_TH0,
475 AMDGPU_UCODE_ID_SDMA_UCODE_TH1,
476 AMDGPU_UCODE_ID_SDMA_RS64,
477 AMDGPU_UCODE_ID_CP_CE,
478 AMDGPU_UCODE_ID_CP_PFP,
479 AMDGPU_UCODE_ID_CP_ME,
480 AMDGPU_UCODE_ID_CP_RS64_PFP,
481 AMDGPU_UCODE_ID_CP_RS64_ME,
482 AMDGPU_UCODE_ID_CP_RS64_MEC,
483 AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK,
484 AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK,
485 AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK,
486 AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK,
487 AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK,
488 AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK,
489 AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK,
490 AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK,
491 AMDGPU_UCODE_ID_CP_MEC1,
492 AMDGPU_UCODE_ID_CP_MEC1_JT,
493 AMDGPU_UCODE_ID_CP_MEC2,
494 AMDGPU_UCODE_ID_CP_MEC2_JT,
495 AMDGPU_UCODE_ID_CP_MES,
496 AMDGPU_UCODE_ID_CP_MES_DATA,
497 AMDGPU_UCODE_ID_CP_MES1,
498 AMDGPU_UCODE_ID_CP_MES1_DATA,
499 AMDGPU_UCODE_ID_IMU_I,
500 AMDGPU_UCODE_ID_IMU_D,
501 AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS,
502 AMDGPU_UCODE_ID_SE0_TAP_DELAYS,
503 AMDGPU_UCODE_ID_SE1_TAP_DELAYS,
504 AMDGPU_UCODE_ID_SE2_TAP_DELAYS,
505 AMDGPU_UCODE_ID_SE3_TAP_DELAYS,
506 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
507 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
508 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
509 AMDGPU_UCODE_ID_RLC_IRAM,
510 AMDGPU_UCODE_ID_RLC_DRAM,
511 AMDGPU_UCODE_ID_RLC_P,
512 AMDGPU_UCODE_ID_RLC_V,
513 AMDGPU_UCODE_ID_RLC_G,
514 AMDGPU_UCODE_ID_STORAGE,
515 AMDGPU_UCODE_ID_SMC,
516 AMDGPU_UCODE_ID_PPTABLE,
517 AMDGPU_UCODE_ID_UVD,
518 AMDGPU_UCODE_ID_UVD1,
519 AMDGPU_UCODE_ID_VCE,
520 AMDGPU_UCODE_ID_VCN,
521 AMDGPU_UCODE_ID_VCN1,
522 AMDGPU_UCODE_ID_DMCU_ERAM,
523 AMDGPU_UCODE_ID_DMCU_INTV,
524 AMDGPU_UCODE_ID_VCN0_RAM,
525 AMDGPU_UCODE_ID_VCN1_RAM,
526 AMDGPU_UCODE_ID_DMCUB,
527 AMDGPU_UCODE_ID_VPE_CTX,
528 AMDGPU_UCODE_ID_VPE_CTL,
529 AMDGPU_UCODE_ID_VPE,
530 AMDGPU_UCODE_ID_UMSCH_MM_UCODE,
531 AMDGPU_UCODE_ID_UMSCH_MM_DATA,
532 AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER,
533 AMDGPU_UCODE_ID_P2S_TABLE,
534 AMDGPU_UCODE_ID_JPEG_RAM,
535 AMDGPU_UCODE_ID_ISP,
536 AMDGPU_UCODE_ID_MAXIMUM,
537};
538
539/* engine firmware status */
540enum AMDGPU_UCODE_STATUS {
541 AMDGPU_UCODE_STATUS_INVALID,
542 AMDGPU_UCODE_STATUS_NOT_LOADED,
543 AMDGPU_UCODE_STATUS_LOADED,
544};
545
546enum amdgpu_firmware_load_type {
547 AMDGPU_FW_LOAD_DIRECT = 0,
548 AMDGPU_FW_LOAD_PSP,
549 AMDGPU_FW_LOAD_SMU,
550 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
551};
552
553/* conform to smu_ucode_xfer_cz.h */
554#define AMDGPU_SDMA0_UCODE_LOADED 0x00000001
555#define AMDGPU_SDMA1_UCODE_LOADED 0x00000002
556#define AMDGPU_CPCE_UCODE_LOADED 0x00000004
557#define AMDGPU_CPPFP_UCODE_LOADED 0x00000008
558#define AMDGPU_CPME_UCODE_LOADED 0x00000010
559#define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020
560#define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040
561#define AMDGPU_CPRLC_UCODE_LOADED 0x00000100
562
563/* amdgpu firmware info */
564struct amdgpu_firmware_info {
565 /* ucode ID */
566 enum AMDGPU_UCODE_ID ucode_id;
567 /* request_firmware */
568 const struct firmware *fw;
569 /* starting mc address */
570 uint64_t mc_addr;
571 /* kernel linear address */
572 void *kaddr;
573 /* ucode_size_bytes */
574 uint32_t ucode_size;
575 /* starting tmr mc address */
576 uint32_t tmr_mc_addr_lo;
577 uint32_t tmr_mc_addr_hi;
578};
579
580struct amdgpu_firmware {
581 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
582 enum amdgpu_firmware_load_type load_type;
583 struct amdgpu_bo *fw_buf;
584 unsigned int fw_size;
585 unsigned int max_ucodes;
586 /* firmwares are loaded by psp instead of smu from vega10 */
587 const struct amdgpu_psp_funcs *funcs;
588 struct amdgpu_bo *rbuf;
589 struct mutex mutex;
590
591 /* gpu info firmware data pointer */
592 const struct firmware *gpu_info_fw;
593
594 void *fw_buf_ptr;
595 uint64_t fw_buf_mc;
596};
597
598void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
599void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
600void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr);
601void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
602void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
603void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
604void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
605void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
606__printf(3, 4)
607int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,
608 const char *fmt, ...);
609void amdgpu_ucode_release(const struct firmware **fw);
610bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
611 uint16_t hdr_major, uint16_t hdr_minor);
612
613int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
614int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
615int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
616void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
617void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
618
619enum amdgpu_firmware_load_type
620amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
621
622const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id);
623
624void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len);
625
626#endif