Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#ifdef pr_fmt
32#undef pr_fmt
33#endif
34
35#define pr_fmt(fmt) "amdgpu: " fmt
36
37#ifdef dev_fmt
38#undef dev_fmt
39#endif
40
41#define dev_fmt(fmt) "amdgpu: " fmt
42
43#include "amdgpu_ctx.h"
44
45#include <linux/atomic.h>
46#include <linux/wait.h>
47#include <linux/list.h>
48#include <linux/kref.h>
49#include <linux/rbtree.h>
50#include <linux/hashtable.h>
51#include <linux/dma-fence.h>
52#include <linux/pci.h>
53
54#include <drm/ttm/ttm_bo.h>
55#include <drm/ttm/ttm_placement.h>
56
57#include <drm/amdgpu_drm.h>
58#include <drm/drm_gem.h>
59#include <drm/drm_ioctl.h>
60
61#include <kgd_kfd_interface.h>
62#include "dm_pp_interface.h"
63#include "kgd_pp_interface.h"
64
65#include "amd_shared.h"
66#include "amdgpu_mode.h"
67#include "amdgpu_ih.h"
68#include "amdgpu_irq.h"
69#include "amdgpu_ucode.h"
70#include "amdgpu_ttm.h"
71#include "amdgpu_psp.h"
72#include "amdgpu_gds.h"
73#include "amdgpu_sync.h"
74#include "amdgpu_ring.h"
75#include "amdgpu_vm.h"
76#include "amdgpu_dpm.h"
77#include "amdgpu_acp.h"
78#include "amdgpu_uvd.h"
79#include "amdgpu_vce.h"
80#include "amdgpu_vcn.h"
81#include "amdgpu_jpeg.h"
82#include "amdgpu_vpe.h"
83#include "amdgpu_umsch_mm.h"
84#include "amdgpu_gmc.h"
85#include "amdgpu_gfx.h"
86#include "amdgpu_sdma.h"
87#include "amdgpu_lsdma.h"
88#include "amdgpu_nbio.h"
89#include "amdgpu_hdp.h"
90#include "amdgpu_dm.h"
91#include "amdgpu_virt.h"
92#include "amdgpu_csa.h"
93#include "amdgpu_mes_ctx.h"
94#include "amdgpu_gart.h"
95#include "amdgpu_debugfs.h"
96#include "amdgpu_job.h"
97#include "amdgpu_bo_list.h"
98#include "amdgpu_gem.h"
99#include "amdgpu_doorbell.h"
100#include "amdgpu_amdkfd.h"
101#include "amdgpu_discovery.h"
102#include "amdgpu_mes.h"
103#include "amdgpu_umc.h"
104#include "amdgpu_mmhub.h"
105#include "amdgpu_gfxhub.h"
106#include "amdgpu_df.h"
107#include "amdgpu_smuio.h"
108#include "amdgpu_fdinfo.h"
109#include "amdgpu_mca.h"
110#include "amdgpu_aca.h"
111#include "amdgpu_ras.h"
112#include "amdgpu_xcp.h"
113#include "amdgpu_seq64.h"
114#include "amdgpu_reg_state.h"
115#if defined(CONFIG_DRM_AMD_ISP)
116#include "amdgpu_isp.h"
117#endif
118
119#define MAX_GPU_INSTANCE 64
120
121#define GFX_SLICE_PERIOD msecs_to_jiffies(250)
122
123struct amdgpu_gpu_instance {
124 struct amdgpu_device *adev;
125 int mgpu_fan_enabled;
126};
127
128struct amdgpu_mgpu_info {
129 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
130 struct mutex mutex;
131 uint32_t num_gpu;
132 uint32_t num_dgpu;
133 uint32_t num_apu;
134
135 /* delayed reset_func for XGMI configuration if necessary */
136 struct delayed_work delayed_reset_work;
137 bool pending_reset;
138};
139
140enum amdgpu_ss {
141 AMDGPU_SS_DRV_LOAD,
142 AMDGPU_SS_DEV_D0,
143 AMDGPU_SS_DEV_D3,
144 AMDGPU_SS_DRV_UNLOAD
145};
146
147struct amdgpu_hwip_reg_entry {
148 u32 hwip;
149 u32 inst;
150 u32 seg;
151 u32 reg_offset;
152 const char *reg_name;
153};
154
155struct amdgpu_watchdog_timer {
156 bool timeout_fatal_disable;
157 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
158};
159
160#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
161
162/*
163 * Modules parameters.
164 */
165extern int amdgpu_modeset;
166extern unsigned int amdgpu_vram_limit;
167extern int amdgpu_vis_vram_limit;
168extern int amdgpu_gart_size;
169extern int amdgpu_gtt_size;
170extern int amdgpu_moverate;
171extern int amdgpu_audio;
172extern int amdgpu_disp_priority;
173extern int amdgpu_hw_i2c;
174extern int amdgpu_pcie_gen2;
175extern int amdgpu_msi;
176extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
177extern int amdgpu_dpm;
178extern int amdgpu_fw_load_type;
179extern int amdgpu_aspm;
180extern int amdgpu_runtime_pm;
181extern uint amdgpu_ip_block_mask;
182extern int amdgpu_bapm;
183extern int amdgpu_deep_color;
184extern int amdgpu_vm_size;
185extern int amdgpu_vm_block_size;
186extern int amdgpu_vm_fragment_size;
187extern int amdgpu_vm_fault_stop;
188extern int amdgpu_vm_debug;
189extern int amdgpu_vm_update_mode;
190extern int amdgpu_exp_hw_support;
191extern int amdgpu_dc;
192extern int amdgpu_sched_jobs;
193extern int amdgpu_sched_hw_submission;
194extern uint amdgpu_pcie_gen_cap;
195extern uint amdgpu_pcie_lane_cap;
196extern u64 amdgpu_cg_mask;
197extern uint amdgpu_pg_mask;
198extern uint amdgpu_sdma_phase_quantum;
199extern char *amdgpu_disable_cu;
200extern char *amdgpu_virtual_display;
201extern uint amdgpu_pp_feature_mask;
202extern uint amdgpu_force_long_training;
203extern int amdgpu_lbpw;
204extern int amdgpu_compute_multipipe;
205extern int amdgpu_gpu_recovery;
206extern int amdgpu_emu_mode;
207extern uint amdgpu_smu_memory_pool_size;
208extern int amdgpu_smu_pptable_id;
209extern uint amdgpu_dc_feature_mask;
210extern uint amdgpu_freesync_vid_mode;
211extern uint amdgpu_dc_debug_mask;
212extern uint amdgpu_dc_visual_confirm;
213extern int amdgpu_dm_abm_level;
214extern int amdgpu_backlight;
215extern int amdgpu_damage_clips;
216extern struct amdgpu_mgpu_info mgpu_info;
217extern int amdgpu_ras_enable;
218extern uint amdgpu_ras_mask;
219extern int amdgpu_bad_page_threshold;
220extern bool amdgpu_ignore_bad_page_threshold;
221extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
222extern int amdgpu_async_gfx_ring;
223extern int amdgpu_mcbp;
224extern int amdgpu_discovery;
225extern int amdgpu_mes;
226extern int amdgpu_mes_log_enable;
227extern int amdgpu_mes_kiq;
228extern int amdgpu_uni_mes;
229extern int amdgpu_noretry;
230extern int amdgpu_force_asic_type;
231extern int amdgpu_smartshift_bias;
232extern int amdgpu_use_xgmi_p2p;
233extern int amdgpu_mtype_local;
234extern bool enforce_isolation;
235#ifdef CONFIG_HSA_AMD
236extern int sched_policy;
237extern bool debug_evictions;
238extern bool no_system_mem_limit;
239extern int halt_if_hws_hang;
240extern uint amdgpu_svm_default_granularity;
241#else
242static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
243static const bool __maybe_unused debug_evictions; /* = false */
244static const bool __maybe_unused no_system_mem_limit;
245static const int __maybe_unused halt_if_hws_hang;
246#endif
247#ifdef CONFIG_HSA_AMD_P2P
248extern bool pcie_p2p;
249#endif
250
251extern int amdgpu_tmz;
252extern int amdgpu_reset_method;
253
254#ifdef CONFIG_DRM_AMDGPU_SI
255extern int amdgpu_si_support;
256#endif
257#ifdef CONFIG_DRM_AMDGPU_CIK
258extern int amdgpu_cik_support;
259#endif
260extern int amdgpu_num_kcq;
261
262#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
263#define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024)
264extern int amdgpu_vcnfw_log;
265extern int amdgpu_sg_display;
266extern int amdgpu_umsch_mm;
267extern int amdgpu_seamless;
268extern int amdgpu_umsch_mm_fwlog;
269
270extern int amdgpu_user_partt_mode;
271extern int amdgpu_agp;
272
273extern int amdgpu_wbrf;
274
275#define AMDGPU_VM_MAX_NUM_CTX 4096
276#define AMDGPU_SG_THRESHOLD (256*1024*1024)
277#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
278#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
279#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
280#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
281#define AMDGPUFB_CONN_LIMIT 4
282#define AMDGPU_BIOS_NUM_SCRATCH 16
283
284#define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
285
286/* hard reset data */
287#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
288
289/* reset flags */
290#define AMDGPU_RESET_GFX (1 << 0)
291#define AMDGPU_RESET_COMPUTE (1 << 1)
292#define AMDGPU_RESET_DMA (1 << 2)
293#define AMDGPU_RESET_CP (1 << 3)
294#define AMDGPU_RESET_GRBM (1 << 4)
295#define AMDGPU_RESET_DMA1 (1 << 5)
296#define AMDGPU_RESET_RLC (1 << 6)
297#define AMDGPU_RESET_SEM (1 << 7)
298#define AMDGPU_RESET_IH (1 << 8)
299#define AMDGPU_RESET_VMC (1 << 9)
300#define AMDGPU_RESET_MC (1 << 10)
301#define AMDGPU_RESET_DISPLAY (1 << 11)
302#define AMDGPU_RESET_UVD (1 << 12)
303#define AMDGPU_RESET_VCE (1 << 13)
304#define AMDGPU_RESET_VCE1 (1 << 14)
305
306/* max cursor sizes (in pixels) */
307#define CIK_CURSOR_WIDTH 128
308#define CIK_CURSOR_HEIGHT 128
309
310/* smart shift bias level limits */
311#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
312#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
313
314/* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
315#define AMDGPU_SWCTF_EXTRA_DELAY 50
316
317struct amdgpu_xcp_mgr;
318struct amdgpu_device;
319struct amdgpu_irq_src;
320struct amdgpu_fpriv;
321struct amdgpu_bo_va_mapping;
322struct kfd_vm_fault_info;
323struct amdgpu_hive_info;
324struct amdgpu_reset_context;
325struct amdgpu_reset_control;
326
327enum amdgpu_cp_irq {
328 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
329 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
330 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
331 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
332 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
333 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
334 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
335 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
336 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
337 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
338
339 AMDGPU_CP_IRQ_LAST
340};
341
342enum amdgpu_thermal_irq {
343 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
344 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
345
346 AMDGPU_THERMAL_IRQ_LAST
347};
348
349enum amdgpu_kiq_irq {
350 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
351 AMDGPU_CP_KIQ_IRQ_LAST
352};
353#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
354#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
355#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
356#define MAX_KIQ_REG_TRY 1000
357
358int amdgpu_device_ip_set_clockgating_state(void *dev,
359 enum amd_ip_block_type block_type,
360 enum amd_clockgating_state state);
361int amdgpu_device_ip_set_powergating_state(void *dev,
362 enum amd_ip_block_type block_type,
363 enum amd_powergating_state state);
364void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
365 u64 *flags);
366int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
367 enum amd_ip_block_type block_type);
368bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
369 enum amd_ip_block_type block_type);
370
371#define AMDGPU_MAX_IP_NUM 16
372
373struct amdgpu_ip_block_status {
374 bool valid;
375 bool sw;
376 bool hw;
377 bool late_initialized;
378 bool hang;
379};
380
381struct amdgpu_ip_block_version {
382 const enum amd_ip_block_type type;
383 const u32 major;
384 const u32 minor;
385 const u32 rev;
386 const struct amd_ip_funcs *funcs;
387};
388
389struct amdgpu_ip_block {
390 struct amdgpu_ip_block_status status;
391 const struct amdgpu_ip_block_version *version;
392};
393
394int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
395 enum amd_ip_block_type type,
396 u32 major, u32 minor);
397
398struct amdgpu_ip_block *
399amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
400 enum amd_ip_block_type type);
401
402int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
403 const struct amdgpu_ip_block_version *ip_block_version);
404
405/*
406 * BIOS.
407 */
408bool amdgpu_get_bios(struct amdgpu_device *adev);
409bool amdgpu_read_bios(struct amdgpu_device *adev);
410bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
411 u8 *bios, u32 length_bytes);
412/*
413 * Clocks
414 */
415
416#define AMDGPU_MAX_PPLL 3
417
418struct amdgpu_clock {
419 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
420 struct amdgpu_pll spll;
421 struct amdgpu_pll mpll;
422 /* 10 Khz units */
423 uint32_t default_mclk;
424 uint32_t default_sclk;
425 uint32_t default_dispclk;
426 uint32_t current_dispclk;
427 uint32_t dp_extclk;
428 uint32_t max_pixel_clock;
429};
430
431/* sub-allocation manager, it has to be protected by another lock.
432 * By conception this is an helper for other part of the driver
433 * like the indirect buffer or semaphore, which both have their
434 * locking.
435 *
436 * Principe is simple, we keep a list of sub allocation in offset
437 * order (first entry has offset == 0, last entry has the highest
438 * offset).
439 *
440 * When allocating new object we first check if there is room at
441 * the end total_size - (last_object_offset + last_object_size) >=
442 * alloc_size. If so we allocate new object there.
443 *
444 * When there is not enough room at the end, we start waiting for
445 * each sub object until we reach object_offset+object_size >=
446 * alloc_size, this object then become the sub object we return.
447 *
448 * Alignment can't be bigger than page size.
449 *
450 * Hole are not considered for allocation to keep things simple.
451 * Assumption is that there won't be hole (all object on same
452 * alignment).
453 */
454
455struct amdgpu_sa_manager {
456 struct drm_suballoc_manager base;
457 struct amdgpu_bo *bo;
458 uint64_t gpu_addr;
459 void *cpu_ptr;
460};
461
462int amdgpu_fence_slab_init(void);
463void amdgpu_fence_slab_fini(void);
464
465/*
466 * IRQS.
467 */
468
469struct amdgpu_flip_work {
470 struct delayed_work flip_work;
471 struct work_struct unpin_work;
472 struct amdgpu_device *adev;
473 int crtc_id;
474 u32 target_vblank;
475 uint64_t base;
476 struct drm_pending_vblank_event *event;
477 struct amdgpu_bo *old_abo;
478 unsigned shared_count;
479 struct dma_fence **shared;
480 struct dma_fence_cb cb;
481 bool async;
482};
483
484
485/*
486 * file private structure
487 */
488
489struct amdgpu_fpriv {
490 struct amdgpu_vm vm;
491 struct amdgpu_bo_va *prt_va;
492 struct amdgpu_bo_va *csa_va;
493 struct amdgpu_bo_va *seq64_va;
494 struct mutex bo_list_lock;
495 struct idr bo_list_handles;
496 struct amdgpu_ctx_mgr ctx_mgr;
497 /** GPU partition selection */
498 uint32_t xcp_id;
499};
500
501int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
502
503/*
504 * Writeback
505 */
506#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
507
508struct amdgpu_wb {
509 struct amdgpu_bo *wb_obj;
510 volatile uint32_t *wb;
511 uint64_t gpu_addr;
512 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
513 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
514 spinlock_t lock;
515};
516
517int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
518void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
519
520/*
521 * Benchmarking
522 */
523int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
524
525/*
526 * ASIC specific register table accessible by UMD
527 */
528struct amdgpu_allowed_register_entry {
529 uint32_t reg_offset;
530 bool grbm_indexed;
531};
532
533/**
534 * enum amd_reset_method - Methods for resetting AMD GPU devices
535 *
536 * @AMD_RESET_METHOD_NONE: The device will not be reset.
537 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs.
538 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the
539 * any device.
540 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.)
541 * individually. Suitable only for some discrete GPU, not
542 * available for all ASICs.
543 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs
544 * are reset depends on the ASIC. Notably doesn't reset IPs
545 * shared with the CPU on APUs or the memory controllers (so
546 * VRAM is not lost). Not available on all ASICs.
547 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card
548 * but without powering off the PCI bus. Suitable only for
549 * discrete GPUs.
550 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset
551 * and does a secondary bus reset or FLR, depending on what the
552 * underlying hardware supports.
553 *
554 * Methods available for AMD GPU driver for resetting the device. Not all
555 * methods are suitable for every device. User can override the method using
556 * module parameter `reset_method`.
557 */
558enum amd_reset_method {
559 AMD_RESET_METHOD_NONE = -1,
560 AMD_RESET_METHOD_LEGACY = 0,
561 AMD_RESET_METHOD_MODE0,
562 AMD_RESET_METHOD_MODE1,
563 AMD_RESET_METHOD_MODE2,
564 AMD_RESET_METHOD_BACO,
565 AMD_RESET_METHOD_PCI,
566};
567
568struct amdgpu_video_codec_info {
569 u32 codec_type;
570 u32 max_width;
571 u32 max_height;
572 u32 max_pixels_per_frame;
573 u32 max_level;
574};
575
576#define codec_info_build(type, width, height, level) \
577 .codec_type = type,\
578 .max_width = width,\
579 .max_height = height,\
580 .max_pixels_per_frame = height * width,\
581 .max_level = level,
582
583struct amdgpu_video_codecs {
584 const u32 codec_count;
585 const struct amdgpu_video_codec_info *codec_array;
586};
587
588/*
589 * ASIC specific functions.
590 */
591struct amdgpu_asic_funcs {
592 bool (*read_disabled_bios)(struct amdgpu_device *adev);
593 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
594 u8 *bios, u32 length_bytes);
595 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
596 u32 sh_num, u32 reg_offset, u32 *value);
597 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
598 int (*reset)(struct amdgpu_device *adev);
599 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
600 /* get the reference clock */
601 u32 (*get_xclk)(struct amdgpu_device *adev);
602 /* MM block clocks */
603 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
604 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
605 /* static power management */
606 int (*get_pcie_lanes)(struct amdgpu_device *adev);
607 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
608 /* get config memsize register */
609 u32 (*get_config_memsize)(struct amdgpu_device *adev);
610 /* flush hdp write queue */
611 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
612 /* invalidate hdp read cache */
613 void (*invalidate_hdp)(struct amdgpu_device *adev,
614 struct amdgpu_ring *ring);
615 /* check if the asic needs a full reset of if soft reset will work */
616 bool (*need_full_reset)(struct amdgpu_device *adev);
617 /* initialize doorbell layout for specific asic*/
618 void (*init_doorbell_index)(struct amdgpu_device *adev);
619 /* PCIe bandwidth usage */
620 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
621 uint64_t *count1);
622 /* do we need to reset the asic at init time (e.g., kexec) */
623 bool (*need_reset_on_init)(struct amdgpu_device *adev);
624 /* PCIe replay counter */
625 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
626 /* device supports BACO */
627 int (*supports_baco)(struct amdgpu_device *adev);
628 /* pre asic_init quirks */
629 void (*pre_asic_init)(struct amdgpu_device *adev);
630 /* enter/exit umd stable pstate */
631 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
632 /* query video codecs */
633 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
634 const struct amdgpu_video_codecs **codecs);
635 /* encode "> 32bits" smn addressing */
636 u64 (*encode_ext_smn_addressing)(int ext_id);
637
638 ssize_t (*get_reg_state)(struct amdgpu_device *adev,
639 enum amdgpu_reg_state reg_state, void *buf,
640 size_t max_size);
641};
642
643/*
644 * IOCTL.
645 */
646int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
647 struct drm_file *filp);
648
649int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
650int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
651 struct drm_file *filp);
652int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
653int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
654 struct drm_file *filp);
655
656/* VRAM scratch page for HDP bug, default vram page */
657struct amdgpu_mem_scratch {
658 struct amdgpu_bo *robj;
659 volatile uint32_t *ptr;
660 u64 gpu_addr;
661};
662
663/*
664 * CGS
665 */
666struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
667void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
668
669/*
670 * Core structure, functions and helpers.
671 */
672typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
673typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
674
675typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);
676typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);
677
678typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
679typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
680
681typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t);
682typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t);
683
684typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
685typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
686
687struct amdgpu_mmio_remap {
688 u32 reg_offset;
689 resource_size_t bus_addr;
690};
691
692/* Define the HW IP blocks will be used in driver , add more if necessary */
693enum amd_hw_ip_block_type {
694 GC_HWIP = 1,
695 HDP_HWIP,
696 SDMA0_HWIP,
697 SDMA1_HWIP,
698 SDMA2_HWIP,
699 SDMA3_HWIP,
700 SDMA4_HWIP,
701 SDMA5_HWIP,
702 SDMA6_HWIP,
703 SDMA7_HWIP,
704 LSDMA_HWIP,
705 MMHUB_HWIP,
706 ATHUB_HWIP,
707 NBIO_HWIP,
708 MP0_HWIP,
709 MP1_HWIP,
710 UVD_HWIP,
711 VCN_HWIP = UVD_HWIP,
712 JPEG_HWIP = VCN_HWIP,
713 VCN1_HWIP,
714 VCE_HWIP,
715 VPE_HWIP,
716 DF_HWIP,
717 DCE_HWIP,
718 OSSSYS_HWIP,
719 SMUIO_HWIP,
720 PWR_HWIP,
721 NBIF_HWIP,
722 THM_HWIP,
723 CLK_HWIP,
724 UMC_HWIP,
725 RSMU_HWIP,
726 XGMI_HWIP,
727 DCI_HWIP,
728 PCIE_HWIP,
729 ISP_HWIP,
730 MAX_HWIP
731};
732
733#define HWIP_MAX_INSTANCE 44
734
735#define HW_ID_MAX 300
736#define IP_VERSION_FULL(mj, mn, rv, var, srev) \
737 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev))
738#define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0)
739#define IP_VERSION_MAJ(ver) ((ver) >> 24)
740#define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF)
741#define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF)
742#define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF)
743#define IP_VERSION_SUBREV(ver) ((ver) & 0xF)
744#define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8)
745
746struct amdgpu_ip_map_info {
747 /* Map of logical to actual dev instances/mask */
748 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];
749 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
750 enum amd_hw_ip_block_type block,
751 int8_t inst);
752 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
753 enum amd_hw_ip_block_type block,
754 uint32_t mask);
755};
756
757struct amd_powerplay {
758 void *pp_handle;
759 const struct amd_pm_funcs *pp_funcs;
760};
761
762struct ip_discovery_top;
763
764/* polaris10 kickers */
765#define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
766 ((rid == 0xE3) || \
767 (rid == 0xE4) || \
768 (rid == 0xE5) || \
769 (rid == 0xE7) || \
770 (rid == 0xEF))) || \
771 ((did == 0x6FDF) && \
772 ((rid == 0xE7) || \
773 (rid == 0xEF) || \
774 (rid == 0xFF))))
775
776#define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
777 ((rid == 0xE1) || \
778 (rid == 0xF7)))
779
780/* polaris11 kickers */
781#define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
782 ((rid == 0xE0) || \
783 (rid == 0xE5))) || \
784 ((did == 0x67FF) && \
785 ((rid == 0xCF) || \
786 (rid == 0xEF) || \
787 (rid == 0xFF))))
788
789#define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
790 ((rid == 0xE2)))
791
792/* polaris12 kickers */
793#define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
794 ((rid == 0xC0) || \
795 (rid == 0xC1) || \
796 (rid == 0xC3) || \
797 (rid == 0xC7))) || \
798 ((did == 0x6981) && \
799 ((rid == 0x00) || \
800 (rid == 0x01) || \
801 (rid == 0x10))))
802
803struct amdgpu_mqd_prop {
804 uint64_t mqd_gpu_addr;
805 uint64_t hqd_base_gpu_addr;
806 uint64_t rptr_gpu_addr;
807 uint64_t wptr_gpu_addr;
808 uint32_t queue_size;
809 bool use_doorbell;
810 uint32_t doorbell_index;
811 uint64_t eop_gpu_addr;
812 uint32_t hqd_pipe_priority;
813 uint32_t hqd_queue_priority;
814 bool allow_tunneling;
815 bool hqd_active;
816};
817
818struct amdgpu_mqd {
819 unsigned mqd_size;
820 int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
821 struct amdgpu_mqd_prop *p);
822};
823
824#define AMDGPU_RESET_MAGIC_NUM 64
825#define AMDGPU_MAX_DF_PERFMONS 4
826struct amdgpu_reset_domain;
827struct amdgpu_fru_info;
828
829/*
830 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
831 */
832#define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
833
834struct amdgpu_device {
835 struct device *dev;
836 struct pci_dev *pdev;
837 struct drm_device ddev;
838
839#ifdef CONFIG_DRM_AMD_ACP
840 struct amdgpu_acp acp;
841#endif
842 struct amdgpu_hive_info *hive;
843 struct amdgpu_xcp_mgr *xcp_mgr;
844 /* ASIC */
845 enum amd_asic_type asic_type;
846 uint32_t family;
847 uint32_t rev_id;
848 uint32_t external_rev_id;
849 unsigned long flags;
850 unsigned long apu_flags;
851 int usec_timeout;
852 const struct amdgpu_asic_funcs *asic_funcs;
853 bool shutdown;
854 bool need_swiotlb;
855 bool accel_working;
856 struct notifier_block acpi_nb;
857 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
858 struct debugfs_blob_wrapper debugfs_vbios_blob;
859 struct debugfs_blob_wrapper debugfs_discovery_blob;
860 struct mutex srbm_mutex;
861 /* GRBM index mutex. Protects concurrent access to GRBM index */
862 struct mutex grbm_idx_mutex;
863 struct dev_pm_domain vga_pm_domain;
864 bool have_disp_power_ref;
865 bool have_atomics_support;
866
867 /* BIOS */
868 bool is_atom_fw;
869 uint8_t *bios;
870 uint32_t bios_size;
871 uint32_t bios_scratch_reg_offset;
872 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
873
874 /* Register/doorbell mmio */
875 resource_size_t rmmio_base;
876 resource_size_t rmmio_size;
877 void __iomem *rmmio;
878 /* protects concurrent MM_INDEX/DATA based register access */
879 spinlock_t mmio_idx_lock;
880 struct amdgpu_mmio_remap rmmio_remap;
881 /* protects concurrent SMC based register access */
882 spinlock_t smc_idx_lock;
883 amdgpu_rreg_t smc_rreg;
884 amdgpu_wreg_t smc_wreg;
885 /* protects concurrent PCIE register access */
886 spinlock_t pcie_idx_lock;
887 amdgpu_rreg_t pcie_rreg;
888 amdgpu_wreg_t pcie_wreg;
889 amdgpu_rreg_t pciep_rreg;
890 amdgpu_wreg_t pciep_wreg;
891 amdgpu_rreg_ext_t pcie_rreg_ext;
892 amdgpu_wreg_ext_t pcie_wreg_ext;
893 amdgpu_rreg64_t pcie_rreg64;
894 amdgpu_wreg64_t pcie_wreg64;
895 amdgpu_rreg64_ext_t pcie_rreg64_ext;
896 amdgpu_wreg64_ext_t pcie_wreg64_ext;
897 /* protects concurrent UVD register access */
898 spinlock_t uvd_ctx_idx_lock;
899 amdgpu_rreg_t uvd_ctx_rreg;
900 amdgpu_wreg_t uvd_ctx_wreg;
901 /* protects concurrent DIDT register access */
902 spinlock_t didt_idx_lock;
903 amdgpu_rreg_t didt_rreg;
904 amdgpu_wreg_t didt_wreg;
905 /* protects concurrent gc_cac register access */
906 spinlock_t gc_cac_idx_lock;
907 amdgpu_rreg_t gc_cac_rreg;
908 amdgpu_wreg_t gc_cac_wreg;
909 /* protects concurrent se_cac register access */
910 spinlock_t se_cac_idx_lock;
911 amdgpu_rreg_t se_cac_rreg;
912 amdgpu_wreg_t se_cac_wreg;
913 /* protects concurrent ENDPOINT (audio) register access */
914 spinlock_t audio_endpt_idx_lock;
915 amdgpu_block_rreg_t audio_endpt_rreg;
916 amdgpu_block_wreg_t audio_endpt_wreg;
917 struct amdgpu_doorbell doorbell;
918
919 /* clock/pll info */
920 struct amdgpu_clock clock;
921
922 /* MC */
923 struct amdgpu_gmc gmc;
924 struct amdgpu_gart gart;
925 dma_addr_t dummy_page_addr;
926 struct amdgpu_vm_manager vm_manager;
927 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
928 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
929
930 /* memory management */
931 struct amdgpu_mman mman;
932 struct amdgpu_mem_scratch mem_scratch;
933 struct amdgpu_wb wb;
934 atomic64_t num_bytes_moved;
935 atomic64_t num_evictions;
936 atomic64_t num_vram_cpu_page_faults;
937 atomic_t gpu_reset_counter;
938 atomic_t vram_lost_counter;
939
940 /* data for buffer migration throttling */
941 struct {
942 spinlock_t lock;
943 s64 last_update_us;
944 s64 accum_us; /* accumulated microseconds */
945 s64 accum_us_vis; /* for visible VRAM */
946 u32 log2_max_MBps;
947 } mm_stats;
948
949 /* display */
950 bool enable_virtual_display;
951 struct amdgpu_vkms_output *amdgpu_vkms_output;
952 struct amdgpu_mode_info mode_info;
953 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
954 struct delayed_work hotplug_work;
955 struct amdgpu_irq_src crtc_irq;
956 struct amdgpu_irq_src vline0_irq;
957 struct amdgpu_irq_src vupdate_irq;
958 struct amdgpu_irq_src pageflip_irq;
959 struct amdgpu_irq_src hpd_irq;
960 struct amdgpu_irq_src dmub_trace_irq;
961 struct amdgpu_irq_src dmub_outbox_irq;
962
963 /* rings */
964 u64 fence_context;
965 unsigned num_rings;
966 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
967 struct dma_fence __rcu *gang_submit;
968 bool ib_pool_ready;
969 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
970 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
971
972 /* interrupts */
973 struct amdgpu_irq irq;
974
975 /* powerplay */
976 struct amd_powerplay powerplay;
977 struct amdgpu_pm pm;
978 u64 cg_flags;
979 u32 pg_flags;
980
981 /* nbio */
982 struct amdgpu_nbio nbio;
983
984 /* hdp */
985 struct amdgpu_hdp hdp;
986
987 /* smuio */
988 struct amdgpu_smuio smuio;
989
990 /* mmhub */
991 struct amdgpu_mmhub mmhub;
992
993 /* gfxhub */
994 struct amdgpu_gfxhub gfxhub;
995
996 /* gfx */
997 struct amdgpu_gfx gfx;
998
999 /* sdma */
1000 struct amdgpu_sdma sdma;
1001
1002 /* lsdma */
1003 struct amdgpu_lsdma lsdma;
1004
1005 /* uvd */
1006 struct amdgpu_uvd uvd;
1007
1008 /* vce */
1009 struct amdgpu_vce vce;
1010
1011 /* vcn */
1012 struct amdgpu_vcn vcn;
1013
1014 /* jpeg */
1015 struct amdgpu_jpeg jpeg;
1016
1017 /* vpe */
1018 struct amdgpu_vpe vpe;
1019
1020 /* umsch */
1021 struct amdgpu_umsch_mm umsch_mm;
1022 bool enable_umsch_mm;
1023
1024 /* firmwares */
1025 struct amdgpu_firmware firmware;
1026
1027 /* PSP */
1028 struct psp_context psp;
1029
1030 /* GDS */
1031 struct amdgpu_gds gds;
1032
1033 /* for userq and VM fences */
1034 struct amdgpu_seq64 seq64;
1035
1036 /* KFD */
1037 struct amdgpu_kfd_dev kfd;
1038
1039 /* UMC */
1040 struct amdgpu_umc umc;
1041
1042 /* display related functionality */
1043 struct amdgpu_display_manager dm;
1044
1045#if defined(CONFIG_DRM_AMD_ISP)
1046 /* isp */
1047 struct amdgpu_isp isp;
1048#endif
1049
1050 /* mes */
1051 bool enable_mes;
1052 bool enable_mes_kiq;
1053 bool enable_uni_mes;
1054 struct amdgpu_mes mes;
1055 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
1056
1057 /* df */
1058 struct amdgpu_df df;
1059
1060 /* MCA */
1061 struct amdgpu_mca mca;
1062
1063 /* ACA */
1064 struct amdgpu_aca aca;
1065
1066 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1067 uint32_t harvest_ip_mask;
1068 int num_ip_blocks;
1069 struct mutex mn_lock;
1070 DECLARE_HASHTABLE(mn_hash, 7);
1071
1072 /* tracking pinned memory */
1073 atomic64_t vram_pin_size;
1074 atomic64_t visible_pin_size;
1075 atomic64_t gart_pin_size;
1076
1077 /* soc15 register offset based on ip, instance and segment */
1078 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1079 struct amdgpu_ip_map_info ip_map;
1080
1081 /* delayed work_func for deferring clockgating during resume */
1082 struct delayed_work delayed_init_work;
1083
1084 struct amdgpu_virt virt;
1085
1086 /* record hw reset is performed */
1087 bool has_hw_reset;
1088 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1089
1090 /* s3/s4 mask */
1091 bool in_suspend;
1092 bool in_s3;
1093 bool in_s4;
1094 bool in_s0ix;
1095 /* indicate amdgpu suspension status */
1096 bool suspend_complete;
1097
1098 enum pp_mp1_state mp1_state;
1099 struct amdgpu_doorbell_index doorbell_index;
1100
1101 struct mutex notifier_lock;
1102
1103 int asic_reset_res;
1104 struct work_struct xgmi_reset_work;
1105 struct list_head reset_list;
1106
1107 long gfx_timeout;
1108 long sdma_timeout;
1109 long video_timeout;
1110 long compute_timeout;
1111 long psp_timeout;
1112
1113 uint64_t unique_id;
1114 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1115
1116 /* enable runtime pm on the device */
1117 bool in_runpm;
1118 bool has_pr3;
1119
1120 bool ucode_sysfs_en;
1121
1122 struct amdgpu_fru_info *fru_info;
1123 atomic_t throttling_logging_enabled;
1124 struct ratelimit_state throttling_logging_rs;
1125 uint32_t ras_hw_enabled;
1126 uint32_t ras_enabled;
1127
1128 bool no_hw_access;
1129 struct pci_saved_state *pci_state;
1130 pci_channel_state_t pci_channel_state;
1131
1132 /* Track auto wait count on s_barrier settings */
1133 bool barrier_has_auto_waitcnt;
1134
1135 struct amdgpu_reset_control *reset_cntl;
1136 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1137
1138 bool ram_is_direct_mapped;
1139
1140 struct list_head ras_list;
1141
1142 struct ip_discovery_top *ip_top;
1143
1144 struct amdgpu_reset_domain *reset_domain;
1145
1146 struct mutex benchmark_mutex;
1147
1148 bool scpm_enabled;
1149 uint32_t scpm_status;
1150
1151 struct work_struct reset_work;
1152
1153 bool job_hang;
1154 bool dc_enabled;
1155 /* Mask of active clusters */
1156 uint32_t aid_mask;
1157
1158 /* Debug */
1159 bool debug_vm;
1160 bool debug_largebar;
1161 bool debug_disable_soft_recovery;
1162 bool debug_use_vram_fw_buf;
1163 bool debug_enable_ras_aca;
1164 bool debug_exp_resets;
1165
1166 bool enforce_isolation[MAX_XCP];
1167 /* Added this mutex for cleaner shader isolation between GFX and compute processes */
1168 struct mutex enforce_isolation_mutex;
1169};
1170
1171static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
1172 uint8_t ip, uint8_t inst)
1173{
1174 /* This considers only major/minor/rev and ignores
1175 * subrevision/variant fields.
1176 */
1177 return adev->ip_versions[ip][inst] & ~0xFFU;
1178}
1179
1180static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev,
1181 uint8_t ip, uint8_t inst)
1182{
1183 /* This returns full version - major/minor/rev/variant/subrevision */
1184 return adev->ip_versions[ip][inst];
1185}
1186
1187static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1188{
1189 return container_of(ddev, struct amdgpu_device, ddev);
1190}
1191
1192static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1193{
1194 return &adev->ddev;
1195}
1196
1197static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1198{
1199 return container_of(bdev, struct amdgpu_device, mman.bdev);
1200}
1201
1202int amdgpu_device_init(struct amdgpu_device *adev,
1203 uint32_t flags);
1204void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1205void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1206
1207int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1208
1209void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1210 void *buf, size_t size, bool write);
1211size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1212 void *buf, size_t size, bool write);
1213
1214void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1215 void *buf, size_t size, bool write);
1216uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
1217 uint32_t inst, uint32_t reg_addr, char reg_name[],
1218 uint32_t expected_value, uint32_t mask);
1219uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1220 uint32_t reg, uint32_t acc_flags);
1221u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
1222 u64 reg_addr);
1223uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
1224 uint32_t reg, uint32_t acc_flags,
1225 uint32_t xcc_id);
1226void amdgpu_device_wreg(struct amdgpu_device *adev,
1227 uint32_t reg, uint32_t v,
1228 uint32_t acc_flags);
1229void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1230 u64 reg_addr, u32 reg_data);
1231void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
1232 uint32_t reg, uint32_t v,
1233 uint32_t acc_flags,
1234 uint32_t xcc_id);
1235void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1236 uint32_t reg, uint32_t v, uint32_t xcc_id);
1237void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1238uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1239
1240u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1241 u32 reg_addr);
1242u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1243 u32 reg_addr);
1244u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
1245 u64 reg_addr);
1246void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1247 u32 reg_addr, u32 reg_data);
1248void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1249 u32 reg_addr, u64 reg_data);
1250void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1251 u64 reg_addr, u64 reg_data);
1252u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);
1253bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1254bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1255
1256void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1257
1258int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1259 struct amdgpu_reset_context *reset_context);
1260
1261int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1262 struct amdgpu_reset_context *reset_context);
1263
1264int emu_soc_asic_init(struct amdgpu_device *adev);
1265
1266/*
1267 * Registers read & write functions.
1268 */
1269#define AMDGPU_REGS_NO_KIQ (1<<1)
1270#define AMDGPU_REGS_RLC (1<<2)
1271
1272#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1273#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1274
1275#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0)
1276#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0)
1277
1278#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1279#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1280
1281#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1282#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1283#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1284#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1285#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1286#define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)
1287#define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)
1288#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1289#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1290#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1291#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1292#define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1293#define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
1294#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1295#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1296#define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg))
1297#define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))
1298#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1299#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1300#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1301#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1302#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1303#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1304#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1305#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1306#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1307#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1308#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1309#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1310#define WREG32_P(reg, val, mask) \
1311 do { \
1312 uint32_t tmp_ = RREG32(reg); \
1313 tmp_ &= (mask); \
1314 tmp_ |= ((val) & ~(mask)); \
1315 WREG32(reg, tmp_); \
1316 } while (0)
1317#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1318#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1319#define WREG32_PLL_P(reg, val, mask) \
1320 do { \
1321 uint32_t tmp_ = RREG32_PLL(reg); \
1322 tmp_ &= (mask); \
1323 tmp_ |= ((val) & ~(mask)); \
1324 WREG32_PLL(reg, tmp_); \
1325 } while (0)
1326
1327#define WREG32_SMC_P(_Reg, _Val, _Mask) \
1328 do { \
1329 u32 tmp = RREG32_SMC(_Reg); \
1330 tmp &= (_Mask); \
1331 tmp |= ((_Val) & ~(_Mask)); \
1332 WREG32_SMC(_Reg, tmp); \
1333 } while (0)
1334
1335#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1336
1337#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1338#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1339
1340#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1341 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1342 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1343
1344#define REG_GET_FIELD(value, reg, field) \
1345 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1346
1347#define WREG32_FIELD(reg, field, val) \
1348 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1349
1350#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1351 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1352
1353#define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l))
1354/*
1355 * BIOS helpers.
1356 */
1357#define RBIOS8(i) (adev->bios[i])
1358#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1359#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1360
1361/*
1362 * ASICs macro.
1363 */
1364#define amdgpu_asic_set_vga_state(adev, state) \
1365 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
1366#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1367#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1368#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1369#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1370#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1371#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1372#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1373#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1374#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1375#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1376#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1377#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1378#define amdgpu_asic_flush_hdp(adev, r) \
1379 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1380#define amdgpu_asic_invalidate_hdp(adev, r) \
1381 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1382 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0))
1383#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1384#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1385#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1386#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1387#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1388#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1389#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1390#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1391 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1392#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1393
1394#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter))
1395
1396#define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))
1397#define for_each_inst(i, inst_mask) \
1398 for (i = ffs(inst_mask); i-- != 0; \
1399 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
1400
1401/* Common functions */
1402bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1403bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1404int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1405 struct amdgpu_job *job,
1406 struct amdgpu_reset_context *reset_context);
1407void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1408int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1409bool amdgpu_device_need_post(struct amdgpu_device *adev);
1410bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev);
1411bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1412
1413void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1414 u64 num_vis_bytes);
1415int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1416void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1417 const u32 *registers,
1418 const u32 array_size);
1419
1420int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1421bool amdgpu_device_supports_atpx(struct drm_device *dev);
1422bool amdgpu_device_supports_px(struct drm_device *dev);
1423bool amdgpu_device_supports_boco(struct drm_device *dev);
1424bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1425int amdgpu_device_supports_baco(struct drm_device *dev);
1426void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev);
1427bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1428 struct amdgpu_device *peer_adev);
1429int amdgpu_device_baco_enter(struct drm_device *dev);
1430int amdgpu_device_baco_exit(struct drm_device *dev);
1431
1432void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1433 struct amdgpu_ring *ring);
1434void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1435 struct amdgpu_ring *ring);
1436
1437void amdgpu_device_halt(struct amdgpu_device *adev);
1438u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1439 u32 reg);
1440void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1441 u32 reg, u32 v);
1442struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev);
1443struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1444 struct dma_fence *gang);
1445bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1446
1447/* atpx handler */
1448#if defined(CONFIG_VGA_SWITCHEROO)
1449void amdgpu_register_atpx_handler(void);
1450void amdgpu_unregister_atpx_handler(void);
1451bool amdgpu_has_atpx_dgpu_power_cntl(void);
1452bool amdgpu_is_atpx_hybrid(void);
1453bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1454bool amdgpu_has_atpx(void);
1455#else
1456static inline void amdgpu_register_atpx_handler(void) {}
1457static inline void amdgpu_unregister_atpx_handler(void) {}
1458static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1459static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1460static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1461static inline bool amdgpu_has_atpx(void) { return false; }
1462#endif
1463
1464#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1465void *amdgpu_atpx_get_dhandle(void);
1466#else
1467static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1468#endif
1469
1470/*
1471 * KMS
1472 */
1473extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1474extern const int amdgpu_max_kms_ioctl;
1475
1476int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1477void amdgpu_driver_unload_kms(struct drm_device *dev);
1478int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1479void amdgpu_driver_postclose_kms(struct drm_device *dev,
1480 struct drm_file *file_priv);
1481void amdgpu_driver_release_kms(struct drm_device *dev);
1482
1483int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1484int amdgpu_device_prepare(struct drm_device *dev);
1485int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1486int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1487u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1488int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1489void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1490int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1491 struct drm_file *filp);
1492
1493/*
1494 * functions used by amdgpu_encoder.c
1495 */
1496struct amdgpu_afmt_acr {
1497 u32 clock;
1498
1499 int n_32khz;
1500 int cts_32khz;
1501
1502 int n_44_1khz;
1503 int cts_44_1khz;
1504
1505 int n_48khz;
1506 int cts_48khz;
1507
1508};
1509
1510struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1511
1512/* amdgpu_acpi.c */
1513
1514struct amdgpu_numa_info {
1515 uint64_t size;
1516 int pxm;
1517 int nid;
1518};
1519
1520/* ATCS Device/Driver State */
1521#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1522#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1523#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1524#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1525
1526#if defined(CONFIG_ACPI)
1527int amdgpu_acpi_init(struct amdgpu_device *adev);
1528void amdgpu_acpi_fini(struct amdgpu_device *adev);
1529bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1530bool amdgpu_acpi_is_power_shift_control_supported(void);
1531int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1532 u8 perf_req, bool advertise);
1533int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1534 u8 dev_state, bool drv_state);
1535int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1536int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1537int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
1538 u64 *tmr_size);
1539int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1540 struct amdgpu_numa_info *numa_info);
1541
1542void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1543bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1544void amdgpu_acpi_detect(void);
1545void amdgpu_acpi_release(void);
1546#else
1547static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1548static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
1549 u64 *tmr_offset, u64 *tmr_size)
1550{
1551 return -EINVAL;
1552}
1553static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
1554 int xcc_id,
1555 struct amdgpu_numa_info *numa_info)
1556{
1557 return -EINVAL;
1558}
1559static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1560static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1561static inline void amdgpu_acpi_detect(void) { }
1562static inline void amdgpu_acpi_release(void) { }
1563static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1564static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1565 u8 dev_state, bool drv_state) { return 0; }
1566static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1567 enum amdgpu_ss ss_state) { return 0; }
1568static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { }
1569#endif
1570
1571#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1572bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1573bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1574void amdgpu_choose_low_power_state(struct amdgpu_device *adev);
1575#else
1576static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1577static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1578static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { }
1579#endif
1580
1581void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1582void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1583
1584pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1585 pci_channel_state_t state);
1586pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1587pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1588void amdgpu_pci_resume(struct pci_dev *pdev);
1589
1590bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1591bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1592
1593bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1594
1595int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1596 enum amd_clockgating_state state);
1597int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1598 enum amd_powergating_state state);
1599
1600static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1601{
1602 return amdgpu_gpu_recovery != 0 &&
1603 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1604 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1605 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1606 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1607}
1608
1609#include "amdgpu_object.h"
1610
1611static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1612{
1613 return adev->gmc.tmz_enabled;
1614}
1615
1616int amdgpu_in_reset(struct amdgpu_device *adev);
1617
1618extern const struct attribute_group amdgpu_vram_mgr_attr_group;
1619extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
1620extern const struct attribute_group amdgpu_flash_attr_group;
1621
1622#endif