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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 BayLibre, SAS
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: STMicroelectronics STM32 / MCU DWMAC glue layer controller
9
10maintainers:
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
13
14description:
15 This file documents platform glue layer for stmmac.
16
17# We need a select here so we don't match all nodes with 'snps,dwmac'
18select:
19 properties:
20 compatible:
21 contains:
22 enum:
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
25 - st,stm32mp13-dwmac
26 - st,stm32mp25-dwmac
27 required:
28 - compatible
29
30properties:
31 compatible:
32 oneOf:
33 - items:
34 - enum:
35 - st,stm32mp25-dwmac
36 - const: snps,dwmac-5.20
37 - items:
38 - enum:
39 - st,stm32mp1-dwmac
40 - st,stm32mp13-dwmac
41 - const: snps,dwmac-4.20a
42 - items:
43 - enum:
44 - st,stm32-dwmac
45 - const: snps,dwmac-4.10a
46 - items:
47 - enum:
48 - st,stm32-dwmac
49 - const: snps,dwmac-3.50a
50
51 reg: true
52
53 reg-names:
54 items:
55 - const: stmmaceth
56
57 clocks:
58 minItems: 3
59 items:
60 - description: GMAC main clock
61 - description: MAC TX clock
62 - description: MAC RX clock
63 - description: For MPU family, used for power mode
64 - description: For MPU family, used for PHY without quartz
65 - description: PTP clock
66
67 clock-names:
68 minItems: 3
69 maxItems: 6
70 contains:
71 enum:
72 - stmmaceth
73 - mac-clk-tx
74 - mac-clk-rx
75 - ethstp
76 - eth-ck
77 - ptp_ref
78
79 st,syscon:
80 $ref: /schemas/types.yaml#/definitions/phandle-array
81 items:
82 - minItems: 2
83 items:
84 - description: phandle to the syscon node which encompases the glue register
85 - description: offset of the control register
86 - description: field to set mask in register
87 description:
88 Should be phandle/offset pair. The phandle to the syscon node which
89 encompases the glue register, the offset of the control register and
90 the mask to set bitfield in control register
91
92 st,ext-phyclk:
93 description:
94 set this property in RMII mode when you have PHY without crystal 50MHz and want to
95 select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when you want to select
96 RCC clock instead of ETH_CLK125.
97 type: boolean
98
99 st,eth-clk-sel:
100 description:
101 set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
102 type: boolean
103
104 st,eth-ref-clk-sel:
105 description:
106 set this property in RMII mode when you have PHY without crystal 50MHz and want to
107 select RCC clock instead of ETH_REF_CLK.
108 type: boolean
109
110 access-controllers:
111 minItems: 1
112 maxItems: 2
113
114required:
115 - compatible
116 - clocks
117 - clock-names
118 - st,syscon
119
120unevaluatedProperties: false
121
122allOf:
123 - $ref: snps,dwmac.yaml#
124 - if:
125 properties:
126 compatible:
127 contains:
128 enum:
129 - st,stm32-dwmac
130 - st,stm32mp1-dwmac
131 - st,stm32mp25-dwmac
132 then:
133 properties:
134 st,syscon:
135 items:
136 minItems: 2
137 maxItems: 2
138
139 - if:
140 properties:
141 compatible:
142 contains:
143 enum:
144 - st,stm32mp13-dwmac
145 then:
146 properties:
147 st,syscon:
148 items:
149 minItems: 3
150 maxItems: 3
151
152examples:
153 - |
154 #include <dt-bindings/interrupt-controller/arm-gic.h>
155 #include <dt-bindings/clock/stm32mp1-clks.h>
156 //Example 1
157 ethernet0: ethernet@5800a000 {
158 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
159 reg = <0x5800a000 0x2000>;
160 reg-names = "stmmaceth";
161 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
162 interrupt-names = "macirq";
163 clock-names = "stmmaceth",
164 "mac-clk-tx",
165 "mac-clk-rx",
166 "ethstp",
167 "eth-ck";
168 clocks = <&rcc ETHMAC>,
169 <&rcc ETHTX>,
170 <&rcc ETHRX>,
171 <&rcc ETHSTP>,
172 <&rcc ETHCK_K>;
173 st,syscon = <&syscfg 0x4>;
174 snps,pbl = <2>;
175 snps,axi-config = <&stmmac_axi_config_0>;
176 snps,tso;
177 phy-mode = "rgmii";
178 };
179
180 - |
181 //Example 2 (MCU example)
182 ethernet1: ethernet@40028000 {
183 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
184 reg = <0x40028000 0x8000>;
185 reg-names = "stmmaceth";
186 interrupts = <0 61 0>, <0 62 0>;
187 interrupt-names = "macirq", "eth_wake_irq";
188 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
189 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
190 st,syscon = <&syscfg 0x4>;
191 snps,pbl = <8>;
192 snps,mixed-burst;
193 phy-mode = "mii";
194 };
195
196 - |
197 //Example 3
198 ethernet2: ethernet@40027000 {
199 compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
200 reg = <0x40028000 0x8000>;
201 reg-names = "stmmaceth";
202 interrupts = <61>;
203 interrupt-names = "macirq";
204 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
205 clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
206 st,syscon = <&syscfg 0x4>;
207 snps,pbl = <8>;
208 phy-mode = "mii";
209 };