Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __MES_API_DEF_H__
25#define __MES_API_DEF_H__
26
27#pragma pack(push, 8)
28
29#define MES_API_VERSION 0x14
30
31/* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG_12 */
32#define AMDGPU_MES_LOG_BUFFER_SIZE 0xC000
33
34/* Driver submits one API(cmd) as a single Frame and this command size is same for all API
35 * to ease the debugging and parsing of ring buffer.
36 */
37enum {API_FRAME_SIZE_IN_DWORDS = 64};
38
39/* To avoid command in scheduler context to be overwritten whenenver mutilple interrupts come in,
40 * this creates another queue
41 */
42enum {API_NUMBER_OF_COMMAND_MAX = 32};
43
44enum MES_API_TYPE {
45 MES_API_TYPE_SCHEDULER = 1,
46 MES_API_TYPE_MAX
47};
48
49enum MES_SCH_API_OPCODE {
50 MES_SCH_API_SET_HW_RSRC = 0,
51 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */
52 MES_SCH_API_ADD_QUEUE = 2,
53 MES_SCH_API_REMOVE_QUEUE = 3,
54 MES_SCH_API_PERFORM_YIELD = 4,
55 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, /* For windows GANG = Context */
56 MES_SCH_API_SUSPEND = 6,
57 MES_SCH_API_RESUME = 7,
58 MES_SCH_API_RESET = 8,
59 MES_SCH_API_SET_LOG_BUFFER = 9,
60 MES_SCH_API_CHANGE_GANG_PRORITY = 10,
61 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11,
62 MES_SCH_API_SET_DEBUG_VMID = 13,
63 MES_SCH_API_MISC = 14,
64 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15,
65 MES_SCH_API_AMD_LOG = 16,
66 MES_SCH_API_SET_SE_MODE = 17,
67 MES_SCH_API_SET_GANG_SUBMIT = 18,
68 MES_SCH_API_SET_HW_RSRC_1 = 19,
69
70 MES_SCH_API_MAX = 0xFF
71};
72
73union MES_API_HEADER {
74 struct {
75 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
76 uint32_t opcode : 8;
77 uint32_t dwsize : 8; /* including header */
78 uint32_t reserved : 12;
79 };
80
81 uint32_t u32All;
82};
83
84enum MES_AMD_PRIORITY_LEVEL {
85 AMD_PRIORITY_LEVEL_LOW = 0,
86 AMD_PRIORITY_LEVEL_NORMAL = 1,
87 AMD_PRIORITY_LEVEL_MEDIUM = 2,
88 AMD_PRIORITY_LEVEL_HIGH = 3,
89 AMD_PRIORITY_LEVEL_REALTIME = 4,
90
91 AMD_PRIORITY_NUM_LEVELS
92};
93
94enum MES_QUEUE_TYPE {
95 MES_QUEUE_TYPE_GFX,
96 MES_QUEUE_TYPE_COMPUTE,
97 MES_QUEUE_TYPE_SDMA,
98
99 MES_QUEUE_TYPE_MAX,
100};
101
102struct MES_API_STATUS {
103 uint64_t api_completion_fence_addr;
104 uint64_t api_completion_fence_value;
105};
106
107
108enum { MAX_COMPUTE_PIPES = 8 };
109enum { MAX_GFX_PIPES = 2 };
110enum { MAX_SDMA_PIPES = 2 };
111
112enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
113enum { MAX_GFX_HQD_PER_PIPE = 8 };
114enum { MAX_SDMA_HQD_PER_PIPE = 10 };
115enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 };
116
117
118enum { MAX_QUEUES_IN_A_GANG = 8 };
119
120enum VM_HUB_TYPE {
121 VM_HUB_TYPE_GC = 0,
122 VM_HUB_TYPE_MM = 1,
123
124 VM_HUB_TYPE_MAX,
125};
126
127enum { VMID_INVALID = 0xffff };
128
129enum { MAX_VMID_GCHUB = 16 };
130enum { MAX_VMID_MMHUB = 16 };
131
132enum SET_DEBUG_VMID_OPERATIONS {
133 DEBUG_VMID_OP_PROGRAM = 0,
134 DEBUG_VMID_OP_ALLOCATE = 1,
135 DEBUG_VMID_OP_RELEASE = 2,
136 DEBUG_VMID_OP_VM_SETUP = 3 // used to set up the debug vmid page table in the kernel queue case (mode 1)
137};
138
139enum MES_MS_LOG_CONTEXT_STATE {
140 MES_LOG_CONTEXT_STATE_IDLE = 0,
141 MES_LOG_CONTEXT_STATE_RUNNING = 1,
142 MES_LOG_CONTEXT_STATE_READY = 2,
143 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
144 MES_LOG_CONTEXT_STATE_INVALID = 0xF,
145};
146
147enum MES_MS_LOG_OPERATION {
148 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
149 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1,
150 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
151 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
152 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
153 MES_LOG_OPERATION_QUEUE_INVALID = 0xF,
154};
155
156struct MES_LOG_CONTEXT_STATE_CHANGE {
157 uint64_t h_context;
158 enum MES_MS_LOG_CONTEXT_STATE new_context_state;
159};
160
161struct MES_LOG_QUEUE_NEW_WORK {
162 uint64_t h_queue;
163 uint64_t reserved;
164};
165
166struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
167 uint64_t h_queue;
168 uint64_t h_sync_object;
169};
170
171struct MES_LOG_QUEUE_NO_MORE_WORK {
172 uint64_t h_queue;
173 uint64_t reserved;
174};
175
176struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
177 uint64_t h_queue;
178 uint64_t h_sync_object;
179};
180
181struct MES_LOG_ENTRY_HEADER {
182 uint32_t first_free_entry_index;
183 uint32_t wraparound_count;
184 uint64_t number_of_entries;
185 uint64_t reserved[2];
186};
187
188struct MES_LOG_ENTRY_DATA {
189 uint64_t gpu_time_stamp;
190 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
191 uint32_t reserved_operation_type_bits;
192 union {
193 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
194 struct MES_LOG_QUEUE_NEW_WORK queue_new_work;
195 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
196 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work;
197 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object;
198 uint64_t all[2];
199 };
200};
201
202struct MES_LOG_BUFFER {
203 struct MES_LOG_ENTRY_HEADER header;
204 struct MES_LOG_ENTRY_DATA entries[];
205};
206
207enum MES_SWIP_TO_HWIP_DEF {
208 MES_MAX_HWIP_SEGMENT = 8,
209};
210
211union MESAPI_SET_HW_RESOURCES {
212 struct {
213 union MES_API_HEADER header;
214 uint32_t vmid_mask_mmhub;
215 uint32_t vmid_mask_gfxhub;
216 uint32_t gds_size;
217 uint32_t paging_vmid;
218 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES];
219 uint32_t gfx_hqd_mask[MAX_GFX_PIPES];
220 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES];
221 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
222 uint64_t g_sch_ctx_gpu_mc_ptr;
223 uint64_t query_status_fence_gpu_mc_ptr;
224 uint32_t gc_base[MES_MAX_HWIP_SEGMENT];
225 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT];
226 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT];
227 struct MES_API_STATUS api_status;
228 union {
229 struct {
230 uint32_t disable_reset : 1;
231 uint32_t use_different_vmid_compute : 1;
232 uint32_t disable_mes_log : 1;
233 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
234 uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
235 uint32_t second_gfx_pipe_enabled : 1;
236 uint32_t enable_level_process_quantum_check : 1;
237 uint32_t legacy_sch_mode : 1;
238 uint32_t disable_add_queue_wptr_mc_addr : 1;
239 uint32_t enable_mes_event_int_logging : 1;
240 uint32_t enable_reg_active_poll : 1;
241 uint32_t use_disable_queue_in_legacy_uq_preemption : 1;
242 uint32_t send_write_data : 1;
243 uint32_t os_tdr_timeout_override : 1;
244 uint32_t use_rs64mem_for_proc_gang_ctx : 1;
245 uint32_t unmapped_doorbell_handling: 2;
246 uint32_t reserved : 15;
247 };
248 uint32_t uint32_all;
249 };
250 uint32_t oversubscription_timer;
251 uint64_t doorbell_info;
252 uint64_t event_intr_history_gpu_mc_ptr;
253 uint64_t timestamp;
254 uint32_t os_tdr_timeout_in_sec;
255 };
256
257 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
258};
259
260union MESAPI_SET_HW_RESOURCES_1 {
261 struct {
262 union MES_API_HEADER header;
263 struct MES_API_STATUS api_status;
264 uint64_t timestamp;
265 union {
266 struct {
267 uint32_t enable_mes_debug_ctx : 1;
268 uint32_t reserved : 31;
269 };
270 uint32_t uint32_all;
271 };
272 uint64_t mes_debug_ctx_mc_addr;
273 uint32_t mes_debug_ctx_size;
274 /* unit is 100ms */
275 uint32_t mes_kiq_unmap_timeout;
276 };
277
278 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
279};
280
281union MESAPI__ADD_QUEUE {
282 struct {
283 union MES_API_HEADER header;
284 uint32_t process_id;
285 uint64_t page_table_base_addr;
286 uint64_t process_va_start;
287 uint64_t process_va_end;
288 uint64_t process_quantum;
289 uint64_t process_context_addr;
290 uint64_t gang_quantum;
291 uint64_t gang_context_addr;
292 uint32_t inprocess_gang_priority;
293 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
294 uint32_t doorbell_offset;
295 uint64_t mqd_addr;
296 /* From MES_API_VERSION 2, mc addr is expected for wptr_addr */
297 uint64_t wptr_addr;
298 uint64_t h_context;
299 uint64_t h_queue;
300 enum MES_QUEUE_TYPE queue_type;
301 uint32_t gds_base;
302 union {
303 /* backwards compatibility with Linux, remove union once they use kfd_queue_size */
304 uint32_t gds_size;
305 uint32_t kfd_queue_size;
306 };
307 uint32_t gws_base;
308 uint32_t gws_size;
309 uint32_t oa_mask;
310 uint64_t trap_handler_addr;
311 uint32_t vm_context_cntl;
312
313 struct {
314 uint32_t paging : 1;
315 uint32_t debug_vmid : 4;
316 uint32_t program_gds : 1;
317 uint32_t is_gang_suspended : 1;
318 uint32_t is_tmz_queue : 1;
319 uint32_t map_kiq_utility_queue : 1;
320 uint32_t is_kfd_process : 1;
321 uint32_t trap_en : 1;
322 uint32_t is_aql_queue : 1;
323 uint32_t skip_process_ctx_clear : 1;
324 uint32_t map_legacy_kq : 1;
325 uint32_t exclusively_scheduled : 1;
326 uint32_t is_long_running : 1;
327 uint32_t is_dwm_queue : 1;
328 uint32_t reserved : 15;
329 };
330 struct MES_API_STATUS api_status;
331 uint64_t tma_addr;
332 uint32_t sch_id;
333 uint64_t timestamp;
334 uint32_t process_context_array_index;
335 uint32_t gang_context_array_index;
336 uint32_t pipe_id; //used for mapping legacy kernel queue
337 uint32_t queue_id;
338 uint32_t alignment_mode_setting;
339 };
340
341 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
342};
343
344union MESAPI__REMOVE_QUEUE {
345 struct {
346 union MES_API_HEADER header;
347 uint32_t doorbell_offset;
348 uint64_t gang_context_addr;
349
350 struct {
351 uint32_t reserved01 : 1;
352 uint32_t unmap_kiq_utility_queue : 1;
353 uint32_t preempt_legacy_gfx_queue : 1;
354 uint32_t unmap_legacy_queue : 1;
355 uint32_t reserved : 28;
356 };
357 struct MES_API_STATUS api_status;
358
359 uint32_t pipe_id;
360 uint32_t queue_id;
361
362 uint64_t tf_addr;
363 uint32_t tf_data;
364
365 enum MES_QUEUE_TYPE queue_type;
366 uint64_t timestamp;
367 uint32_t gang_context_array_index;
368 };
369
370 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
371};
372
373union MESAPI__SET_SCHEDULING_CONFIG {
374 struct {
375 union MES_API_HEADER header;
376 /* Grace period when preempting another priority band for this priority band.
377 * The value for idle priority band is ignored, as it never preempts other bands.
378 */
379 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
380
381 /* Default quantum for scheduling across processes within a priority band. */
382 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
383
384 /* Default grace period for processes that preempt each other within a priority band.*/
385 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
386
387 /* For normal level this field specifies the target GPU percentage in situations when it's starved by the high level.
388 * Valid values are between 0 and 50, with the default being 10.
389 */
390 uint32_t normal_yield_percent;
391
392 struct MES_API_STATUS api_status;
393 uint64_t timestamp;
394 };
395
396 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
397};
398
399union MESAPI__PERFORM_YIELD {
400 struct {
401 union MES_API_HEADER header;
402 uint32_t dummy;
403 struct MES_API_STATUS api_status;
404 uint64_t timestamp;
405 };
406
407 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
408};
409
410union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
411 struct {
412 union MES_API_HEADER header;
413 uint32_t inprocess_gang_priority;
414 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
415 uint64_t gang_quantum;
416 uint64_t gang_context_addr;
417 struct MES_API_STATUS api_status;
418 uint32_t doorbell_offset;
419 uint64_t timestamp;
420 uint32_t gang_context_array_index;
421 struct {
422 uint32_t queue_quantum_scale : 2;
423 uint32_t queue_quantum_duration : 8;
424 uint32_t apply_quantum_all_processes : 1;
425 uint32_t reserved : 21;
426 };
427 };
428
429 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
430};
431
432union MESAPI__SUSPEND {
433 struct {
434 union MES_API_HEADER header;
435 /* false - suspend all gangs; true - specific gang */
436 struct {
437 uint32_t suspend_all_gangs : 1;
438 uint32_t reserved : 31;
439 };
440 /* gang_context_addr is valid only if suspend_all = false */
441
442 uint64_t gang_context_addr;
443
444 uint64_t suspend_fence_addr;
445 uint32_t suspend_fence_value;
446
447 struct MES_API_STATUS api_status;
448
449 union {
450 uint32_t return_value; // to be removed
451 uint32_t sch_id; //keep the old return_value temporarily for compatibility
452 };
453 uint32_t doorbell_offset;
454 uint64_t timestamp;
455 enum MES_QUEUE_TYPE legacy_uq_type;
456 enum MES_AMD_PRIORITY_LEVEL legacy_uq_priority_level;
457 uint32_t gang_context_array_index;
458 };
459
460 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
461};
462
463union MESAPI__RESUME {
464 struct {
465 union MES_API_HEADER header;
466 /* false - resume all gangs; true - specified gang */
467 struct {
468 uint32_t resume_all_gangs : 1;
469 uint32_t reserved : 31;
470 };
471 /* valid only if resume_all_gangs = false */
472 uint64_t gang_context_addr;
473
474 struct MES_API_STATUS api_status;
475 uint32_t doorbell_offset;
476 uint64_t timestamp;
477 uint32_t gang_context_array_index;
478 };
479
480 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
481};
482
483union MESAPI__RESET {
484 struct {
485 union MES_API_HEADER header;
486
487 struct {
488 /* Only reset the queue given by doorbell_offset (not entire gang) */
489 uint32_t reset_queue_only : 1;
490 /* Hang detection first then reset any queues that are hung */
491 uint32_t hang_detect_then_reset : 1;
492 /* Only do hang detection (no reset) */
493 uint32_t hang_detect_only : 1;
494 /* Reset HP and LP kernel queues not managed by MES */
495 uint32_t reset_legacy_gfx : 1;
496 /* Fallback to use conneceted queue index when CP_CNTX_STAT method fails (gfx pipe 0) */
497 uint32_t use_connected_queue_index : 1;
498 /* For gfx pipe 1 */
499 uint32_t use_connected_queue_index_p1 : 1;
500 uint32_t reserved : 26;
501 };
502
503 uint64_t gang_context_addr;
504
505 /* valid only if reset_queue_only = true */
506 uint32_t doorbell_offset;
507
508 /* valid only if hang_detect_then_reset = true */
509 uint64_t doorbell_offset_addr;
510 enum MES_QUEUE_TYPE queue_type;
511
512 /* valid only if reset_legacy_gfx = true */
513 uint32_t pipe_id_lp;
514 uint32_t queue_id_lp;
515 uint32_t vmid_id_lp;
516 uint64_t mqd_mc_addr_lp;
517 uint32_t doorbell_offset_lp;
518 uint64_t wptr_addr_lp;
519
520 uint32_t pipe_id_hp;
521 uint32_t queue_id_hp;
522 uint32_t vmid_id_hp;
523 uint64_t mqd_mc_addr_hp;
524 uint32_t doorbell_offset_hp;
525 uint64_t wptr_addr_hp;
526
527 struct MES_API_STATUS api_status;
528 uint32_t active_vmids;
529 uint64_t timestamp;
530
531 uint32_t gang_context_array_index;
532
533 uint32_t connected_queue_index;
534 uint32_t connected_queue_index_p1;
535 };
536
537 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
538};
539
540union MESAPI__SET_LOGGING_BUFFER {
541 struct {
542 union MES_API_HEADER header;
543 /* There are separate log buffers for each queue type */
544 enum MES_QUEUE_TYPE log_type;
545 /* Log buffer GPU Address */
546 uint64_t logging_buffer_addr;
547 /* number of entries in the log buffer */
548 uint32_t number_of_entries;
549 /* Entry index at which CPU interrupt needs to be signalled */
550 uint32_t interrupt_entry;
551
552 struct MES_API_STATUS api_status;
553 uint64_t timestamp;
554 uint32_t vmid;
555 };
556
557 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
558};
559
560enum MES_API_QUERY_MES_OPCODE {
561 MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE,
562 MES_API_QUERY_MES__CHECK_HEALTHY,
563 MES_API_QUERY_MES__MAX,
564};
565
566enum { QUERY_MES_MAX_SIZE_IN_DWORDS = 20 };
567
568struct MES_API_QUERY_MES__CTX_ARRAY_SIZE {
569 uint64_t proc_ctx_array_size_addr;
570 uint64_t gang_ctx_array_size_addr;
571};
572
573struct MES_API_QUERY_MES__HEALTHY_CHECK {
574 uint64_t healthy_addr;
575};
576
577union MESAPI__QUERY_MES_STATUS {
578 struct {
579 union MES_API_HEADER header;
580 enum MES_API_QUERY_MES_OPCODE subopcode;
581 struct MES_API_STATUS api_status;
582 uint64_t timestamp;
583 union {
584 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE ctx_array_size;
585 struct MES_API_QUERY_MES__HEALTHY_CHECK healthy_check;
586 uint32_t data[QUERY_MES_MAX_SIZE_IN_DWORDS];
587 };
588 };
589
590 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
591};
592
593union MESAPI__SET_DEBUG_VMID {
594 struct {
595 union MES_API_HEADER header;
596 struct MES_API_STATUS api_status;
597 union {
598 struct {
599 uint32_t use_gds : 1;
600 uint32_t operation : 2;
601 uint32_t reserved : 29;
602 } flags;
603 uint32_t u32All;
604 };
605 uint32_t reserved;
606 uint32_t debug_vmid;
607 uint64_t process_context_addr;
608 uint64_t page_table_base_addr;
609 uint64_t process_va_start;
610 uint64_t process_va_end;
611 uint32_t gds_base;
612 uint32_t gds_size;
613 uint32_t gws_base;
614 uint32_t gws_size;
615 uint32_t oa_mask;
616
617 uint64_t output_addr; // output addr of the acquired vmid value
618
619 uint64_t timestamp;
620
621 uint32_t process_vm_cntl;
622 enum MES_QUEUE_TYPE queue_type;
623
624 uint32_t process_context_array_index;
625
626 uint32_t alignment_mode_setting;
627 };
628
629 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
630};
631
632enum MESAPI_MISC_OPCODE {
633 MESAPI_MISC__WRITE_REG,
634 MESAPI_MISC__INV_GART,
635 MESAPI_MISC__QUERY_STATUS,
636 MESAPI_MISC__READ_REG,
637 MESAPI_MISC__WAIT_REG_MEM,
638 MESAPI_MISC__SET_SHADER_DEBUGGER,
639 MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE,
640 MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES,
641
642 MESAPI_MISC__MAX,
643};
644
645enum {MISC_DATA_MAX_SIZE_IN_DWORDS = 20};
646
647struct WRITE_REG {
648 uint32_t reg_offset;
649 uint32_t reg_value;
650};
651
652struct READ_REG {
653 uint32_t reg_offset;
654 uint64_t buffer_addr;
655 union {
656 struct {
657 uint32_t read64Bits : 1;
658 uint32_t reserved : 31;
659 } bits;
660 uint32_t all;
661 } option;
662};
663
664struct INV_GART {
665 uint64_t inv_range_va_start;
666 uint64_t inv_range_size;
667};
668
669struct QUERY_STATUS {
670 uint32_t context_id;
671};
672
673enum WRM_OPERATION {
674 WRM_OPERATION__WAIT_REG_MEM,
675 WRM_OPERATION__WR_WAIT_WR_REG,
676
677 WRM_OPERATION__MAX,
678};
679
680struct WAIT_REG_MEM {
681 enum WRM_OPERATION op;
682 /* only function = equal_to_the_reference_value and mem_space = register_space supported for now */
683 uint32_t reference;
684 uint32_t mask;
685 uint32_t reg_offset1;
686 uint32_t reg_offset2;
687};
688
689struct SET_SHADER_DEBUGGER {
690 uint64_t process_context_addr;
691 union {
692 struct {
693 uint32_t single_memop : 1; // SQ_DEBUG.single_memop
694 uint32_t single_alu_op : 1; // SQ_DEBUG.single_alu_op
695 uint32_t reserved : 30;
696 };
697 uint32_t u32all;
698 } flags;
699 uint32_t spi_gdbg_per_vmid_cntl;
700 uint32_t tcp_watch_cntl[4]; // TCP_WATCHx_CNTL
701 uint32_t trap_en;
702};
703
704struct SET_GANG_SUBMIT {
705 uint64_t gang_context_addr;
706 uint64_t slave_gang_context_addr;
707 uint32_t gang_context_array_index;
708 uint32_t slave_gang_context_array_index;
709};
710
711union MESAPI__MISC {
712 struct {
713 union MES_API_HEADER header;
714 enum MESAPI_MISC_OPCODE opcode;
715 struct MES_API_STATUS api_status;
716 union {
717 struct WRITE_REG write_reg;
718 struct INV_GART inv_gart;
719 struct QUERY_STATUS query_status;
720 struct READ_REG read_reg;
721 struct WAIT_REG_MEM wait_reg_mem;
722 struct SET_SHADER_DEBUGGER set_shader_debugger;
723 enum MES_AMD_PRIORITY_LEVEL queue_sch_level;
724
725 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];
726 };
727 uint64_t timestamp;
728 uint32_t doorbell_offset;
729 uint32_t os_fence;
730 };
731
732 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
733};
734
735union MESAPI__UPDATE_ROOT_PAGE_TABLE {
736 struct {
737 union MES_API_HEADER header;
738 uint64_t page_table_base_addr;
739 uint64_t process_context_addr;
740 struct MES_API_STATUS api_status;
741 uint64_t timestamp;
742 uint32_t process_context_array_index;
743 };
744
745 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
746};
747
748union MESAPI_AMD_LOG {
749 struct {
750 union MES_API_HEADER header;
751 uint64_t p_buffer_memory;
752 uint64_t p_buffer_size_used;
753 struct MES_API_STATUS api_status;
754 uint64_t timestamp;
755 };
756
757 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
758};
759
760enum MES_SE_MODE {
761 MES_SE_MODE_INVALID = 0,
762 MES_SE_MODE_SINGLE_SE = 1,
763 MES_SE_MODE_DUAL_SE = 2,
764 MES_SE_MODE_LOWER_POWER = 3,
765};
766
767union MESAPI__SET_SE_MODE {
768 struct {
769 union MES_API_HEADER header;
770 /* the new SE mode to apply*/
771 enum MES_SE_MODE new_se_mode;
772 /* the fence to make sure the ItCpgCtxtSync packet is completed */
773 uint64_t cpg_ctxt_sync_fence_addr;
774 uint32_t cpg_ctxt_sync_fence_value;
775 /* log_seq_time - Scheduler logs the switch seq start/end ts in the IH cookies */
776 union {
777 struct {
778 uint32_t log_seq_time : 1;
779 uint32_t reserved : 31;
780 };
781 uint32_t uint32_all;
782 };
783 struct MES_API_STATUS api_status;
784 };
785
786 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
787};
788
789union MESAPI__SET_GANG_SUBMIT {
790 struct {
791 union MES_API_HEADER header;
792 struct MES_API_STATUS api_status;
793 struct SET_GANG_SUBMIT set_gang_submit;
794 };
795
796 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
797};
798
799#pragma pack(pop)
800
801#endif