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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * TI CPUFreq/OPP hw-supported driver
4 *
5 * Copyright (C) 2016-2017 Texas Instruments, Inc.
6 * Dave Gerlach <d-gerlach@ti.com>
7 */
8
9#include <linux/cpu.h>
10#include <linux/io.h>
11#include <linux/mfd/syscon.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/pm_opp.h>
17#include <linux/regmap.h>
18#include <linux/slab.h>
19
20#define REVISION_MASK 0xF
21#define REVISION_SHIFT 28
22
23#define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F
24#define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA
25
26#define DRA7_EFUSE_HAS_OD_MPU_OPP 11
27#define DRA7_EFUSE_HAS_HIGH_MPU_OPP 15
28#define DRA76_EFUSE_HAS_PLUS_MPU_OPP 18
29#define DRA7_EFUSE_HAS_ALL_MPU_OPP 23
30#define DRA76_EFUSE_HAS_ALL_MPU_OPP 24
31
32#define DRA7_EFUSE_NOM_MPU_OPP BIT(0)
33#define DRA7_EFUSE_OD_MPU_OPP BIT(1)
34#define DRA7_EFUSE_HIGH_MPU_OPP BIT(2)
35#define DRA76_EFUSE_PLUS_MPU_OPP BIT(3)
36
37#define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C
38#define OMAP3_CONTROL_IDCODE 0x4830A204
39#define OMAP34xx_ProdID_SKUID 0x4830A20C
40#define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270)
41
42#define AM625_EFUSE_K_MPU_OPP 11
43#define AM625_EFUSE_S_MPU_OPP 19
44#define AM625_EFUSE_T_MPU_OPP 20
45
46#define AM625_SUPPORT_K_MPU_OPP BIT(0)
47#define AM625_SUPPORT_S_MPU_OPP BIT(1)
48#define AM625_SUPPORT_T_MPU_OPP BIT(2)
49
50enum {
51 AM62A7_EFUSE_M_MPU_OPP = 13,
52 AM62A7_EFUSE_N_MPU_OPP,
53 AM62A7_EFUSE_O_MPU_OPP,
54 AM62A7_EFUSE_P_MPU_OPP,
55 AM62A7_EFUSE_Q_MPU_OPP,
56 AM62A7_EFUSE_R_MPU_OPP,
57 AM62A7_EFUSE_S_MPU_OPP,
58 /*
59 * The V, U, and T speed grade numbering is out of order
60 * to align with the AM625 more uniformly. I promise I know
61 * my ABCs ;)
62 */
63 AM62A7_EFUSE_V_MPU_OPP,
64 AM62A7_EFUSE_U_MPU_OPP,
65 AM62A7_EFUSE_T_MPU_OPP,
66};
67
68#define AM62A7_SUPPORT_N_MPU_OPP BIT(0)
69#define AM62A7_SUPPORT_R_MPU_OPP BIT(1)
70#define AM62A7_SUPPORT_V_MPU_OPP BIT(2)
71
72#define AM62P5_EFUSE_O_MPU_OPP 15
73#define AM62P5_EFUSE_S_MPU_OPP 19
74#define AM62P5_EFUSE_U_MPU_OPP 21
75
76#define AM62P5_SUPPORT_O_MPU_OPP BIT(0)
77#define AM62P5_SUPPORT_U_MPU_OPP BIT(2)
78
79#define VERSION_COUNT 2
80
81struct ti_cpufreq_data;
82
83struct ti_cpufreq_soc_data {
84 const char * const *reg_names;
85 unsigned long (*efuse_xlate)(struct ti_cpufreq_data *opp_data,
86 unsigned long efuse);
87 unsigned long efuse_fallback;
88 unsigned long efuse_offset;
89 unsigned long efuse_mask;
90 unsigned long efuse_shift;
91 unsigned long rev_offset;
92 bool multi_regulator;
93};
94
95struct ti_cpufreq_data {
96 struct device *cpu_dev;
97 struct device_node *opp_node;
98 struct regmap *syscon;
99 const struct ti_cpufreq_soc_data *soc_data;
100};
101
102static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data,
103 unsigned long efuse)
104{
105 if (!efuse)
106 efuse = opp_data->soc_data->efuse_fallback;
107 /* AM335x and AM437x use "OPP disable" bits, so invert */
108 return ~efuse;
109}
110
111static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data,
112 unsigned long efuse)
113{
114 unsigned long calculated_efuse = DRA7_EFUSE_NOM_MPU_OPP;
115
116 /*
117 * The efuse on dra7 and am57 parts contains a specific
118 * value indicating the highest available OPP.
119 */
120
121 switch (efuse) {
122 case DRA76_EFUSE_HAS_PLUS_MPU_OPP:
123 case DRA76_EFUSE_HAS_ALL_MPU_OPP:
124 calculated_efuse |= DRA76_EFUSE_PLUS_MPU_OPP;
125 fallthrough;
126 case DRA7_EFUSE_HAS_ALL_MPU_OPP:
127 case DRA7_EFUSE_HAS_HIGH_MPU_OPP:
128 calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP;
129 fallthrough;
130 case DRA7_EFUSE_HAS_OD_MPU_OPP:
131 calculated_efuse |= DRA7_EFUSE_OD_MPU_OPP;
132 }
133
134 return calculated_efuse;
135}
136
137static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data,
138 unsigned long efuse)
139{
140 /* OPP enable bit ("Speed Binned") */
141 return BIT(efuse);
142}
143
144static unsigned long am62p5_efuse_xlate(struct ti_cpufreq_data *opp_data,
145 unsigned long efuse)
146{
147 unsigned long calculated_efuse = AM62P5_SUPPORT_O_MPU_OPP;
148
149 switch (efuse) {
150 case AM62P5_EFUSE_U_MPU_OPP:
151 case AM62P5_EFUSE_S_MPU_OPP:
152 calculated_efuse |= AM62P5_SUPPORT_U_MPU_OPP;
153 fallthrough;
154 case AM62P5_EFUSE_O_MPU_OPP:
155 calculated_efuse |= AM62P5_SUPPORT_O_MPU_OPP;
156 }
157
158 return calculated_efuse;
159}
160
161static unsigned long am62a7_efuse_xlate(struct ti_cpufreq_data *opp_data,
162 unsigned long efuse)
163{
164 unsigned long calculated_efuse = AM62A7_SUPPORT_N_MPU_OPP;
165
166 switch (efuse) {
167 case AM62A7_EFUSE_V_MPU_OPP:
168 case AM62A7_EFUSE_U_MPU_OPP:
169 case AM62A7_EFUSE_T_MPU_OPP:
170 case AM62A7_EFUSE_S_MPU_OPP:
171 calculated_efuse |= AM62A7_SUPPORT_V_MPU_OPP;
172 fallthrough;
173 case AM62A7_EFUSE_R_MPU_OPP:
174 case AM62A7_EFUSE_Q_MPU_OPP:
175 case AM62A7_EFUSE_P_MPU_OPP:
176 case AM62A7_EFUSE_O_MPU_OPP:
177 calculated_efuse |= AM62A7_SUPPORT_R_MPU_OPP;
178 fallthrough;
179 case AM62A7_EFUSE_N_MPU_OPP:
180 case AM62A7_EFUSE_M_MPU_OPP:
181 calculated_efuse |= AM62A7_SUPPORT_N_MPU_OPP;
182 }
183
184 return calculated_efuse;
185}
186
187static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data,
188 unsigned long efuse)
189{
190 unsigned long calculated_efuse = AM625_SUPPORT_K_MPU_OPP;
191
192 switch (efuse) {
193 case AM625_EFUSE_T_MPU_OPP:
194 calculated_efuse |= AM625_SUPPORT_T_MPU_OPP;
195 fallthrough;
196 case AM625_EFUSE_S_MPU_OPP:
197 calculated_efuse |= AM625_SUPPORT_S_MPU_OPP;
198 fallthrough;
199 case AM625_EFUSE_K_MPU_OPP:
200 calculated_efuse |= AM625_SUPPORT_K_MPU_OPP;
201 }
202
203 return calculated_efuse;
204}
205
206static struct ti_cpufreq_soc_data am3x_soc_data = {
207 .efuse_xlate = amx3_efuse_xlate,
208 .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
209 .efuse_offset = 0x07fc,
210 .efuse_mask = 0x1fff,
211 .rev_offset = 0x600,
212 .multi_regulator = false,
213};
214
215static struct ti_cpufreq_soc_data am4x_soc_data = {
216 .efuse_xlate = amx3_efuse_xlate,
217 .efuse_fallback = AM43XX_600M_ARM_MPU_MAX_FREQ,
218 .efuse_offset = 0x0610,
219 .efuse_mask = 0x3f,
220 .rev_offset = 0x600,
221 .multi_regulator = false,
222};
223
224static struct ti_cpufreq_soc_data dra7_soc_data = {
225 .efuse_xlate = dra7_efuse_xlate,
226 .efuse_offset = 0x020c,
227 .efuse_mask = 0xf80000,
228 .efuse_shift = 19,
229 .rev_offset = 0x204,
230 .multi_regulator = true,
231};
232
233/*
234 * OMAP35x TRM (SPRUF98K):
235 * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
236 * Control OMAP Status Register 15:0 (Address 0x4800 244C)
237 * to separate between omap3503, omap3515, omap3525, omap3530
238 * and feature presence.
239 * There are encodings for versions limited to 400/266MHz
240 * but we ignore.
241 * Not clear if this also holds for omap34xx.
242 * some eFuse values e.g. CONTROL_FUSE_OPP1_VDD1
243 * are stored in the SYSCON register range
244 * Register 0x4830A20C [ProdID.SKUID] [0:3]
245 * 0x0 for normal 600/430MHz device.
246 * 0x8 for 720/520MHz device.
247 * Not clear what omap34xx value is.
248 */
249
250static struct ti_cpufreq_soc_data omap34xx_soc_data = {
251 .efuse_xlate = omap3_efuse_xlate,
252 .efuse_offset = OMAP34xx_ProdID_SKUID - OMAP3_SYSCON_BASE,
253 .efuse_shift = 3,
254 .efuse_mask = BIT(3),
255 .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
256 .multi_regulator = false,
257};
258
259/*
260 * AM/DM37x TRM (SPRUGN4M)
261 * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
262 * Control Device Status Register 15:0 (Address 0x4800 244C)
263 * to separate between am3703, am3715, dm3725, dm3730
264 * and feature presence.
265 * Speed Binned = Bit 9
266 * 0 800/600 MHz
267 * 1 1000/800 MHz
268 * some eFuse values e.g. CONTROL_FUSE_OPP 1G_VDD1
269 * are stored in the SYSCON register range.
270 * There is no 0x4830A20C [ProdID.SKUID] register (exists but
271 * seems to always read as 0).
272 */
273
274static const char * const omap3_reg_names[] = {"cpu0", "vbb", NULL};
275
276static struct ti_cpufreq_soc_data omap36xx_soc_data = {
277 .reg_names = omap3_reg_names,
278 .efuse_xlate = omap3_efuse_xlate,
279 .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE,
280 .efuse_shift = 9,
281 .efuse_mask = BIT(9),
282 .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
283 .multi_regulator = true,
284};
285
286/*
287 * AM3517 is quite similar to AM/DM37x except that it has no
288 * high speed grade eFuse and no abb ldo
289 */
290
291static struct ti_cpufreq_soc_data am3517_soc_data = {
292 .efuse_xlate = omap3_efuse_xlate,
293 .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE,
294 .efuse_shift = 0,
295 .efuse_mask = 0,
296 .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
297 .multi_regulator = false,
298};
299
300static struct ti_cpufreq_soc_data am625_soc_data = {
301 .efuse_xlate = am625_efuse_xlate,
302 .efuse_offset = 0x0018,
303 .efuse_mask = 0x07c0,
304 .efuse_shift = 0x6,
305 .rev_offset = 0x0014,
306 .multi_regulator = false,
307};
308
309static struct ti_cpufreq_soc_data am62a7_soc_data = {
310 .efuse_xlate = am62a7_efuse_xlate,
311 .efuse_offset = 0x0,
312 .efuse_mask = 0x07c0,
313 .efuse_shift = 0x6,
314 .rev_offset = 0x0014,
315 .multi_regulator = false,
316};
317
318static struct ti_cpufreq_soc_data am62p5_soc_data = {
319 .efuse_xlate = am62p5_efuse_xlate,
320 .efuse_offset = 0x0,
321 .efuse_mask = 0x07c0,
322 .efuse_shift = 0x6,
323 .rev_offset = 0x0014,
324 .multi_regulator = false,
325};
326
327/**
328 * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC
329 * @opp_data: pointer to ti_cpufreq_data context
330 * @efuse_value: Set to the value parsed from efuse
331 *
332 * Returns error code if efuse not read properly.
333 */
334static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data,
335 u32 *efuse_value)
336{
337 struct device *dev = opp_data->cpu_dev;
338 u32 efuse;
339 int ret;
340
341 ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset,
342 &efuse);
343 if (ret == -EIO) {
344 /* not a syscon register! */
345 void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
346 opp_data->soc_data->efuse_offset, 4);
347
348 if (!regs)
349 return -ENOMEM;
350 efuse = readl(regs);
351 iounmap(regs);
352 }
353 else if (ret) {
354 dev_err(dev,
355 "Failed to read the efuse value from syscon: %d\n",
356 ret);
357 return ret;
358 }
359
360 efuse = (efuse & opp_data->soc_data->efuse_mask);
361 efuse >>= opp_data->soc_data->efuse_shift;
362
363 *efuse_value = opp_data->soc_data->efuse_xlate(opp_data, efuse);
364
365 return 0;
366}
367
368/**
369 * ti_cpufreq_get_rev() - Parse and return rev value present on SoC
370 * @opp_data: pointer to ti_cpufreq_data context
371 * @revision_value: Set to the value parsed from revision register
372 *
373 * Returns error code if revision not read properly.
374 */
375static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data,
376 u32 *revision_value)
377{
378 struct device *dev = opp_data->cpu_dev;
379 u32 revision;
380 int ret;
381
382 ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset,
383 &revision);
384 if (ret == -EIO) {
385 /* not a syscon register! */
386 void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
387 opp_data->soc_data->rev_offset, 4);
388
389 if (!regs)
390 return -ENOMEM;
391 revision = readl(regs);
392 iounmap(regs);
393 }
394 else if (ret) {
395 dev_err(dev,
396 "Failed to read the revision number from syscon: %d\n",
397 ret);
398 return ret;
399 }
400
401 *revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK);
402
403 return 0;
404}
405
406static int ti_cpufreq_setup_syscon_register(struct ti_cpufreq_data *opp_data)
407{
408 struct device *dev = opp_data->cpu_dev;
409 struct device_node *np = opp_data->opp_node;
410
411 opp_data->syscon = syscon_regmap_lookup_by_phandle(np,
412 "syscon");
413 if (IS_ERR(opp_data->syscon)) {
414 dev_err(dev,
415 "\"syscon\" is missing, cannot use OPPv2 table.\n");
416 return PTR_ERR(opp_data->syscon);
417 }
418
419 return 0;
420}
421
422static const struct of_device_id ti_cpufreq_of_match[] = {
423 { .compatible = "ti,am33xx", .data = &am3x_soc_data, },
424 { .compatible = "ti,am3517", .data = &am3517_soc_data, },
425 { .compatible = "ti,am43", .data = &am4x_soc_data, },
426 { .compatible = "ti,dra7", .data = &dra7_soc_data },
427 { .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, },
428 { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, },
429 { .compatible = "ti,am625", .data = &am625_soc_data, },
430 { .compatible = "ti,am62a7", .data = &am62a7_soc_data, },
431 { .compatible = "ti,am62p5", .data = &am62p5_soc_data, },
432 /* legacy */
433 { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },
434 { .compatible = "ti,omap3630", .data = &omap36xx_soc_data, },
435 {},
436};
437
438static const struct of_device_id *ti_cpufreq_match_node(void)
439{
440 struct device_node *np __free(device_node) = of_find_node_by_path("/");
441 const struct of_device_id *match;
442
443 match = of_match_node(ti_cpufreq_of_match, np);
444
445 return match;
446}
447
448static int ti_cpufreq_probe(struct platform_device *pdev)
449{
450 u32 version[VERSION_COUNT];
451 const struct of_device_id *match;
452 struct ti_cpufreq_data *opp_data;
453 const char * const default_reg_names[] = {"vdd", "vbb", NULL};
454 int ret;
455 struct dev_pm_opp_config config = {
456 .supported_hw = version,
457 .supported_hw_count = ARRAY_SIZE(version),
458 };
459
460 match = dev_get_platdata(&pdev->dev);
461 if (!match)
462 return -ENODEV;
463
464 opp_data = devm_kzalloc(&pdev->dev, sizeof(*opp_data), GFP_KERNEL);
465 if (!opp_data)
466 return -ENOMEM;
467
468 opp_data->soc_data = match->data;
469
470 opp_data->cpu_dev = get_cpu_device(0);
471 if (!opp_data->cpu_dev) {
472 pr_err("%s: Failed to get device for CPU0\n", __func__);
473 return -ENODEV;
474 }
475
476 opp_data->opp_node = dev_pm_opp_of_get_opp_desc_node(opp_data->cpu_dev);
477 if (!opp_data->opp_node) {
478 dev_info(opp_data->cpu_dev,
479 "OPP-v2 not supported, cpufreq-dt will attempt to use legacy tables.\n");
480 goto register_cpufreq_dt;
481 }
482
483 ret = ti_cpufreq_setup_syscon_register(opp_data);
484 if (ret)
485 goto fail_put_node;
486
487 /*
488 * OPPs determine whether or not they are supported based on
489 * two metrics:
490 * 0 - SoC Revision
491 * 1 - eFuse value
492 */
493 ret = ti_cpufreq_get_rev(opp_data, &version[0]);
494 if (ret)
495 goto fail_put_node;
496
497 ret = ti_cpufreq_get_efuse(opp_data, &version[1]);
498 if (ret)
499 goto fail_put_node;
500
501 if (opp_data->soc_data->multi_regulator) {
502 if (opp_data->soc_data->reg_names)
503 config.regulator_names = opp_data->soc_data->reg_names;
504 else
505 config.regulator_names = default_reg_names;
506 }
507
508 ret = dev_pm_opp_set_config(opp_data->cpu_dev, &config);
509 if (ret < 0) {
510 dev_err_probe(opp_data->cpu_dev, ret, "Failed to set OPP config\n");
511 goto fail_put_node;
512 }
513
514 of_node_put(opp_data->opp_node);
515
516register_cpufreq_dt:
517 platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
518
519 return 0;
520
521fail_put_node:
522 of_node_put(opp_data->opp_node);
523
524 return ret;
525}
526
527static int __init ti_cpufreq_init(void)
528{
529 const struct of_device_id *match;
530
531 /* Check to ensure we are on a compatible platform */
532 match = ti_cpufreq_match_node();
533 if (match)
534 platform_device_register_data(NULL, "ti-cpufreq", -1, match,
535 sizeof(*match));
536
537 return 0;
538}
539module_init(ti_cpufreq_init);
540
541static struct platform_driver ti_cpufreq_driver = {
542 .probe = ti_cpufreq_probe,
543 .driver = {
544 .name = "ti-cpufreq",
545 },
546};
547builtin_platform_driver(ti_cpufreq_driver);
548
549MODULE_DESCRIPTION("TI CPUFreq/OPP hw-supported driver");
550MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");
551MODULE_LICENSE("GPL v2");