tjh.dev
Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0
2/* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs.
3 *
4 * Copyright (C) 2017 Texas Instruments Inc.
5 */
6
7#include <linux/ethtool.h>
8#include <linux/etherdevice.h>
9#include <linux/kernel.h>
10#include <linux/mii.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/phy.h>
14#include <linux/netdevice.h>
15#include <linux/bitfield.h>
16
17#define DP83822_PHY_ID 0x2000a240
18#define DP83825S_PHY_ID 0x2000a140
19#define DP83825I_PHY_ID 0x2000a150
20#define DP83825CM_PHY_ID 0x2000a160
21#define DP83825CS_PHY_ID 0x2000a170
22#define DP83826C_PHY_ID 0x2000a130
23#define DP83826NC_PHY_ID 0x2000a110
24
25#define DP83822_DEVADDR 0x1f
26
27#define MII_DP83822_CTRL_2 0x0a
28#define MII_DP83822_PHYSTS 0x10
29#define MII_DP83822_PHYSCR 0x11
30#define MII_DP83822_MISR1 0x12
31#define MII_DP83822_MISR2 0x13
32#define MII_DP83822_FCSCR 0x14
33#define MII_DP83822_RCSR 0x17
34#define MII_DP83822_RESET_CTRL 0x1f
35#define MII_DP83822_GENCFG 0x465
36#define MII_DP83822_SOR1 0x467
37
38/* DP83826 specific registers */
39#define MII_DP83826_VOD_CFG1 0x30b
40#define MII_DP83826_VOD_CFG2 0x30c
41
42/* GENCFG */
43#define DP83822_SIG_DET_LOW BIT(0)
44
45/* Control Register 2 bits */
46#define DP83822_FX_ENABLE BIT(14)
47
48#define DP83822_HW_RESET BIT(15)
49#define DP83822_SW_RESET BIT(14)
50
51/* PHY STS bits */
52#define DP83822_PHYSTS_DUPLEX BIT(2)
53#define DP83822_PHYSTS_10 BIT(1)
54#define DP83822_PHYSTS_LINK BIT(0)
55
56/* PHYSCR Register Fields */
57#define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */
58#define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */
59
60/* MISR1 bits */
61#define DP83822_RX_ERR_HF_INT_EN BIT(0)
62#define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1)
63#define DP83822_ANEG_COMPLETE_INT_EN BIT(2)
64#define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3)
65#define DP83822_SPEED_CHANGED_INT_EN BIT(4)
66#define DP83822_LINK_STAT_INT_EN BIT(5)
67#define DP83822_ENERGY_DET_INT_EN BIT(6)
68#define DP83822_LINK_QUAL_INT_EN BIT(7)
69
70/* MISR2 bits */
71#define DP83822_JABBER_DET_INT_EN BIT(0)
72#define DP83822_WOL_PKT_INT_EN BIT(1)
73#define DP83822_SLEEP_MODE_INT_EN BIT(2)
74#define DP83822_MDI_XOVER_INT_EN BIT(3)
75#define DP83822_LB_FIFO_INT_EN BIT(4)
76#define DP83822_PAGE_RX_INT_EN BIT(5)
77#define DP83822_ANEG_ERR_INT_EN BIT(6)
78#define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7)
79
80/* INT_STAT1 bits */
81#define DP83822_WOL_INT_EN BIT(4)
82#define DP83822_WOL_INT_STAT BIT(12)
83
84#define MII_DP83822_RXSOP1 0x04a5
85#define MII_DP83822_RXSOP2 0x04a6
86#define MII_DP83822_RXSOP3 0x04a7
87
88/* WoL Registers */
89#define MII_DP83822_WOL_CFG 0x04a0
90#define MII_DP83822_WOL_STAT 0x04a1
91#define MII_DP83822_WOL_DA1 0x04a2
92#define MII_DP83822_WOL_DA2 0x04a3
93#define MII_DP83822_WOL_DA3 0x04a4
94
95/* WoL bits */
96#define DP83822_WOL_MAGIC_EN BIT(0)
97#define DP83822_WOL_SECURE_ON BIT(5)
98#define DP83822_WOL_EN BIT(7)
99#define DP83822_WOL_INDICATION_SEL BIT(8)
100#define DP83822_WOL_CLR_INDICATION BIT(11)
101
102/* RCSR bits */
103#define DP83822_RMII_MODE_EN BIT(5)
104#define DP83822_RMII_MODE_SEL BIT(7)
105#define DP83822_RGMII_MODE_EN BIT(9)
106#define DP83822_RX_CLK_SHIFT BIT(12)
107#define DP83822_TX_CLK_SHIFT BIT(11)
108
109/* SOR1 mode */
110#define DP83822_STRAP_MODE1 0
111#define DP83822_STRAP_MODE2 BIT(0)
112#define DP83822_STRAP_MODE3 BIT(1)
113#define DP83822_STRAP_MODE4 GENMASK(1, 0)
114
115#define DP83822_COL_STRAP_MASK GENMASK(11, 10)
116#define DP83822_COL_SHIFT 10
117#define DP83822_RX_ER_STR_MASK GENMASK(9, 8)
118#define DP83822_RX_ER_SHIFT 8
119
120/* DP83826: VOD_CFG1 & VOD_CFG2 */
121#define DP83826_VOD_CFG1_MINUS_MDIX_MASK GENMASK(13, 12)
122#define DP83826_VOD_CFG1_MINUS_MDI_MASK GENMASK(11, 6)
123#define DP83826_VOD_CFG2_MINUS_MDIX_MASK GENMASK(15, 12)
124#define DP83826_VOD_CFG2_PLUS_MDIX_MASK GENMASK(11, 6)
125#define DP83826_VOD_CFG2_PLUS_MDI_MASK GENMASK(5, 0)
126#define DP83826_CFG_DAC_MINUS_MDIX_5_TO_4 GENMASK(5, 4)
127#define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0 GENMASK(3, 0)
128#define DP83826_CFG_DAC_PERCENT_PER_STEP 625
129#define DP83826_CFG_DAC_PERCENT_DEFAULT 10000
130#define DP83826_CFG_DAC_MINUS_DEFAULT 0x30
131#define DP83826_CFG_DAC_PLUS_DEFAULT 0x10
132
133#define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \
134 ADVERTISED_FIBRE | \
135 ADVERTISED_Pause | ADVERTISED_Asym_Pause)
136
137struct dp83822_private {
138 bool fx_signal_det_low;
139 int fx_enabled;
140 u16 fx_sd_enable;
141 u8 cfg_dac_minus;
142 u8 cfg_dac_plus;
143 struct ethtool_wolinfo wol;
144};
145
146static int dp83822_config_wol(struct phy_device *phydev,
147 struct ethtool_wolinfo *wol)
148{
149 struct net_device *ndev = phydev->attached_dev;
150 u16 value;
151 const u8 *mac;
152
153 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
154 mac = (const u8 *)ndev->dev_addr;
155
156 if (!is_valid_ether_addr(mac))
157 return -EINVAL;
158
159 /* MAC addresses start with byte 5, but stored in mac[0].
160 * 822 PHYs store bytes 4|5, 2|3, 0|1
161 */
162 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1,
163 (mac[1] << 8) | mac[0]);
164 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2,
165 (mac[3] << 8) | mac[2]);
166 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3,
167 (mac[5] << 8) | mac[4]);
168
169 value = phy_read_mmd(phydev, DP83822_DEVADDR,
170 MII_DP83822_WOL_CFG);
171 if (wol->wolopts & WAKE_MAGIC)
172 value |= DP83822_WOL_MAGIC_EN;
173 else
174 value &= ~DP83822_WOL_MAGIC_EN;
175
176 if (wol->wolopts & WAKE_MAGICSECURE) {
177 phy_write_mmd(phydev, DP83822_DEVADDR,
178 MII_DP83822_RXSOP1,
179 (wol->sopass[1] << 8) | wol->sopass[0]);
180 phy_write_mmd(phydev, DP83822_DEVADDR,
181 MII_DP83822_RXSOP2,
182 (wol->sopass[3] << 8) | wol->sopass[2]);
183 phy_write_mmd(phydev, DP83822_DEVADDR,
184 MII_DP83822_RXSOP3,
185 (wol->sopass[5] << 8) | wol->sopass[4]);
186 value |= DP83822_WOL_SECURE_ON;
187 } else {
188 value &= ~DP83822_WOL_SECURE_ON;
189 }
190
191 /* Clear any pending WoL interrupt */
192 phy_read(phydev, MII_DP83822_MISR2);
193
194 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL |
195 DP83822_WOL_CLR_INDICATION;
196
197 return phy_write_mmd(phydev, DP83822_DEVADDR,
198 MII_DP83822_WOL_CFG, value);
199 } else {
200 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
201 MII_DP83822_WOL_CFG,
202 DP83822_WOL_EN |
203 DP83822_WOL_MAGIC_EN |
204 DP83822_WOL_SECURE_ON);
205 }
206}
207
208static int dp83822_set_wol(struct phy_device *phydev,
209 struct ethtool_wolinfo *wol)
210{
211 struct dp83822_private *dp83822 = phydev->priv;
212 int ret;
213
214 ret = dp83822_config_wol(phydev, wol);
215 if (!ret)
216 memcpy(&dp83822->wol, wol, sizeof(*wol));
217 return ret;
218}
219
220static void dp83822_get_wol(struct phy_device *phydev,
221 struct ethtool_wolinfo *wol)
222{
223 int value;
224 u16 sopass_val;
225
226 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
227 wol->wolopts = 0;
228
229 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
230
231 if (value & DP83822_WOL_MAGIC_EN)
232 wol->wolopts |= WAKE_MAGIC;
233
234 if (value & DP83822_WOL_SECURE_ON) {
235 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
236 MII_DP83822_RXSOP1);
237 wol->sopass[0] = (sopass_val & 0xff);
238 wol->sopass[1] = (sopass_val >> 8);
239
240 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
241 MII_DP83822_RXSOP2);
242 wol->sopass[2] = (sopass_val & 0xff);
243 wol->sopass[3] = (sopass_val >> 8);
244
245 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
246 MII_DP83822_RXSOP3);
247 wol->sopass[4] = (sopass_val & 0xff);
248 wol->sopass[5] = (sopass_val >> 8);
249
250 wol->wolopts |= WAKE_MAGICSECURE;
251 }
252
253 /* WoL is not enabled so set wolopts to 0 */
254 if (!(value & DP83822_WOL_EN))
255 wol->wolopts = 0;
256}
257
258static int dp83822_config_intr(struct phy_device *phydev)
259{
260 struct dp83822_private *dp83822 = phydev->priv;
261 int misr_status;
262 int physcr_status;
263 int err;
264
265 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
266 misr_status = phy_read(phydev, MII_DP83822_MISR1);
267 if (misr_status < 0)
268 return misr_status;
269
270 misr_status |= (DP83822_LINK_STAT_INT_EN |
271 DP83822_ENERGY_DET_INT_EN |
272 DP83822_LINK_QUAL_INT_EN);
273
274 /* Private data pointer is NULL on DP83825 */
275 if (!dp83822 || !dp83822->fx_enabled)
276 misr_status |= DP83822_ANEG_COMPLETE_INT_EN |
277 DP83822_DUP_MODE_CHANGE_INT_EN |
278 DP83822_SPEED_CHANGED_INT_EN;
279
280
281 err = phy_write(phydev, MII_DP83822_MISR1, misr_status);
282 if (err < 0)
283 return err;
284
285 misr_status = phy_read(phydev, MII_DP83822_MISR2);
286 if (misr_status < 0)
287 return misr_status;
288
289 misr_status |= (DP83822_JABBER_DET_INT_EN |
290 DP83822_SLEEP_MODE_INT_EN |
291 DP83822_LB_FIFO_INT_EN |
292 DP83822_PAGE_RX_INT_EN |
293 DP83822_EEE_ERROR_CHANGE_INT_EN);
294
295 /* Private data pointer is NULL on DP83825 */
296 if (!dp83822 || !dp83822->fx_enabled)
297 misr_status |= DP83822_ANEG_ERR_INT_EN |
298 DP83822_WOL_PKT_INT_EN;
299
300 err = phy_write(phydev, MII_DP83822_MISR2, misr_status);
301 if (err < 0)
302 return err;
303
304 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
305 if (physcr_status < 0)
306 return physcr_status;
307
308 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN;
309
310 } else {
311 err = phy_write(phydev, MII_DP83822_MISR1, 0);
312 if (err < 0)
313 return err;
314
315 err = phy_write(phydev, MII_DP83822_MISR2, 0);
316 if (err < 0)
317 return err;
318
319 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
320 if (physcr_status < 0)
321 return physcr_status;
322
323 physcr_status &= ~DP83822_PHYSCR_INTEN;
324 }
325
326 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status);
327}
328
329static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev)
330{
331 bool trigger_machine = false;
332 int irq_status;
333
334 /* The MISR1 and MISR2 registers are holding the interrupt status in
335 * the upper half (15:8), while the lower half (7:0) is used for
336 * controlling the interrupt enable state of those individual interrupt
337 * sources. To determine the possible interrupt sources, just read the
338 * MISR* register and use it directly to know which interrupts have
339 * been enabled previously or not.
340 */
341 irq_status = phy_read(phydev, MII_DP83822_MISR1);
342 if (irq_status < 0) {
343 phy_error(phydev);
344 return IRQ_NONE;
345 }
346 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
347 trigger_machine = true;
348
349 irq_status = phy_read(phydev, MII_DP83822_MISR2);
350 if (irq_status < 0) {
351 phy_error(phydev);
352 return IRQ_NONE;
353 }
354 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
355 trigger_machine = true;
356
357 if (!trigger_machine)
358 return IRQ_NONE;
359
360 phy_trigger_machine(phydev);
361
362 return IRQ_HANDLED;
363}
364
365static int dp83822_read_status(struct phy_device *phydev)
366{
367 struct dp83822_private *dp83822 = phydev->priv;
368 int status = phy_read(phydev, MII_DP83822_PHYSTS);
369 int ctrl2;
370 int ret;
371
372 if (dp83822->fx_enabled) {
373 if (status & DP83822_PHYSTS_LINK) {
374 phydev->speed = SPEED_UNKNOWN;
375 phydev->duplex = DUPLEX_UNKNOWN;
376 } else {
377 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2);
378 if (ctrl2 < 0)
379 return ctrl2;
380
381 if (!(ctrl2 & DP83822_FX_ENABLE)) {
382 ret = phy_write(phydev, MII_DP83822_CTRL_2,
383 DP83822_FX_ENABLE | ctrl2);
384 if (ret < 0)
385 return ret;
386 }
387 }
388 }
389
390 ret = genphy_read_status(phydev);
391 if (ret)
392 return ret;
393
394 if (status < 0)
395 return status;
396
397 if (status & DP83822_PHYSTS_DUPLEX)
398 phydev->duplex = DUPLEX_FULL;
399 else
400 phydev->duplex = DUPLEX_HALF;
401
402 if (status & DP83822_PHYSTS_10)
403 phydev->speed = SPEED_10;
404 else
405 phydev->speed = SPEED_100;
406
407 return 0;
408}
409
410static int dp83822_config_init(struct phy_device *phydev)
411{
412 struct dp83822_private *dp83822 = phydev->priv;
413 struct device *dev = &phydev->mdio.dev;
414 int rgmii_delay = 0;
415 s32 rx_int_delay;
416 s32 tx_int_delay;
417 int err = 0;
418 int bmcr;
419
420 if (phy_interface_is_rgmii(phydev)) {
421 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
422 true);
423
424 /* Set DP83822_RX_CLK_SHIFT to enable rx clk internal delay */
425 if (rx_int_delay > 0)
426 rgmii_delay |= DP83822_RX_CLK_SHIFT;
427
428 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
429 false);
430
431 /* Set DP83822_TX_CLK_SHIFT to disable tx clk internal delay */
432 if (tx_int_delay <= 0)
433 rgmii_delay |= DP83822_TX_CLK_SHIFT;
434
435 err = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
436 DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay);
437 if (err)
438 return err;
439
440 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
441 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
442
443 if (err)
444 return err;
445 } else {
446 err = phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
447 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
448
449 if (err)
450 return err;
451 }
452
453 if (dp83822->fx_enabled) {
454 err = phy_modify(phydev, MII_DP83822_CTRL_2,
455 DP83822_FX_ENABLE, 1);
456 if (err < 0)
457 return err;
458
459 /* Only allow advertising what this PHY supports */
460 linkmode_and(phydev->advertising, phydev->advertising,
461 phydev->supported);
462
463 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
464 phydev->supported);
465 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
466 phydev->advertising);
467 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
468 phydev->supported);
469 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
470 phydev->supported);
471 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
472 phydev->advertising);
473 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
474 phydev->advertising);
475
476 /* Auto neg is not supported in fiber mode */
477 bmcr = phy_read(phydev, MII_BMCR);
478 if (bmcr < 0)
479 return bmcr;
480
481 if (bmcr & BMCR_ANENABLE) {
482 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
483 if (err < 0)
484 return err;
485 }
486 phydev->autoneg = AUTONEG_DISABLE;
487 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
488 phydev->supported);
489 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
490 phydev->advertising);
491
492 /* Setup fiber advertisement */
493 err = phy_modify_changed(phydev, MII_ADVERTISE,
494 MII_DP83822_FIBER_ADVERTISE,
495 MII_DP83822_FIBER_ADVERTISE);
496
497 if (err < 0)
498 return err;
499
500 if (dp83822->fx_signal_det_low) {
501 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
502 MII_DP83822_GENCFG,
503 DP83822_SIG_DET_LOW);
504 if (err)
505 return err;
506 }
507 }
508 return dp83822_config_wol(phydev, &dp83822->wol);
509}
510
511static int dp83826_config_rmii_mode(struct phy_device *phydev)
512{
513 struct device *dev = &phydev->mdio.dev;
514 const char *of_val;
515 int ret;
516
517 if (!device_property_read_string(dev, "ti,rmii-mode", &of_val)) {
518 if (strcmp(of_val, "master") == 0) {
519 ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
520 DP83822_RMII_MODE_SEL);
521 } else if (strcmp(of_val, "slave") == 0) {
522 ret = phy_set_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
523 DP83822_RMII_MODE_SEL);
524 } else {
525 phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n",
526 of_val);
527 ret = -EINVAL;
528 }
529
530 if (ret)
531 return ret;
532 }
533
534 return 0;
535}
536
537static int dp83826_config_init(struct phy_device *phydev)
538{
539 struct dp83822_private *dp83822 = phydev->priv;
540 u16 val, mask;
541 int ret;
542
543 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
544 ret = phy_set_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
545 DP83822_RMII_MODE_EN);
546 if (ret)
547 return ret;
548
549 ret = dp83826_config_rmii_mode(phydev);
550 if (ret)
551 return ret;
552 } else {
553 ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
554 DP83822_RMII_MODE_EN);
555 if (ret)
556 return ret;
557 }
558
559 if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) {
560 val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) |
561 FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK,
562 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_5_TO_4,
563 dp83822->cfg_dac_minus));
564 mask = DP83826_VOD_CFG1_MINUS_MDIX_MASK | DP83826_VOD_CFG1_MINUS_MDI_MASK;
565 ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG1, mask, val);
566 if (ret)
567 return ret;
568
569 val = FIELD_PREP(DP83826_VOD_CFG2_MINUS_MDIX_MASK,
570 FIELD_GET(DP83826_CFG_DAC_MINUS_MDIX_3_TO_0,
571 dp83822->cfg_dac_minus));
572 mask = DP83826_VOD_CFG2_MINUS_MDIX_MASK;
573 ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG2, mask, val);
574 if (ret)
575 return ret;
576 }
577
578 if (dp83822->cfg_dac_plus != DP83826_CFG_DAC_PLUS_DEFAULT) {
579 val = FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDIX_MASK, dp83822->cfg_dac_plus) |
580 FIELD_PREP(DP83826_VOD_CFG2_PLUS_MDI_MASK, dp83822->cfg_dac_plus);
581 mask = DP83826_VOD_CFG2_PLUS_MDIX_MASK | DP83826_VOD_CFG2_PLUS_MDI_MASK;
582 ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83826_VOD_CFG2, mask, val);
583 if (ret)
584 return ret;
585 }
586
587 return dp83822_config_wol(phydev, &dp83822->wol);
588}
589
590static int dp8382x_config_init(struct phy_device *phydev)
591{
592 struct dp83822_private *dp83822 = phydev->priv;
593
594 return dp83822_config_wol(phydev, &dp83822->wol);
595}
596
597static int dp83822_phy_reset(struct phy_device *phydev)
598{
599 int err;
600
601 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET);
602 if (err < 0)
603 return err;
604
605 return phydev->drv->config_init(phydev);
606}
607
608#ifdef CONFIG_OF_MDIO
609static int dp83822_of_init(struct phy_device *phydev)
610{
611 struct dp83822_private *dp83822 = phydev->priv;
612 struct device *dev = &phydev->mdio.dev;
613
614 /* Signal detection for the PHY is only enabled if the FX_EN and the
615 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN
616 * is strapped otherwise signal detection is disabled for the PHY.
617 */
618 if (dp83822->fx_enabled && dp83822->fx_sd_enable)
619 dp83822->fx_signal_det_low = device_property_present(dev,
620 "ti,link-loss-low");
621 if (!dp83822->fx_enabled)
622 dp83822->fx_enabled = device_property_present(dev,
623 "ti,fiber-mode");
624
625 return 0;
626}
627
628static int dp83826_to_dac_minus_one_regval(int percent)
629{
630 int tmp = DP83826_CFG_DAC_PERCENT_DEFAULT - percent;
631
632 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP;
633}
634
635static int dp83826_to_dac_plus_one_regval(int percent)
636{
637 int tmp = percent - DP83826_CFG_DAC_PERCENT_DEFAULT;
638
639 return tmp / DP83826_CFG_DAC_PERCENT_PER_STEP;
640}
641
642static void dp83826_of_init(struct phy_device *phydev)
643{
644 struct dp83822_private *dp83822 = phydev->priv;
645 struct device *dev = &phydev->mdio.dev;
646 u32 val;
647
648 dp83822->cfg_dac_minus = DP83826_CFG_DAC_MINUS_DEFAULT;
649 if (!device_property_read_u32(dev, "ti,cfg-dac-minus-one-bp", &val))
650 dp83822->cfg_dac_minus += dp83826_to_dac_minus_one_regval(val);
651
652 dp83822->cfg_dac_plus = DP83826_CFG_DAC_PLUS_DEFAULT;
653 if (!device_property_read_u32(dev, "ti,cfg-dac-plus-one-bp", &val))
654 dp83822->cfg_dac_plus += dp83826_to_dac_plus_one_regval(val);
655}
656#else
657static int dp83822_of_init(struct phy_device *phydev)
658{
659 return 0;
660}
661
662static void dp83826_of_init(struct phy_device *phydev)
663{
664}
665#endif /* CONFIG_OF_MDIO */
666
667static int dp83822_read_straps(struct phy_device *phydev)
668{
669 struct dp83822_private *dp83822 = phydev->priv;
670 int fx_enabled, fx_sd_enable;
671 int val;
672
673 val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1);
674 if (val < 0)
675 return val;
676
677 phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val);
678
679 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT;
680 if (fx_enabled == DP83822_STRAP_MODE2 ||
681 fx_enabled == DP83822_STRAP_MODE3)
682 dp83822->fx_enabled = 1;
683
684 if (dp83822->fx_enabled) {
685 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT;
686 if (fx_sd_enable == DP83822_STRAP_MODE3 ||
687 fx_sd_enable == DP83822_STRAP_MODE4)
688 dp83822->fx_sd_enable = 1;
689 }
690
691 return 0;
692}
693
694static int dp83822_probe(struct phy_device *phydev)
695{
696 struct dp83822_private *dp83822;
697 int ret;
698
699 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
700 GFP_KERNEL);
701 if (!dp83822)
702 return -ENOMEM;
703
704 phydev->priv = dp83822;
705
706 ret = dp83822_read_straps(phydev);
707 if (ret)
708 return ret;
709
710 dp83822_of_init(phydev);
711
712 if (dp83822->fx_enabled)
713 phydev->port = PORT_FIBRE;
714
715 return 0;
716}
717
718static int dp83826_probe(struct phy_device *phydev)
719{
720 struct dp83822_private *dp83822;
721
722 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
723 GFP_KERNEL);
724 if (!dp83822)
725 return -ENOMEM;
726
727 phydev->priv = dp83822;
728
729 dp83826_of_init(phydev);
730
731 return 0;
732}
733
734static int dp83822_suspend(struct phy_device *phydev)
735{
736 int value;
737
738 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
739
740 if (!(value & DP83822_WOL_EN))
741 genphy_suspend(phydev);
742
743 return 0;
744}
745
746static int dp83822_resume(struct phy_device *phydev)
747{
748 int value;
749
750 genphy_resume(phydev);
751
752 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
753
754 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value |
755 DP83822_WOL_CLR_INDICATION);
756
757 return 0;
758}
759
760#define DP83822_PHY_DRIVER(_id, _name) \
761 { \
762 PHY_ID_MATCH_MODEL(_id), \
763 .name = (_name), \
764 /* PHY_BASIC_FEATURES */ \
765 .probe = dp83822_probe, \
766 .soft_reset = dp83822_phy_reset, \
767 .config_init = dp83822_config_init, \
768 .read_status = dp83822_read_status, \
769 .get_wol = dp83822_get_wol, \
770 .set_wol = dp83822_set_wol, \
771 .config_intr = dp83822_config_intr, \
772 .handle_interrupt = dp83822_handle_interrupt, \
773 .suspend = dp83822_suspend, \
774 .resume = dp83822_resume, \
775 }
776
777#define DP83826_PHY_DRIVER(_id, _name) \
778 { \
779 PHY_ID_MATCH_MODEL(_id), \
780 .name = (_name), \
781 /* PHY_BASIC_FEATURES */ \
782 .probe = dp83826_probe, \
783 .soft_reset = dp83822_phy_reset, \
784 .config_init = dp83826_config_init, \
785 .get_wol = dp83822_get_wol, \
786 .set_wol = dp83822_set_wol, \
787 .config_intr = dp83822_config_intr, \
788 .handle_interrupt = dp83822_handle_interrupt, \
789 .suspend = dp83822_suspend, \
790 .resume = dp83822_resume, \
791 }
792
793#define DP8382X_PHY_DRIVER(_id, _name) \
794 { \
795 PHY_ID_MATCH_MODEL(_id), \
796 .name = (_name), \
797 /* PHY_BASIC_FEATURES */ \
798 .soft_reset = dp83822_phy_reset, \
799 .config_init = dp8382x_config_init, \
800 .get_wol = dp83822_get_wol, \
801 .set_wol = dp83822_set_wol, \
802 .config_intr = dp83822_config_intr, \
803 .handle_interrupt = dp83822_handle_interrupt, \
804 .suspend = dp83822_suspend, \
805 .resume = dp83822_resume, \
806 }
807
808static struct phy_driver dp83822_driver[] = {
809 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"),
810 DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"),
811 DP83826_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
812 DP83826_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
813 DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"),
814 DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"),
815 DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"),
816};
817module_phy_driver(dp83822_driver);
818
819static struct mdio_device_id __maybe_unused dp83822_tbl[] = {
820 { DP83822_PHY_ID, 0xfffffff0 },
821 { DP83825I_PHY_ID, 0xfffffff0 },
822 { DP83826C_PHY_ID, 0xfffffff0 },
823 { DP83826NC_PHY_ID, 0xfffffff0 },
824 { DP83825S_PHY_ID, 0xfffffff0 },
825 { DP83825CM_PHY_ID, 0xfffffff0 },
826 { DP83825CS_PHY_ID, 0xfffffff0 },
827 { },
828};
829MODULE_DEVICE_TABLE(mdio, dp83822_tbl);
830
831MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver");
832MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
833MODULE_LICENSE("GPL v2");