tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2
3#include <linux/clk.h>
4#include <linux/interconnect-provider.h>
5#include <linux/mod_devicetable.h>
6#include <linux/module.h>
7#include <linux/of_device.h>
8#include <linux/platform_device.h>
9#include <linux/regmap.h>
10
11#include <dt-bindings/interconnect/qcom,msm8953.h>
12
13#include "icc-rpm.h"
14
15enum {
16 MSM8953_MASTER_AMPSS_M0 = 1,
17 MSM8953_MASTER_GRAPHICS_3D,
18 MSM8953_SNOC_BIMC_0_MAS,
19 MSM8953_SNOC_BIMC_2_MAS,
20 MSM8953_SNOC_BIMC_1_MAS,
21 MSM8953_MASTER_TCU_0,
22 MSM8953_SLAVE_EBI_CH0,
23 MSM8953_BIMC_SNOC_SLV,
24 MSM8953_MASTER_SPDM,
25 MSM8953_MASTER_BLSP_1,
26 MSM8953_MASTER_BLSP_2,
27 MSM8953_MASTER_USB3,
28 MSM8953_MASTER_CRYPTO_CORE0,
29 MSM8953_MASTER_SDCC_1,
30 MSM8953_MASTER_SDCC_2,
31 MSM8953_SNOC_PNOC_MAS,
32 MSM8953_PNOC_M_0,
33 MSM8953_PNOC_M_1,
34 MSM8953_PNOC_INT_1,
35 MSM8953_PNOC_INT_2,
36 MSM8953_PNOC_SLV_0,
37 MSM8953_PNOC_SLV_1,
38 MSM8953_PNOC_SLV_2,
39 MSM8953_PNOC_SLV_3,
40 MSM8953_PNOC_SLV_4,
41 MSM8953_PNOC_SLV_6,
42 MSM8953_PNOC_SLV_7,
43 MSM8953_PNOC_SLV_8,
44 MSM8953_PNOC_SLV_9,
45 MSM8953_SLAVE_SPDM_WRAPPER,
46 MSM8953_SLAVE_PDM,
47 MSM8953_SLAVE_TCSR,
48 MSM8953_SLAVE_SNOC_CFG,
49 MSM8953_SLAVE_TLMM,
50 MSM8953_SLAVE_MESSAGE_RAM,
51 MSM8953_SLAVE_BLSP_1,
52 MSM8953_SLAVE_BLSP_2,
53 MSM8953_SLAVE_PRNG,
54 MSM8953_SLAVE_CAMERA_CFG,
55 MSM8953_SLAVE_DISPLAY_CFG,
56 MSM8953_SLAVE_VENUS_CFG,
57 MSM8953_SLAVE_GRAPHICS_3D_CFG,
58 MSM8953_SLAVE_SDCC_1,
59 MSM8953_SLAVE_SDCC_2,
60 MSM8953_SLAVE_CRYPTO_0_CFG,
61 MSM8953_SLAVE_PMIC_ARB,
62 MSM8953_SLAVE_USB3,
63 MSM8953_SLAVE_IPA_CFG,
64 MSM8953_SLAVE_TCU,
65 MSM8953_PNOC_SNOC_SLV,
66 MSM8953_MASTER_QDSS_BAM,
67 MSM8953_BIMC_SNOC_MAS,
68 MSM8953_PNOC_SNOC_MAS,
69 MSM8953_MASTER_IPA,
70 MSM8953_MASTER_QDSS_ETR,
71 MSM8953_SNOC_QDSS_INT,
72 MSM8953_SNOC_INT_0,
73 MSM8953_SNOC_INT_1,
74 MSM8953_SNOC_INT_2,
75 MSM8953_SLAVE_APPSS,
76 MSM8953_SLAVE_WCSS,
77 MSM8953_SNOC_BIMC_1_SLV,
78 MSM8953_SLAVE_OCIMEM,
79 MSM8953_SNOC_PNOC_SLV,
80 MSM8953_SLAVE_QDSS_STM,
81 MSM8953_SLAVE_OCMEM_64,
82 MSM8953_SLAVE_LPASS,
83 MSM8953_MASTER_JPEG,
84 MSM8953_MASTER_MDP_PORT0,
85 MSM8953_MASTER_VIDEO_P0,
86 MSM8953_MASTER_VFE,
87 MSM8953_MASTER_VFE1,
88 MSM8953_MASTER_CPP,
89 MSM8953_SNOC_BIMC_0_SLV,
90 MSM8953_SNOC_BIMC_2_SLV,
91 MSM8953_SLAVE_CATS_128,
92};
93
94static const u16 mas_apps_proc_links[] = {
95 MSM8953_SLAVE_EBI_CH0,
96 MSM8953_BIMC_SNOC_SLV
97};
98
99static struct qcom_icc_node mas_apps_proc = {
100 .name = "mas_apps_proc",
101 .id = MSM8953_MASTER_AMPSS_M0,
102 .buswidth = 8,
103 .qos.ap_owned = true,
104 .qos.qos_mode = NOC_QOS_MODE_FIXED,
105 .qos.prio_level = 0,
106 .qos.areq_prio = 0,
107 .qos.qos_port = 0,
108 .num_links = ARRAY_SIZE(mas_apps_proc_links),
109 .links = mas_apps_proc_links,
110};
111
112static const u16 mas_oxili_links[] = {
113 MSM8953_SLAVE_EBI_CH0,
114 MSM8953_BIMC_SNOC_SLV
115};
116
117static struct qcom_icc_node mas_oxili = {
118 .name = "mas_oxili",
119 .id = MSM8953_MASTER_GRAPHICS_3D,
120 .buswidth = 8,
121 .qos.ap_owned = true,
122 .qos.qos_mode = NOC_QOS_MODE_FIXED,
123 .qos.prio_level = 0,
124 .qos.areq_prio = 0,
125 .qos.qos_port = 2,
126 .num_links = ARRAY_SIZE(mas_oxili_links),
127 .links = mas_oxili_links,
128};
129
130static const u16 mas_snoc_bimc_0_links[] = {
131 MSM8953_SLAVE_EBI_CH0,
132 MSM8953_BIMC_SNOC_SLV
133};
134
135static struct qcom_icc_node mas_snoc_bimc_0 = {
136 .name = "mas_snoc_bimc_0",
137 .id = MSM8953_SNOC_BIMC_0_MAS,
138 .buswidth = 8,
139 .qos.ap_owned = true,
140 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
141 .qos.prio_level = 0,
142 .qos.areq_prio = 0,
143 .qos.qos_port = 3,
144 .num_links = ARRAY_SIZE(mas_snoc_bimc_0_links),
145 .links = mas_snoc_bimc_0_links,
146};
147
148static const u16 mas_snoc_bimc_2_links[] = {
149 MSM8953_SLAVE_EBI_CH0,
150 MSM8953_BIMC_SNOC_SLV
151};
152
153static struct qcom_icc_node mas_snoc_bimc_2 = {
154 .name = "mas_snoc_bimc_2",
155 .id = MSM8953_SNOC_BIMC_2_MAS,
156 .buswidth = 8,
157 .qos.ap_owned = true,
158 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
159 .qos.prio_level = 0,
160 .qos.areq_prio = 0,
161 .qos.qos_port = 4,
162 .num_links = ARRAY_SIZE(mas_snoc_bimc_2_links),
163 .links = mas_snoc_bimc_2_links,
164};
165
166static const u16 mas_snoc_bimc_1_links[] = {
167 MSM8953_SLAVE_EBI_CH0
168};
169
170static struct qcom_icc_node mas_snoc_bimc_1 = {
171 .name = "mas_snoc_bimc_1",
172 .id = MSM8953_SNOC_BIMC_1_MAS,
173 .buswidth = 8,
174 .mas_rpm_id = 76,
175 .slv_rpm_id = -1,
176 .num_links = ARRAY_SIZE(mas_snoc_bimc_1_links),
177 .links = mas_snoc_bimc_1_links,
178};
179
180static const u16 mas_tcu_0_links[] = {
181 MSM8953_SLAVE_EBI_CH0,
182 MSM8953_BIMC_SNOC_SLV
183};
184
185static struct qcom_icc_node mas_tcu_0 = {
186 .name = "mas_tcu_0",
187 .id = MSM8953_MASTER_TCU_0,
188 .buswidth = 8,
189 .qos.ap_owned = true,
190 .qos.qos_mode = NOC_QOS_MODE_FIXED,
191 .qos.prio_level = 2,
192 .qos.areq_prio = 2,
193 .qos.qos_port = 6,
194 .num_links = ARRAY_SIZE(mas_tcu_0_links),
195 .links = mas_tcu_0_links,
196};
197
198static struct qcom_icc_node slv_ebi = {
199 .name = "slv_ebi",
200 .id = MSM8953_SLAVE_EBI_CH0,
201 .buswidth = 8,
202 .mas_rpm_id = -1,
203 .slv_rpm_id = 0,
204};
205
206static const u16 slv_bimc_snoc_links[] = {
207 MSM8953_BIMC_SNOC_MAS
208};
209
210static struct qcom_icc_node slv_bimc_snoc = {
211 .name = "slv_bimc_snoc",
212 .id = MSM8953_BIMC_SNOC_SLV,
213 .buswidth = 8,
214 .mas_rpm_id = -1,
215 .slv_rpm_id = 2,
216 .num_links = ARRAY_SIZE(slv_bimc_snoc_links),
217 .links = slv_bimc_snoc_links,
218};
219
220static const u16 mas_spdm_links[] = {
221 MSM8953_PNOC_M_0
222};
223
224static struct qcom_icc_node mas_spdm = {
225 .name = "mas_spdm",
226 .id = MSM8953_MASTER_SPDM,
227 .buswidth = 4,
228 .qos.ap_owned = true,
229 .qos.qos_mode = NOC_QOS_MODE_INVALID,
230 .qos.prio_level = 0,
231 .qos.areq_prio = 0,
232 .qos.qos_port = -1,
233 .num_links = ARRAY_SIZE(mas_spdm_links),
234 .links = mas_spdm_links,
235};
236
237static const u16 mas_blsp_1_links[] = {
238 MSM8953_PNOC_M_1
239};
240
241static struct qcom_icc_node mas_blsp_1 = {
242 .name = "mas_blsp_1",
243 .id = MSM8953_MASTER_BLSP_1,
244 .buswidth = 4,
245 .mas_rpm_id = 41,
246 .slv_rpm_id = -1,
247 .num_links = ARRAY_SIZE(mas_blsp_1_links),
248 .links = mas_blsp_1_links,
249};
250
251static const u16 mas_blsp_2_links[] = {
252 MSM8953_PNOC_M_1
253};
254
255static struct qcom_icc_node mas_blsp_2 = {
256 .name = "mas_blsp_2",
257 .id = MSM8953_MASTER_BLSP_2,
258 .buswidth = 4,
259 .mas_rpm_id = 39,
260 .slv_rpm_id = -1,
261 .num_links = ARRAY_SIZE(mas_blsp_2_links),
262 .links = mas_blsp_2_links,
263};
264
265static const u16 mas_usb3_links[] = {
266 MSM8953_PNOC_INT_1
267};
268
269static struct qcom_icc_node mas_usb3 = {
270 .name = "mas_usb3",
271 .id = MSM8953_MASTER_USB3,
272 .buswidth = 8,
273 .qos.ap_owned = true,
274 .qos.qos_mode = NOC_QOS_MODE_FIXED,
275 .qos.prio_level = 1,
276 .qos.areq_prio = 1,
277 .qos.qos_port = 11,
278 .num_links = ARRAY_SIZE(mas_usb3_links),
279 .links = mas_usb3_links,
280};
281
282static const u16 mas_crypto_links[] = {
283 MSM8953_PNOC_INT_1
284};
285
286static struct qcom_icc_node mas_crypto = {
287 .name = "mas_crypto",
288 .id = MSM8953_MASTER_CRYPTO_CORE0,
289 .buswidth = 8,
290 .qos.ap_owned = true,
291 .qos.qos_mode = NOC_QOS_MODE_FIXED,
292 .qos.prio_level = 1,
293 .qos.areq_prio = 1,
294 .qos.qos_port = 0,
295 .num_links = ARRAY_SIZE(mas_crypto_links),
296 .links = mas_crypto_links,
297};
298
299static const u16 mas_sdcc_1_links[] = {
300 MSM8953_PNOC_INT_1
301};
302
303static struct qcom_icc_node mas_sdcc_1 = {
304 .name = "mas_sdcc_1",
305 .id = MSM8953_MASTER_SDCC_1,
306 .buswidth = 8,
307 .mas_rpm_id = 33,
308 .slv_rpm_id = -1,
309 .num_links = ARRAY_SIZE(mas_sdcc_1_links),
310 .links = mas_sdcc_1_links,
311};
312
313static const u16 mas_sdcc_2_links[] = {
314 MSM8953_PNOC_INT_1
315};
316
317static struct qcom_icc_node mas_sdcc_2 = {
318 .name = "mas_sdcc_2",
319 .id = MSM8953_MASTER_SDCC_2,
320 .buswidth = 8,
321 .mas_rpm_id = 35,
322 .slv_rpm_id = -1,
323 .num_links = ARRAY_SIZE(mas_sdcc_2_links),
324 .links = mas_sdcc_2_links,
325};
326
327static const u16 mas_snoc_pcnoc_links[] = {
328 MSM8953_PNOC_INT_2
329};
330
331static struct qcom_icc_node mas_snoc_pcnoc = {
332 .name = "mas_snoc_pcnoc",
333 .id = MSM8953_SNOC_PNOC_MAS,
334 .buswidth = 8,
335 .mas_rpm_id = 77,
336 .slv_rpm_id = -1,
337 .num_links = ARRAY_SIZE(mas_snoc_pcnoc_links),
338 .links = mas_snoc_pcnoc_links,
339};
340
341static const u16 pcnoc_m_0_links[] = {
342 MSM8953_PNOC_INT_1
343};
344
345static struct qcom_icc_node pcnoc_m_0 = {
346 .name = "pcnoc_m_0",
347 .id = MSM8953_PNOC_M_0,
348 .buswidth = 4,
349 .qos.ap_owned = true,
350 .qos.qos_mode = NOC_QOS_MODE_FIXED,
351 .qos.prio_level = 1,
352 .qos.areq_prio = 1,
353 .qos.qos_port = 5,
354 .num_links = ARRAY_SIZE(pcnoc_m_0_links),
355 .links = pcnoc_m_0_links,
356};
357
358static const u16 pcnoc_m_1_links[] = {
359 MSM8953_PNOC_INT_1
360};
361
362static struct qcom_icc_node pcnoc_m_1 = {
363 .name = "pcnoc_m_1",
364 .id = MSM8953_PNOC_M_1,
365 .buswidth = 4,
366 .mas_rpm_id = 88,
367 .slv_rpm_id = 117,
368 .num_links = ARRAY_SIZE(pcnoc_m_1_links),
369 .links = pcnoc_m_1_links,
370};
371
372static const u16 pcnoc_int_1_links[] = {
373 MSM8953_PNOC_INT_2,
374 MSM8953_PNOC_SNOC_SLV
375};
376
377static struct qcom_icc_node pcnoc_int_1 = {
378 .name = "pcnoc_int_1",
379 .id = MSM8953_PNOC_INT_1,
380 .buswidth = 8,
381 .mas_rpm_id = 86,
382 .slv_rpm_id = 115,
383 .num_links = ARRAY_SIZE(pcnoc_int_1_links),
384 .links = pcnoc_int_1_links,
385};
386
387static const u16 pcnoc_int_2_links[] = {
388 MSM8953_PNOC_SLV_1,
389 MSM8953_PNOC_SLV_2,
390 MSM8953_PNOC_SLV_0,
391 MSM8953_PNOC_SLV_4,
392 MSM8953_PNOC_SLV_6,
393 MSM8953_PNOC_SLV_7,
394 MSM8953_PNOC_SLV_8,
395 MSM8953_PNOC_SLV_9,
396 MSM8953_SLAVE_TCU,
397 MSM8953_SLAVE_GRAPHICS_3D_CFG,
398 MSM8953_PNOC_SLV_3
399};
400
401static struct qcom_icc_node pcnoc_int_2 = {
402 .name = "pcnoc_int_2",
403 .id = MSM8953_PNOC_INT_2,
404 .buswidth = 8,
405 .mas_rpm_id = 124,
406 .slv_rpm_id = 184,
407 .num_links = ARRAY_SIZE(pcnoc_int_2_links),
408 .links = pcnoc_int_2_links,
409};
410
411static const u16 pcnoc_s_0_links[] = {
412 MSM8953_SLAVE_PDM,
413 MSM8953_SLAVE_SPDM_WRAPPER
414};
415
416static struct qcom_icc_node pcnoc_s_0 = {
417 .name = "pcnoc_s_0",
418 .id = MSM8953_PNOC_SLV_0,
419 .buswidth = 4,
420 .mas_rpm_id = 89,
421 .slv_rpm_id = 118,
422 .num_links = ARRAY_SIZE(pcnoc_s_0_links),
423 .links = pcnoc_s_0_links,
424};
425
426static const u16 pcnoc_s_1_links[] = {
427 MSM8953_SLAVE_TCSR
428};
429
430static struct qcom_icc_node pcnoc_s_1 = {
431 .name = "pcnoc_s_1",
432 .id = MSM8953_PNOC_SLV_1,
433 .buswidth = 4,
434 .mas_rpm_id = 90,
435 .slv_rpm_id = 119,
436 .num_links = ARRAY_SIZE(pcnoc_s_1_links),
437 .links = pcnoc_s_1_links,
438};
439
440static const u16 pcnoc_s_2_links[] = {
441 MSM8953_SLAVE_SNOC_CFG
442};
443
444static struct qcom_icc_node pcnoc_s_2 = {
445 .name = "pcnoc_s_2",
446 .id = MSM8953_PNOC_SLV_2,
447 .buswidth = 4,
448 .mas_rpm_id = 91,
449 .slv_rpm_id = 120,
450 .num_links = ARRAY_SIZE(pcnoc_s_2_links),
451 .links = pcnoc_s_2_links,
452};
453
454static const u16 pcnoc_s_3_links[] = {
455 MSM8953_SLAVE_TLMM,
456 MSM8953_SLAVE_PRNG,
457 MSM8953_SLAVE_BLSP_1,
458 MSM8953_SLAVE_BLSP_2,
459 MSM8953_SLAVE_MESSAGE_RAM
460};
461
462static struct qcom_icc_node pcnoc_s_3 = {
463 .name = "pcnoc_s_3",
464 .id = MSM8953_PNOC_SLV_3,
465 .buswidth = 4,
466 .mas_rpm_id = 92,
467 .slv_rpm_id = 121,
468 .num_links = ARRAY_SIZE(pcnoc_s_3_links),
469 .links = pcnoc_s_3_links,
470};
471
472static const u16 pcnoc_s_4_links[] = {
473 MSM8953_SLAVE_CAMERA_CFG,
474 MSM8953_SLAVE_DISPLAY_CFG,
475 MSM8953_SLAVE_VENUS_CFG
476};
477
478static struct qcom_icc_node pcnoc_s_4 = {
479 .name = "pcnoc_s_4",
480 .id = MSM8953_PNOC_SLV_4,
481 .buswidth = 4,
482 .qos.ap_owned = true,
483 .qos.qos_mode = NOC_QOS_MODE_INVALID,
484 .qos.prio_level = 0,
485 .qos.areq_prio = 0,
486 .qos.qos_port = -1,
487 .num_links = ARRAY_SIZE(pcnoc_s_4_links),
488 .links = pcnoc_s_4_links,
489};
490
491static const u16 pcnoc_s_6_links[] = {
492 MSM8953_SLAVE_CRYPTO_0_CFG,
493 MSM8953_SLAVE_SDCC_2,
494 MSM8953_SLAVE_SDCC_1
495};
496
497static struct qcom_icc_node pcnoc_s_6 = {
498 .name = "pcnoc_s_6",
499 .id = MSM8953_PNOC_SLV_6,
500 .buswidth = 4,
501 .mas_rpm_id = 94,
502 .slv_rpm_id = 123,
503 .num_links = ARRAY_SIZE(pcnoc_s_6_links),
504 .links = pcnoc_s_6_links,
505};
506
507static const u16 pcnoc_s_7_links[] = {
508 MSM8953_SLAVE_PMIC_ARB
509};
510
511static struct qcom_icc_node pcnoc_s_7 = {
512 .name = "pcnoc_s_7",
513 .id = MSM8953_PNOC_SLV_7,
514 .buswidth = 4,
515 .mas_rpm_id = 95,
516 .slv_rpm_id = 124,
517 .num_links = ARRAY_SIZE(pcnoc_s_7_links),
518 .links = pcnoc_s_7_links,
519};
520
521static const u16 pcnoc_s_8_links[] = {
522 MSM8953_SLAVE_USB3
523};
524
525static struct qcom_icc_node pcnoc_s_8 = {
526 .name = "pcnoc_s_8",
527 .id = MSM8953_PNOC_SLV_8,
528 .buswidth = 4,
529 .qos.ap_owned = true,
530 .qos.qos_mode = NOC_QOS_MODE_INVALID,
531 .qos.prio_level = 0,
532 .qos.areq_prio = 0,
533 .qos.qos_port = -1,
534 .num_links = ARRAY_SIZE(pcnoc_s_8_links),
535 .links = pcnoc_s_8_links,
536};
537
538static const u16 pcnoc_s_9_links[] = {
539 MSM8953_SLAVE_IPA_CFG
540};
541
542static struct qcom_icc_node pcnoc_s_9 = {
543 .name = "pcnoc_s_9",
544 .id = MSM8953_PNOC_SLV_9,
545 .buswidth = 4,
546 .qos.ap_owned = true,
547 .qos.qos_mode = NOC_QOS_MODE_INVALID,
548 .qos.prio_level = 0,
549 .qos.areq_prio = 0,
550 .qos.qos_port = -1,
551 .num_links = ARRAY_SIZE(pcnoc_s_9_links),
552 .links = pcnoc_s_9_links,
553};
554
555static struct qcom_icc_node slv_spdm = {
556 .name = "slv_spdm",
557 .id = MSM8953_SLAVE_SPDM_WRAPPER,
558 .buswidth = 4,
559 .qos.ap_owned = true,
560 .qos.qos_mode = NOC_QOS_MODE_INVALID,
561 .qos.prio_level = 0,
562 .qos.areq_prio = 0,
563 .qos.qos_port = -1,
564};
565
566static struct qcom_icc_node slv_pdm = {
567 .name = "slv_pdm",
568 .id = MSM8953_SLAVE_PDM,
569 .buswidth = 4,
570 .mas_rpm_id = -1,
571 .slv_rpm_id = 41,
572};
573
574static struct qcom_icc_node slv_tcsr = {
575 .name = "slv_tcsr",
576 .id = MSM8953_SLAVE_TCSR,
577 .buswidth = 4,
578 .mas_rpm_id = -1,
579 .slv_rpm_id = 50,
580};
581
582static struct qcom_icc_node slv_snoc_cfg = {
583 .name = "slv_snoc_cfg",
584 .id = MSM8953_SLAVE_SNOC_CFG,
585 .buswidth = 4,
586 .mas_rpm_id = -1,
587 .slv_rpm_id = 70,
588};
589
590static struct qcom_icc_node slv_tlmm = {
591 .name = "slv_tlmm",
592 .id = MSM8953_SLAVE_TLMM,
593 .buswidth = 4,
594 .mas_rpm_id = -1,
595 .slv_rpm_id = 51,
596};
597
598static struct qcom_icc_node slv_message_ram = {
599 .name = "slv_message_ram",
600 .id = MSM8953_SLAVE_MESSAGE_RAM,
601 .buswidth = 4,
602 .mas_rpm_id = -1,
603 .slv_rpm_id = 55,
604};
605
606static struct qcom_icc_node slv_blsp_1 = {
607 .name = "slv_blsp_1",
608 .id = MSM8953_SLAVE_BLSP_1,
609 .buswidth = 4,
610 .mas_rpm_id = -1,
611 .slv_rpm_id = 39,
612};
613
614static struct qcom_icc_node slv_blsp_2 = {
615 .name = "slv_blsp_2",
616 .id = MSM8953_SLAVE_BLSP_2,
617 .buswidth = 4,
618 .mas_rpm_id = -1,
619 .slv_rpm_id = 37,
620};
621
622static struct qcom_icc_node slv_prng = {
623 .name = "slv_prng",
624 .id = MSM8953_SLAVE_PRNG,
625 .buswidth = 4,
626 .mas_rpm_id = -1,
627 .slv_rpm_id = 44,
628};
629
630static struct qcom_icc_node slv_camera_ss_cfg = {
631 .name = "slv_camera_ss_cfg",
632 .id = MSM8953_SLAVE_CAMERA_CFG,
633 .buswidth = 4,
634 .qos.ap_owned = true,
635 .qos.qos_mode = NOC_QOS_MODE_INVALID,
636 .qos.prio_level = 0,
637 .qos.areq_prio = 0,
638 .qos.qos_port = -1,
639};
640
641static struct qcom_icc_node slv_disp_ss_cfg = {
642 .name = "slv_disp_ss_cfg",
643 .id = MSM8953_SLAVE_DISPLAY_CFG,
644 .buswidth = 4,
645 .qos.ap_owned = true,
646 .qos.qos_mode = NOC_QOS_MODE_INVALID,
647 .qos.prio_level = 0,
648 .qos.areq_prio = 0,
649 .qos.qos_port = -1,
650};
651
652static struct qcom_icc_node slv_venus_cfg = {
653 .name = "slv_venus_cfg",
654 .id = MSM8953_SLAVE_VENUS_CFG,
655 .buswidth = 4,
656 .qos.ap_owned = true,
657 .qos.qos_mode = NOC_QOS_MODE_INVALID,
658 .qos.prio_level = 0,
659 .qos.areq_prio = 0,
660 .qos.qos_port = -1,
661};
662
663static struct qcom_icc_node slv_gpu_cfg = {
664 .name = "slv_gpu_cfg",
665 .id = MSM8953_SLAVE_GRAPHICS_3D_CFG,
666 .buswidth = 8,
667 .qos.ap_owned = true,
668 .qos.qos_mode = NOC_QOS_MODE_INVALID,
669 .qos.prio_level = 0,
670 .qos.areq_prio = 0,
671 .qos.qos_port = -1,
672};
673
674static struct qcom_icc_node slv_sdcc_1 = {
675 .name = "slv_sdcc_1",
676 .id = MSM8953_SLAVE_SDCC_1,
677 .buswidth = 4,
678 .mas_rpm_id = -1,
679 .slv_rpm_id = 31,
680};
681
682static struct qcom_icc_node slv_sdcc_2 = {
683 .name = "slv_sdcc_2",
684 .id = MSM8953_SLAVE_SDCC_2,
685 .buswidth = 4,
686 .mas_rpm_id = -1,
687 .slv_rpm_id = 33,
688};
689
690static struct qcom_icc_node slv_crypto_0_cfg = {
691 .name = "slv_crypto_0_cfg",
692 .id = MSM8953_SLAVE_CRYPTO_0_CFG,
693 .buswidth = 4,
694 .qos.ap_owned = true,
695 .qos.qos_mode = NOC_QOS_MODE_INVALID,
696 .qos.prio_level = 0,
697 .qos.areq_prio = 0,
698 .qos.qos_port = -1,
699};
700
701static struct qcom_icc_node slv_pmic_arb = {
702 .name = "slv_pmic_arb",
703 .id = MSM8953_SLAVE_PMIC_ARB,
704 .buswidth = 4,
705 .mas_rpm_id = -1,
706 .slv_rpm_id = 59,
707};
708
709static struct qcom_icc_node slv_usb3 = {
710 .name = "slv_usb3",
711 .id = MSM8953_SLAVE_USB3,
712 .buswidth = 4,
713 .qos.ap_owned = true,
714 .qos.qos_mode = NOC_QOS_MODE_INVALID,
715 .qos.prio_level = 0,
716 .qos.areq_prio = 0,
717 .qos.qos_port = -1,
718};
719
720static struct qcom_icc_node slv_ipa_cfg = {
721 .name = "slv_ipa_cfg",
722 .id = MSM8953_SLAVE_IPA_CFG,
723 .buswidth = 4,
724 .qos.ap_owned = true,
725 .qos.qos_mode = NOC_QOS_MODE_INVALID,
726 .qos.prio_level = 0,
727 .qos.areq_prio = 0,
728 .qos.qos_port = -1,
729};
730
731static struct qcom_icc_node slv_tcu = {
732 .name = "slv_tcu",
733 .id = MSM8953_SLAVE_TCU,
734 .buswidth = 8,
735 .qos.ap_owned = true,
736 .qos.qos_mode = NOC_QOS_MODE_INVALID,
737 .qos.prio_level = 0,
738 .qos.areq_prio = 0,
739 .qos.qos_port = -1,
740};
741
742static const u16 slv_pcnoc_snoc_links[] = {
743 MSM8953_PNOC_SNOC_MAS
744};
745
746static struct qcom_icc_node slv_pcnoc_snoc = {
747 .name = "slv_pcnoc_snoc",
748 .id = MSM8953_PNOC_SNOC_SLV,
749 .buswidth = 8,
750 .mas_rpm_id = -1,
751 .slv_rpm_id = 45,
752 .num_links = ARRAY_SIZE(slv_pcnoc_snoc_links),
753 .links = slv_pcnoc_snoc_links,
754};
755
756static const u16 mas_qdss_bam_links[] = {
757 MSM8953_SNOC_QDSS_INT
758};
759
760static struct qcom_icc_node mas_qdss_bam = {
761 .name = "mas_qdss_bam",
762 .id = MSM8953_MASTER_QDSS_BAM,
763 .buswidth = 4,
764 .qos.ap_owned = true,
765 .qos.qos_mode = NOC_QOS_MODE_FIXED,
766 .qos.prio_level = 1,
767 .qos.areq_prio = 1,
768 .qos.qos_port = 11,
769 .num_links = ARRAY_SIZE(mas_qdss_bam_links),
770 .links = mas_qdss_bam_links,
771};
772
773static const u16 mas_bimc_snoc_links[] = {
774 MSM8953_SNOC_INT_0,
775 MSM8953_SNOC_INT_1,
776 MSM8953_SNOC_INT_2
777};
778
779static struct qcom_icc_node mas_bimc_snoc = {
780 .name = "mas_bimc_snoc",
781 .id = MSM8953_BIMC_SNOC_MAS,
782 .buswidth = 8,
783 .mas_rpm_id = 21,
784 .slv_rpm_id = -1,
785 .num_links = ARRAY_SIZE(mas_bimc_snoc_links),
786 .links = mas_bimc_snoc_links,
787};
788
789static const u16 mas_pcnoc_snoc_links[] = {
790 MSM8953_SNOC_INT_0,
791 MSM8953_SNOC_INT_1,
792 MSM8953_SNOC_BIMC_1_SLV
793};
794
795static struct qcom_icc_node mas_pcnoc_snoc = {
796 .name = "mas_pcnoc_snoc",
797 .id = MSM8953_PNOC_SNOC_MAS,
798 .buswidth = 8,
799 .mas_rpm_id = 29,
800 .slv_rpm_id = -1,
801 .num_links = ARRAY_SIZE(mas_pcnoc_snoc_links),
802 .links = mas_pcnoc_snoc_links,
803};
804
805static const u16 mas_ipa_links[] = {
806 MSM8953_SNOC_INT_0,
807 MSM8953_SNOC_INT_1,
808 MSM8953_SNOC_BIMC_1_SLV
809};
810
811static struct qcom_icc_node mas_ipa = {
812 .name = "mas_ipa",
813 .id = MSM8953_MASTER_IPA,
814 .buswidth = 8,
815 .qos.ap_owned = true,
816 .qos.qos_mode = NOC_QOS_MODE_FIXED,
817 .qos.prio_level = 0,
818 .qos.areq_prio = 0,
819 .qos.qos_port = 14,
820 .num_links = ARRAY_SIZE(mas_ipa_links),
821 .links = mas_ipa_links,
822};
823
824static const u16 mas_qdss_etr_links[] = {
825 MSM8953_SNOC_QDSS_INT
826};
827
828static struct qcom_icc_node mas_qdss_etr = {
829 .name = "mas_qdss_etr",
830 .id = MSM8953_MASTER_QDSS_ETR,
831 .buswidth = 8,
832 .qos.ap_owned = true,
833 .qos.qos_mode = NOC_QOS_MODE_FIXED,
834 .qos.prio_level = 1,
835 .qos.areq_prio = 1,
836 .qos.qos_port = 10,
837 .num_links = ARRAY_SIZE(mas_qdss_etr_links),
838 .links = mas_qdss_etr_links,
839};
840
841static const u16 qdss_int_links[] = {
842 MSM8953_SNOC_INT_1,
843 MSM8953_SNOC_BIMC_1_SLV
844};
845
846static struct qcom_icc_node qdss_int = {
847 .name = "qdss_int",
848 .id = MSM8953_SNOC_QDSS_INT,
849 .buswidth = 8,
850 .qos.ap_owned = true,
851 .qos.qos_mode = NOC_QOS_MODE_INVALID,
852 .qos.prio_level = 0,
853 .qos.areq_prio = 0,
854 .qos.qos_port = -1,
855 .num_links = ARRAY_SIZE(qdss_int_links),
856 .links = qdss_int_links,
857};
858
859static const u16 snoc_int_0_links[] = {
860 MSM8953_SLAVE_LPASS,
861 MSM8953_SLAVE_WCSS,
862 MSM8953_SLAVE_APPSS
863};
864
865static struct qcom_icc_node snoc_int_0 = {
866 .name = "snoc_int_0",
867 .id = MSM8953_SNOC_INT_0,
868 .buswidth = 8,
869 .qos.ap_owned = true,
870 .qos.qos_mode = NOC_QOS_MODE_INVALID,
871 .qos.prio_level = 0,
872 .qos.areq_prio = 0,
873 .qos.qos_port = -1,
874 .num_links = ARRAY_SIZE(snoc_int_0_links),
875 .links = snoc_int_0_links,
876};
877
878static const u16 snoc_int_1_links[] = {
879 MSM8953_SLAVE_QDSS_STM,
880 MSM8953_SLAVE_OCIMEM,
881 MSM8953_SNOC_PNOC_SLV
882};
883
884static struct qcom_icc_node snoc_int_1 = {
885 .name = "snoc_int_1",
886 .id = MSM8953_SNOC_INT_1,
887 .buswidth = 8,
888 .mas_rpm_id = 100,
889 .slv_rpm_id = 131,
890 .num_links = ARRAY_SIZE(snoc_int_1_links),
891 .links = snoc_int_1_links,
892};
893
894static const u16 snoc_int_2_links[] = {
895 MSM8953_SLAVE_CATS_128,
896 MSM8953_SLAVE_OCMEM_64
897};
898
899static struct qcom_icc_node snoc_int_2 = {
900 .name = "snoc_int_2",
901 .id = MSM8953_SNOC_INT_2,
902 .buswidth = 8,
903 .qos.ap_owned = true,
904 .qos.qos_mode = NOC_QOS_MODE_INVALID,
905 .qos.prio_level = 0,
906 .qos.areq_prio = 0,
907 .qos.qos_port = -1,
908 .num_links = ARRAY_SIZE(snoc_int_2_links),
909 .links = snoc_int_2_links,
910};
911
912static struct qcom_icc_node slv_kpss_ahb = {
913 .name = "slv_kpss_ahb",
914 .id = MSM8953_SLAVE_APPSS,
915 .buswidth = 4,
916 .qos.ap_owned = true,
917 .qos.qos_mode = NOC_QOS_MODE_INVALID,
918 .qos.prio_level = 0,
919 .qos.areq_prio = 0,
920 .qos.qos_port = -1,
921};
922
923static struct qcom_icc_node slv_wcss = {
924 .name = "slv_wcss",
925 .id = MSM8953_SLAVE_WCSS,
926 .buswidth = 4,
927 .qos.ap_owned = true,
928 .qos.qos_mode = NOC_QOS_MODE_INVALID,
929 .qos.prio_level = 0,
930 .qos.areq_prio = 0,
931 .qos.qos_port = -1,
932};
933
934static const u16 slv_snoc_bimc_1_links[] = {
935 MSM8953_SNOC_BIMC_1_MAS
936};
937
938static struct qcom_icc_node slv_snoc_bimc_1 = {
939 .name = "slv_snoc_bimc_1",
940 .id = MSM8953_SNOC_BIMC_1_SLV,
941 .buswidth = 8,
942 .mas_rpm_id = -1,
943 .slv_rpm_id = 104,
944 .num_links = ARRAY_SIZE(slv_snoc_bimc_1_links),
945 .links = slv_snoc_bimc_1_links,
946};
947
948static struct qcom_icc_node slv_imem = {
949 .name = "slv_imem",
950 .id = MSM8953_SLAVE_OCIMEM,
951 .buswidth = 8,
952 .mas_rpm_id = -1,
953 .slv_rpm_id = 26,
954};
955
956static const u16 slv_snoc_pcnoc_links[] = {
957 MSM8953_SNOC_PNOC_MAS
958};
959
960static struct qcom_icc_node slv_snoc_pcnoc = {
961 .name = "slv_snoc_pcnoc",
962 .id = MSM8953_SNOC_PNOC_SLV,
963 .buswidth = 8,
964 .mas_rpm_id = -1,
965 .slv_rpm_id = 28,
966 .num_links = ARRAY_SIZE(slv_snoc_pcnoc_links),
967 .links = slv_snoc_pcnoc_links,
968};
969
970static struct qcom_icc_node slv_qdss_stm = {
971 .name = "slv_qdss_stm",
972 .id = MSM8953_SLAVE_QDSS_STM,
973 .buswidth = 4,
974 .mas_rpm_id = -1,
975 .slv_rpm_id = 30,
976};
977
978static struct qcom_icc_node slv_cats_1 = {
979 .name = "slv_cats_1",
980 .id = MSM8953_SLAVE_OCMEM_64,
981 .buswidth = 8,
982 .qos.ap_owned = true,
983 .qos.qos_mode = NOC_QOS_MODE_INVALID,
984 .qos.prio_level = 0,
985 .qos.areq_prio = 0,
986 .qos.qos_port = -1,
987};
988
989static struct qcom_icc_node slv_lpass = {
990 .name = "slv_lpass",
991 .id = MSM8953_SLAVE_LPASS,
992 .buswidth = 4,
993 .qos.ap_owned = true,
994 .qos.qos_mode = NOC_QOS_MODE_INVALID,
995 .qos.prio_level = 0,
996 .qos.areq_prio = 0,
997 .qos.qos_port = -1,
998};
999
1000static const u16 mas_jpeg_links[] = {
1001 MSM8953_SNOC_BIMC_2_SLV
1002};
1003
1004static struct qcom_icc_node mas_jpeg = {
1005 .name = "mas_jpeg",
1006 .id = MSM8953_MASTER_JPEG,
1007 .buswidth = 16,
1008 .qos.ap_owned = true,
1009 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
1010 .qos.prio_level = 0,
1011 .qos.areq_prio = 0,
1012 .qos.qos_port = 6,
1013 .num_links = ARRAY_SIZE(mas_jpeg_links),
1014 .links = mas_jpeg_links,
1015};
1016
1017static const u16 mas_mdp_links[] = {
1018 MSM8953_SNOC_BIMC_0_SLV
1019};
1020
1021static struct qcom_icc_node mas_mdp = {
1022 .name = "mas_mdp",
1023 .id = MSM8953_MASTER_MDP_PORT0,
1024 .buswidth = 16,
1025 .qos.ap_owned = true,
1026 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
1027 .qos.prio_level = 0,
1028 .qos.areq_prio = 0,
1029 .qos.qos_port = 7,
1030 .num_links = ARRAY_SIZE(mas_mdp_links),
1031 .links = mas_mdp_links,
1032};
1033
1034static const u16 mas_venus_links[] = {
1035 MSM8953_SNOC_BIMC_2_SLV
1036};
1037
1038static struct qcom_icc_node mas_venus = {
1039 .name = "mas_venus",
1040 .id = MSM8953_MASTER_VIDEO_P0,
1041 .buswidth = 16,
1042 .qos.ap_owned = true,
1043 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
1044 .qos.prio_level = 0,
1045 .qos.areq_prio = 0,
1046 .qos.qos_port = 8,
1047 .num_links = ARRAY_SIZE(mas_venus_links),
1048 .links = mas_venus_links,
1049};
1050
1051static const u16 mas_vfe0_links[] = {
1052 MSM8953_SNOC_BIMC_0_SLV
1053};
1054
1055static struct qcom_icc_node mas_vfe0 = {
1056 .name = "mas_vfe0",
1057 .id = MSM8953_MASTER_VFE,
1058 .buswidth = 16,
1059 .qos.ap_owned = true,
1060 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
1061 .qos.prio_level = 0,
1062 .qos.areq_prio = 0,
1063 .qos.qos_port = 9,
1064 .num_links = ARRAY_SIZE(mas_vfe0_links),
1065 .links = mas_vfe0_links,
1066};
1067
1068static const u16 mas_vfe1_links[] = {
1069 MSM8953_SNOC_BIMC_0_SLV
1070};
1071
1072static struct qcom_icc_node mas_vfe1 = {
1073 .name = "mas_vfe1",
1074 .id = MSM8953_MASTER_VFE1,
1075 .buswidth = 16,
1076 .qos.ap_owned = true,
1077 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
1078 .qos.prio_level = 0,
1079 .qos.areq_prio = 0,
1080 .qos.qos_port = 13,
1081 .num_links = ARRAY_SIZE(mas_vfe1_links),
1082 .links = mas_vfe1_links,
1083};
1084
1085static const u16 mas_cpp_links[] = {
1086 MSM8953_SNOC_BIMC_2_SLV
1087};
1088
1089static struct qcom_icc_node mas_cpp = {
1090 .name = "mas_cpp",
1091 .id = MSM8953_MASTER_CPP,
1092 .buswidth = 16,
1093 .qos.ap_owned = true,
1094 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
1095 .qos.prio_level = 0,
1096 .qos.areq_prio = 0,
1097 .qos.qos_port = 12,
1098 .num_links = ARRAY_SIZE(mas_cpp_links),
1099 .links = mas_cpp_links,
1100};
1101
1102static const u16 slv_snoc_bimc_0_links[] = {
1103 MSM8953_SNOC_BIMC_0_MAS
1104};
1105
1106static struct qcom_icc_node slv_snoc_bimc_0 = {
1107 .name = "slv_snoc_bimc_0",
1108 .id = MSM8953_SNOC_BIMC_0_SLV,
1109 .buswidth = 16,
1110 .qos.ap_owned = true,
1111 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1112 .qos.prio_level = 0,
1113 .qos.areq_prio = 0,
1114 .qos.qos_port = -1,
1115 .num_links = ARRAY_SIZE(slv_snoc_bimc_0_links),
1116 .links = slv_snoc_bimc_0_links,
1117};
1118
1119static const u16 slv_snoc_bimc_2_links[] = {
1120 MSM8953_SNOC_BIMC_2_MAS
1121};
1122
1123static struct qcom_icc_node slv_snoc_bimc_2 = {
1124 .name = "slv_snoc_bimc_2",
1125 .id = MSM8953_SNOC_BIMC_2_SLV,
1126 .buswidth = 16,
1127 .qos.ap_owned = true,
1128 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1129 .qos.prio_level = 0,
1130 .qos.areq_prio = 0,
1131 .qos.qos_port = -1,
1132 .num_links = ARRAY_SIZE(slv_snoc_bimc_2_links),
1133 .links = slv_snoc_bimc_2_links,
1134};
1135
1136static struct qcom_icc_node slv_cats_0 = {
1137 .name = "slv_cats_0",
1138 .id = MSM8953_SLAVE_CATS_128,
1139 .buswidth = 16,
1140 .qos.ap_owned = true,
1141 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1142 .qos.prio_level = 0,
1143 .qos.areq_prio = 0,
1144 .qos.qos_port = -1,
1145};
1146
1147static struct qcom_icc_node * const msm8953_bimc_nodes[] = {
1148 [MAS_APPS_PROC] = &mas_apps_proc,
1149 [MAS_OXILI] = &mas_oxili,
1150 [MAS_SNOC_BIMC_0] = &mas_snoc_bimc_0,
1151 [MAS_SNOC_BIMC_2] = &mas_snoc_bimc_2,
1152 [MAS_SNOC_BIMC_1] = &mas_snoc_bimc_1,
1153 [MAS_TCU_0] = &mas_tcu_0,
1154 [SLV_EBI] = &slv_ebi,
1155 [SLV_BIMC_SNOC] = &slv_bimc_snoc,
1156};
1157
1158static const struct regmap_config msm8953_bimc_regmap_config = {
1159 .fast_io = true,
1160 .max_register = 0x5a000,
1161 .reg_bits = 32,
1162 .reg_stride = 4,
1163 .val_bits = 32,
1164};
1165
1166static const struct qcom_icc_desc msm8953_bimc = {
1167 .type = QCOM_ICC_BIMC,
1168 .bus_clk_desc = &bimc_clk,
1169 .nodes = msm8953_bimc_nodes,
1170 .num_nodes = ARRAY_SIZE(msm8953_bimc_nodes),
1171 .qos_offset = 0x8000,
1172 .regmap_cfg = &msm8953_bimc_regmap_config
1173};
1174
1175static struct qcom_icc_node * const msm8953_pcnoc_nodes[] = {
1176 [MAS_SPDM] = &mas_spdm,
1177 [MAS_BLSP_1] = &mas_blsp_1,
1178 [MAS_BLSP_2] = &mas_blsp_2,
1179 [MAS_USB3] = &mas_usb3,
1180 [MAS_CRYPTO] = &mas_crypto,
1181 [MAS_SDCC_1] = &mas_sdcc_1,
1182 [MAS_SDCC_2] = &mas_sdcc_2,
1183 [MAS_SNOC_PCNOC] = &mas_snoc_pcnoc,
1184 [PCNOC_M_0] = &pcnoc_m_0,
1185 [PCNOC_M_1] = &pcnoc_m_1,
1186 [PCNOC_INT_1] = &pcnoc_int_1,
1187 [PCNOC_INT_2] = &pcnoc_int_2,
1188 [PCNOC_S_0] = &pcnoc_s_0,
1189 [PCNOC_S_1] = &pcnoc_s_1,
1190 [PCNOC_S_2] = &pcnoc_s_2,
1191 [PCNOC_S_3] = &pcnoc_s_3,
1192 [PCNOC_S_4] = &pcnoc_s_4,
1193 [PCNOC_S_6] = &pcnoc_s_6,
1194 [PCNOC_S_7] = &pcnoc_s_7,
1195 [PCNOC_S_8] = &pcnoc_s_8,
1196 [PCNOC_S_9] = &pcnoc_s_9,
1197 [SLV_SPDM] = &slv_spdm,
1198 [SLV_PDM] = &slv_pdm,
1199 [SLV_TCSR] = &slv_tcsr,
1200 [SLV_SNOC_CFG] = &slv_snoc_cfg,
1201 [SLV_TLMM] = &slv_tlmm,
1202 [SLV_MESSAGE_RAM] = &slv_message_ram,
1203 [SLV_BLSP_1] = &slv_blsp_1,
1204 [SLV_BLSP_2] = &slv_blsp_2,
1205 [SLV_PRNG] = &slv_prng,
1206 [SLV_CAMERA_SS_CFG] = &slv_camera_ss_cfg,
1207 [SLV_DISP_SS_CFG] = &slv_disp_ss_cfg,
1208 [SLV_VENUS_CFG] = &slv_venus_cfg,
1209 [SLV_GPU_CFG] = &slv_gpu_cfg,
1210 [SLV_SDCC_1] = &slv_sdcc_1,
1211 [SLV_SDCC_2] = &slv_sdcc_2,
1212 [SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1213 [SLV_PMIC_ARB] = &slv_pmic_arb,
1214 [SLV_USB3] = &slv_usb3,
1215 [SLV_IPA_CFG] = &slv_ipa_cfg,
1216 [SLV_TCU] = &slv_tcu,
1217 [SLV_PCNOC_SNOC] = &slv_pcnoc_snoc,
1218};
1219
1220static const char * const msm8953_pcnoc_intf_clocks[] = {
1221 "pcnoc_usb3_axi"
1222};
1223
1224static const struct regmap_config msm8953_pcnoc_regmap_config = {
1225 .fast_io = true,
1226 .max_register = 0x12080,
1227 .reg_bits = 32,
1228 .reg_stride = 4,
1229 .val_bits = 32,
1230};
1231
1232static const struct qcom_icc_desc msm8953_pcnoc = {
1233 .type = QCOM_ICC_NOC,
1234 .bus_clk_desc = &bus_0_clk,
1235 .intf_clocks = msm8953_pcnoc_intf_clocks,
1236 .num_intf_clocks = ARRAY_SIZE(msm8953_pcnoc_intf_clocks),
1237 .nodes = msm8953_pcnoc_nodes,
1238 .num_nodes = ARRAY_SIZE(msm8953_pcnoc_nodes),
1239 .qos_offset = 0x7000,
1240 .regmap_cfg = &msm8953_pcnoc_regmap_config,
1241};
1242
1243static struct qcom_icc_node * const msm8953_snoc_nodes[] = {
1244 [MAS_QDSS_BAM] = &mas_qdss_bam,
1245 [MAS_BIMC_SNOC] = &mas_bimc_snoc,
1246 [MAS_PCNOC_SNOC] = &mas_pcnoc_snoc,
1247 [MAS_IPA] = &mas_ipa,
1248 [MAS_QDSS_ETR] = &mas_qdss_etr,
1249 [QDSS_INT] = &qdss_int,
1250 [SNOC_INT_0] = &snoc_int_0,
1251 [SNOC_INT_1] = &snoc_int_1,
1252 [SNOC_INT_2] = &snoc_int_2,
1253 [SLV_KPSS_AHB] = &slv_kpss_ahb,
1254 [SLV_WCSS] = &slv_wcss,
1255 [SLV_SNOC_BIMC_1] = &slv_snoc_bimc_1,
1256 [SLV_IMEM] = &slv_imem,
1257 [SLV_SNOC_PCNOC] = &slv_snoc_pcnoc,
1258 [SLV_QDSS_STM] = &slv_qdss_stm,
1259 [SLV_CATS_1] = &slv_cats_1,
1260 [SLV_LPASS] = &slv_lpass,
1261};
1262
1263static const struct regmap_config msm8953_snoc_regmap_config = {
1264 .fast_io = true,
1265 .max_register = 0x16080,
1266 .reg_bits = 32,
1267 .reg_stride = 4,
1268 .val_bits = 32,
1269};
1270
1271static const struct qcom_icc_desc msm8953_snoc = {
1272 .type = QCOM_ICC_NOC,
1273 .bus_clk_desc = &bus_1_clk,
1274 .nodes = msm8953_snoc_nodes,
1275 .num_nodes = ARRAY_SIZE(msm8953_snoc_nodes),
1276 .qos_offset = 0x7000,
1277 .regmap_cfg = &msm8953_snoc_regmap_config,
1278};
1279
1280static struct qcom_icc_node * const msm8953_snoc_mm_nodes[] = {
1281 [MAS_JPEG] = &mas_jpeg,
1282 [MAS_MDP] = &mas_mdp,
1283 [MAS_VENUS] = &mas_venus,
1284 [MAS_VFE0] = &mas_vfe0,
1285 [MAS_VFE1] = &mas_vfe1,
1286 [MAS_CPP] = &mas_cpp,
1287 [SLV_SNOC_BIMC_0] = &slv_snoc_bimc_0,
1288 [SLV_SNOC_BIMC_2] = &slv_snoc_bimc_2,
1289 [SLV_CATS_0] = &slv_cats_0,
1290};
1291
1292static const struct qcom_icc_desc msm8953_snoc_mm = {
1293 .type = QCOM_ICC_NOC,
1294 .bus_clk_desc = &bus_2_clk,
1295 .nodes = msm8953_snoc_mm_nodes,
1296 .num_nodes = ARRAY_SIZE(msm8953_snoc_mm_nodes),
1297 .qos_offset = 0x7000,
1298 .regmap_cfg = &msm8953_snoc_regmap_config,
1299};
1300
1301static const struct of_device_id msm8953_noc_of_match[] = {
1302 { .compatible = "qcom,msm8953-bimc", .data = &msm8953_bimc },
1303 { .compatible = "qcom,msm8953-pcnoc", .data = &msm8953_pcnoc },
1304 { .compatible = "qcom,msm8953-snoc", .data = &msm8953_snoc },
1305 { .compatible = "qcom,msm8953-snoc-mm", .data = &msm8953_snoc_mm },
1306 { }
1307};
1308
1309static struct platform_driver msm8953_noc_driver = {
1310 .probe = qnoc_probe,
1311 .remove_new = qnoc_remove,
1312 .driver = {
1313 .name = "qnoc-msm8953",
1314 .of_match_table = msm8953_noc_of_match,
1315 },
1316};
1317
1318module_platform_driver(msm8953_noc_driver);
1319MODULE_DEVICE_TABLE(of, msm8953_noc_of_match);
1320MODULE_DESCRIPTION("Qualcomm MSM8953 NoC driver");
1321MODULE_LICENSE("GPL");