tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Zheng Yang <zhengyang@rock-chips.com>
5 * Yakir Yang <ykk@rock-chips.com>
6 */
7
8#include <linux/irq.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/err.h>
12#include <linux/hdmi.h>
13#include <linux/mod_devicetable.h>
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <linux/platform_device.h>
17
18#include <drm/drm_atomic.h>
19#include <drm/drm_atomic_helper.h>
20#include <drm/drm_edid.h>
21#include <drm/drm_of.h>
22#include <drm/drm_probe_helper.h>
23#include <drm/drm_simple_kms_helper.h>
24
25#include <drm/display/drm_hdmi_helper.h>
26#include <drm/display/drm_hdmi_state_helper.h>
27
28#include "rockchip_drm_drv.h"
29
30#include "inno_hdmi.h"
31
32#define INNO_HDMI_MIN_TMDS_CLOCK 25000000U
33
34struct inno_hdmi_phy_config {
35 unsigned long pixelclock;
36 u8 pre_emphasis;
37 u8 voltage_level_control;
38};
39
40struct inno_hdmi_variant {
41 struct inno_hdmi_phy_config *phy_configs;
42 struct inno_hdmi_phy_config *default_phy_config;
43};
44
45struct inno_hdmi_i2c {
46 struct i2c_adapter adap;
47
48 u8 ddc_addr;
49 u8 segment_addr;
50
51 struct mutex lock;
52 struct completion cmp;
53};
54
55struct inno_hdmi {
56 struct device *dev;
57
58 struct clk *pclk;
59 struct clk *refclk;
60 void __iomem *regs;
61
62 struct drm_connector connector;
63 struct rockchip_encoder encoder;
64
65 struct inno_hdmi_i2c *i2c;
66 struct i2c_adapter *ddc;
67
68 const struct inno_hdmi_variant *variant;
69};
70
71struct inno_hdmi_connector_state {
72 struct drm_connector_state base;
73 unsigned int colorimetry;
74};
75
76static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder)
77{
78 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
79
80 return container_of(rkencoder, struct inno_hdmi, encoder);
81}
82
83static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector)
84{
85 return container_of(connector, struct inno_hdmi, connector);
86}
87
88#define to_inno_hdmi_conn_state(conn_state) \
89 container_of_const(conn_state, struct inno_hdmi_connector_state, base)
90
91enum {
92 CSC_RGB_0_255_TO_ITU601_16_235_8BIT,
93 CSC_RGB_0_255_TO_ITU709_16_235_8BIT,
94 CSC_RGB_0_255_TO_RGB_16_235_8BIT,
95};
96
97static const char coeff_csc[][24] = {
98 /*
99 * RGB2YUV:601 SD mode:
100 * Cb = -0.291G - 0.148R + 0.439B + 128
101 * Y = 0.504G + 0.257R + 0.098B + 16
102 * Cr = -0.368G + 0.439R - 0.071B + 128
103 */
104 {
105 0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80,
106 0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e,
107 0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80
108 },
109 /*
110 * RGB2YUV:709 HD mode:
111 * Cb = - 0.338G - 0.101R + 0.439B + 128
112 * Y = 0.614G + 0.183R + 0.062B + 16
113 * Cr = - 0.399G + 0.439R - 0.040B + 128
114 */
115 {
116 0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80,
117 0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10,
118 0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80
119 },
120 /*
121 * RGB[0:255]2RGB[16:235]:
122 * R' = R x (235-16)/255 + 16;
123 * G' = G x (235-16)/255 + 16;
124 * B' = B x (235-16)/255 + 16;
125 */
126 {
127 0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10,
128 0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
129 0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10
130 },
131};
132
133static struct inno_hdmi_phy_config rk3036_hdmi_phy_configs[] = {
134 { 74250000, 0x3f, 0xbb },
135 { 165000000, 0x6f, 0xbb },
136 { ~0UL, 0x00, 0x00 }
137};
138
139static struct inno_hdmi_phy_config rk3128_hdmi_phy_configs[] = {
140 { 74250000, 0x3f, 0xaa },
141 { 165000000, 0x5f, 0xaa },
142 { ~0UL, 0x00, 0x00 }
143};
144
145static int inno_hdmi_find_phy_config(struct inno_hdmi *hdmi,
146 unsigned long pixelclk)
147{
148 const struct inno_hdmi_phy_config *phy_configs =
149 hdmi->variant->phy_configs;
150 int i;
151
152 for (i = 0; phy_configs[i].pixelclock != ~0UL; i++) {
153 if (pixelclk <= phy_configs[i].pixelclock)
154 return i;
155 }
156
157 DRM_DEV_DEBUG(hdmi->dev, "No phy configuration for pixelclock %lu\n",
158 pixelclk);
159
160 return -EINVAL;
161}
162
163static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset)
164{
165 return readl_relaxed(hdmi->regs + (offset) * 0x04);
166}
167
168static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val)
169{
170 writel_relaxed(val, hdmi->regs + (offset) * 0x04);
171}
172
173static inline void hdmi_modb(struct inno_hdmi *hdmi, u16 offset,
174 u32 msk, u32 val)
175{
176 u8 temp = hdmi_readb(hdmi, offset) & ~msk;
177
178 temp |= val & msk;
179 hdmi_writeb(hdmi, offset, temp);
180}
181
182static void inno_hdmi_i2c_init(struct inno_hdmi *hdmi, unsigned long long rate)
183{
184 unsigned long long ddc_bus_freq = rate >> 2;
185
186 do_div(ddc_bus_freq, HDMI_SCL_RATE);
187
188 hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
189 hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
190
191 /* Clear the EDID interrupt flag and mute the interrupt */
192 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
193 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
194}
195
196static void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable)
197{
198 if (enable)
199 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON);
200 else
201 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF);
202}
203
204static void inno_hdmi_standby(struct inno_hdmi *hdmi)
205{
206 inno_hdmi_sys_power(hdmi, false);
207
208 hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00);
209 hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00);
210 hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00);
211 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
212};
213
214static void inno_hdmi_power_up(struct inno_hdmi *hdmi,
215 unsigned long mpixelclock)
216{
217 struct inno_hdmi_phy_config *phy_config;
218 int ret = inno_hdmi_find_phy_config(hdmi, mpixelclock);
219
220 if (ret < 0) {
221 phy_config = hdmi->variant->default_phy_config;
222 DRM_DEV_ERROR(hdmi->dev,
223 "Using default phy configuration for TMDS rate %lu",
224 mpixelclock);
225 } else {
226 phy_config = &hdmi->variant->phy_configs[ret];
227 }
228
229 inno_hdmi_sys_power(hdmi, false);
230
231 hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, phy_config->pre_emphasis);
232 hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->voltage_level_control);
233 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
234 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14);
235 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10);
236 hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f);
237 hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00);
238 hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01);
239
240 inno_hdmi_sys_power(hdmi, true);
241};
242
243static void inno_hdmi_reset(struct inno_hdmi *hdmi)
244{
245 u32 val;
246 u32 msk;
247
248 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL);
249 udelay(100);
250
251 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG);
252 udelay(100);
253
254 msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL;
255 val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH;
256 hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val);
257
258 inno_hdmi_standby(hdmi);
259}
260
261static int inno_hdmi_disable_frame(struct drm_connector *connector,
262 enum hdmi_infoframe_type type)
263{
264 struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
265
266 if (type != HDMI_INFOFRAME_TYPE_AVI) {
267 drm_err(connector->dev,
268 "Unsupported infoframe type: %u\n", type);
269 return 0;
270 }
271
272 hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, INFOFRAME_AVI);
273
274 return 0;
275}
276
277static int inno_hdmi_upload_frame(struct drm_connector *connector,
278 enum hdmi_infoframe_type type,
279 const u8 *buffer, size_t len)
280{
281 struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
282 u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
283 ssize_t i;
284
285 if (type != HDMI_INFOFRAME_TYPE_AVI) {
286 drm_err(connector->dev,
287 "Unsupported infoframe type: %u\n", type);
288 return 0;
289 }
290
291 inno_hdmi_disable_frame(connector, type);
292
293 for (i = 0; i < len; i++)
294 hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i,
295 packed_frame[i]);
296
297 return 0;
298}
299
300static const struct drm_connector_hdmi_funcs inno_hdmi_hdmi_connector_funcs = {
301 .clear_infoframe = inno_hdmi_disable_frame,
302 .write_infoframe = inno_hdmi_upload_frame,
303};
304
305static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi)
306{
307 struct drm_connector *connector = &hdmi->connector;
308 struct drm_connector_state *conn_state = connector->state;
309 struct inno_hdmi_connector_state *inno_conn_state =
310 to_inno_hdmi_conn_state(conn_state);
311 int c0_c2_change = 0;
312 int csc_enable = 0;
313 int csc_mode = 0;
314 int auto_csc = 0;
315 int value;
316 int i;
317
318 /* Input video mode is SDR RGB24bit, data enable signal from external */
319 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL |
320 v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444));
321
322 /* Input color hardcode to RGB, and output color hardcode to RGB888 */
323 value = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) |
324 v_VIDEO_OUTPUT_COLOR(0) |
325 v_VIDEO_INPUT_CSP(0);
326 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value);
327
328 if (conn_state->hdmi.output_format == HDMI_COLORSPACE_RGB) {
329 if (conn_state->hdmi.is_limited_range) {
330 csc_mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
331 auto_csc = AUTO_CSC_DISABLE;
332 c0_c2_change = C0_C2_CHANGE_DISABLE;
333 csc_enable = v_CSC_ENABLE;
334
335 } else {
336 value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1);
337 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
338
339 hdmi_modb(hdmi, HDMI_VIDEO_CONTRL,
340 m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP,
341 v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) |
342 v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE));
343 return 0;
344 }
345 } else {
346 if (inno_conn_state->colorimetry == HDMI_COLORIMETRY_ITU_601) {
347 if (conn_state->hdmi.output_format == HDMI_COLORSPACE_YUV444) {
348 csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
349 auto_csc = AUTO_CSC_DISABLE;
350 c0_c2_change = C0_C2_CHANGE_DISABLE;
351 csc_enable = v_CSC_ENABLE;
352 }
353 } else {
354 if (conn_state->hdmi.output_format == HDMI_COLORSPACE_YUV444) {
355 csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
356 auto_csc = AUTO_CSC_DISABLE;
357 c0_c2_change = C0_C2_CHANGE_DISABLE;
358 csc_enable = v_CSC_ENABLE;
359 }
360 }
361 }
362
363 for (i = 0; i < 24; i++)
364 hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i,
365 coeff_csc[csc_mode][i]);
366
367 value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1);
368 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
369 hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC |
370 m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) |
371 v_VIDEO_C0_C2_SWAP(c0_c2_change));
372
373 return 0;
374}
375
376static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi,
377 struct drm_display_mode *mode)
378{
379 int value;
380
381 /* Set detail external video timing polarity and interlace mode */
382 value = v_EXTERANL_VIDEO(1);
383 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
384 v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0);
385 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
386 v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0);
387 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
388 v_INETLACE(1) : v_INETLACE(0);
389 hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value);
390
391 /* Set detail external video timing */
392 value = mode->htotal;
393 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF);
394 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF);
395
396 value = mode->htotal - mode->hdisplay;
397 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF);
398 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF);
399
400 value = mode->htotal - mode->hsync_start;
401 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF);
402 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF);
403
404 value = mode->hsync_end - mode->hsync_start;
405 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF);
406 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF);
407
408 value = mode->vtotal;
409 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF);
410 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF);
411
412 value = mode->vtotal - mode->vdisplay;
413 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF);
414
415 value = mode->vtotal - mode->vsync_start;
416 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF);
417
418 value = mode->vsync_end - mode->vsync_start;
419 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF);
420
421 hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e);
422 hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c);
423 hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01);
424
425 return 0;
426}
427
428static int inno_hdmi_setup(struct inno_hdmi *hdmi,
429 struct drm_atomic_state *state)
430{
431 struct drm_connector *connector = &hdmi->connector;
432 struct drm_display_info *display = &connector->display_info;
433 struct drm_connector_state *new_conn_state;
434 struct drm_crtc_state *new_crtc_state;
435
436 new_conn_state = drm_atomic_get_new_connector_state(state, connector);
437 if (WARN_ON(!new_conn_state))
438 return -EINVAL;
439
440 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
441 if (WARN_ON(!new_crtc_state))
442 return -EINVAL;
443
444 /* Mute video and audio output */
445 hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
446 v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1));
447
448 /* Set HDMI Mode */
449 hdmi_writeb(hdmi, HDMI_HDCP_CTRL,
450 v_HDMI_DVI(display->is_hdmi));
451
452 inno_hdmi_config_video_timing(hdmi, &new_crtc_state->adjusted_mode);
453
454 inno_hdmi_config_video_csc(hdmi);
455
456 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
457
458 /*
459 * When IP controller have configured to an accurate video
460 * timing, then the TMDS clock source would be switched to
461 * DCLK_LCDC, so we need to init the TMDS rate to mode pixel
462 * clock rate, and reconfigure the DDC clock.
463 */
464 inno_hdmi_i2c_init(hdmi, new_conn_state->hdmi.tmds_char_rate);
465
466 /* Unmute video and audio output */
467 hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
468 v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0));
469
470 inno_hdmi_power_up(hdmi, new_conn_state->hdmi.tmds_char_rate);
471
472 return 0;
473}
474
475static enum drm_mode_status inno_hdmi_display_mode_valid(struct inno_hdmi *hdmi,
476 struct drm_display_mode *mode)
477{
478 unsigned long mpixelclk, max_tolerance;
479 long rounded_refclk;
480
481 /* No support for double-clock modes */
482 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
483 return MODE_BAD;
484
485 mpixelclk = mode->clock * 1000;
486
487 if (mpixelclk < INNO_HDMI_MIN_TMDS_CLOCK)
488 return MODE_CLOCK_LOW;
489
490 if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0)
491 return MODE_CLOCK_HIGH;
492
493 if (hdmi->refclk) {
494 rounded_refclk = clk_round_rate(hdmi->refclk, mpixelclk);
495 if (rounded_refclk < 0)
496 return MODE_BAD;
497
498 /* Vesa DMT standard mentions +/- 0.5% max tolerance */
499 max_tolerance = mpixelclk / 200;
500 if (abs_diff((unsigned long)rounded_refclk, mpixelclk) > max_tolerance)
501 return MODE_NOCLOCK;
502 }
503
504 return MODE_OK;
505}
506
507static void inno_hdmi_encoder_enable(struct drm_encoder *encoder,
508 struct drm_atomic_state *state)
509{
510 struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
511
512 inno_hdmi_setup(hdmi, state);
513}
514
515static void inno_hdmi_encoder_disable(struct drm_encoder *encoder,
516 struct drm_atomic_state *state)
517{
518 struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
519
520 inno_hdmi_standby(hdmi);
521}
522
523static int
524inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
525 struct drm_crtc_state *crtc_state,
526 struct drm_connector_state *conn_state)
527{
528 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
529 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
530 u8 vic = drm_match_cea_mode(mode);
531 struct inno_hdmi_connector_state *inno_conn_state =
532 to_inno_hdmi_conn_state(conn_state);
533
534 s->output_mode = ROCKCHIP_OUT_MODE_P888;
535 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
536
537 if (vic == 6 || vic == 7 ||
538 vic == 21 || vic == 22 ||
539 vic == 2 || vic == 3 ||
540 vic == 17 || vic == 18)
541 inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_601;
542 else
543 inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709;
544
545 return 0;
546}
547
548static struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = {
549 .atomic_check = inno_hdmi_encoder_atomic_check,
550 .atomic_enable = inno_hdmi_encoder_enable,
551 .atomic_disable = inno_hdmi_encoder_disable,
552};
553
554static enum drm_connector_status
555inno_hdmi_connector_detect(struct drm_connector *connector, bool force)
556{
557 struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
558
559 return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ?
560 connector_status_connected : connector_status_disconnected;
561}
562
563static int inno_hdmi_connector_get_modes(struct drm_connector *connector)
564{
565 struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
566 const struct drm_edid *drm_edid;
567 int ret = 0;
568
569 if (!hdmi->ddc)
570 return 0;
571
572 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc);
573 drm_edid_connector_update(connector, drm_edid);
574 ret = drm_edid_connector_add_modes(connector);
575 drm_edid_free(drm_edid);
576
577 return ret;
578}
579
580static enum drm_mode_status
581inno_hdmi_connector_mode_valid(struct drm_connector *connector,
582 struct drm_display_mode *mode)
583{
584 struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
585
586 return inno_hdmi_display_mode_valid(hdmi, mode);
587}
588
589static void
590inno_hdmi_connector_destroy_state(struct drm_connector *connector,
591 struct drm_connector_state *state)
592{
593 struct inno_hdmi_connector_state *inno_conn_state =
594 to_inno_hdmi_conn_state(state);
595
596 __drm_atomic_helper_connector_destroy_state(&inno_conn_state->base);
597 kfree(inno_conn_state);
598}
599
600static void inno_hdmi_connector_reset(struct drm_connector *connector)
601{
602 struct inno_hdmi_connector_state *inno_conn_state;
603
604 if (connector->state) {
605 inno_hdmi_connector_destroy_state(connector, connector->state);
606 connector->state = NULL;
607 }
608
609 inno_conn_state = kzalloc(sizeof(*inno_conn_state), GFP_KERNEL);
610 if (!inno_conn_state)
611 return;
612
613 __drm_atomic_helper_connector_reset(connector, &inno_conn_state->base);
614 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state);
615
616 inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709;
617}
618
619static struct drm_connector_state *
620inno_hdmi_connector_duplicate_state(struct drm_connector *connector)
621{
622 struct inno_hdmi_connector_state *inno_conn_state;
623
624 if (WARN_ON(!connector->state))
625 return NULL;
626
627 inno_conn_state = kmemdup(to_inno_hdmi_conn_state(connector->state),
628 sizeof(*inno_conn_state), GFP_KERNEL);
629
630 if (!inno_conn_state)
631 return NULL;
632
633 __drm_atomic_helper_connector_duplicate_state(connector,
634 &inno_conn_state->base);
635
636 return &inno_conn_state->base;
637}
638
639static const struct drm_connector_funcs inno_hdmi_connector_funcs = {
640 .fill_modes = drm_helper_probe_single_connector_modes,
641 .detect = inno_hdmi_connector_detect,
642 .reset = inno_hdmi_connector_reset,
643 .atomic_duplicate_state = inno_hdmi_connector_duplicate_state,
644 .atomic_destroy_state = inno_hdmi_connector_destroy_state,
645};
646
647static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = {
648 .atomic_check = drm_atomic_helper_connector_hdmi_check,
649 .get_modes = inno_hdmi_connector_get_modes,
650 .mode_valid = inno_hdmi_connector_mode_valid,
651};
652
653static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi)
654{
655 struct drm_encoder *encoder = &hdmi->encoder.encoder;
656 struct device *dev = hdmi->dev;
657
658 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
659
660 /*
661 * If we failed to find the CRTC(s) which this encoder is
662 * supposed to be connected to, it's because the CRTC has
663 * not been registered yet. Defer probing, and hope that
664 * the required CRTC is added later.
665 */
666 if (encoder->possible_crtcs == 0)
667 return -EPROBE_DEFER;
668
669 drm_encoder_helper_add(encoder, &inno_hdmi_encoder_helper_funcs);
670 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
671
672 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
673
674 drm_connector_helper_add(&hdmi->connector,
675 &inno_hdmi_connector_helper_funcs);
676 drmm_connector_hdmi_init(drm, &hdmi->connector,
677 "Rockchip", "Inno HDMI",
678 &inno_hdmi_connector_funcs,
679 &inno_hdmi_hdmi_connector_funcs,
680 DRM_MODE_CONNECTOR_HDMIA,
681 hdmi->ddc,
682 BIT(HDMI_COLORSPACE_RGB),
683 8);
684
685 drm_connector_attach_encoder(&hdmi->connector, encoder);
686
687 return 0;
688}
689
690static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi)
691{
692 struct inno_hdmi_i2c *i2c = hdmi->i2c;
693 u8 stat;
694
695 stat = hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1);
696 if (!(stat & m_INT_EDID_READY))
697 return IRQ_NONE;
698
699 /* Clear HDMI EDID interrupt flag */
700 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
701
702 complete(&i2c->cmp);
703
704 return IRQ_HANDLED;
705}
706
707static irqreturn_t inno_hdmi_hardirq(int irq, void *dev_id)
708{
709 struct inno_hdmi *hdmi = dev_id;
710 irqreturn_t ret = IRQ_NONE;
711 u8 interrupt;
712
713 if (hdmi->i2c)
714 ret = inno_hdmi_i2c_irq(hdmi);
715
716 interrupt = hdmi_readb(hdmi, HDMI_STATUS);
717 if (interrupt & m_INT_HOTPLUG) {
718 hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG);
719 ret = IRQ_WAKE_THREAD;
720 }
721
722 return ret;
723}
724
725static irqreturn_t inno_hdmi_irq(int irq, void *dev_id)
726{
727 struct inno_hdmi *hdmi = dev_id;
728
729 drm_helper_hpd_irq_event(hdmi->connector.dev);
730
731 return IRQ_HANDLED;
732}
733
734static int inno_hdmi_i2c_read(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
735{
736 int length = msgs->len;
737 u8 *buf = msgs->buf;
738 int ret;
739
740 ret = wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10);
741 if (!ret)
742 return -EAGAIN;
743
744 while (length--)
745 *buf++ = hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR);
746
747 return 0;
748}
749
750static int inno_hdmi_i2c_write(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
751{
752 /*
753 * The DDC module only support read EDID message, so
754 * we assume that each word write to this i2c adapter
755 * should be the offset of EDID word address.
756 */
757 if ((msgs->len != 1) ||
758 ((msgs->addr != DDC_ADDR) && (msgs->addr != DDC_SEGMENT_ADDR)))
759 return -EINVAL;
760
761 reinit_completion(&hdmi->i2c->cmp);
762
763 if (msgs->addr == DDC_SEGMENT_ADDR)
764 hdmi->i2c->segment_addr = msgs->buf[0];
765 if (msgs->addr == DDC_ADDR)
766 hdmi->i2c->ddc_addr = msgs->buf[0];
767
768 /* Set edid fifo first addr */
769 hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00);
770
771 /* Set edid word address 0x00/0x80 */
772 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
773
774 /* Set edid segment pointer */
775 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
776
777 return 0;
778}
779
780static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap,
781 struct i2c_msg *msgs, int num)
782{
783 struct inno_hdmi *hdmi = i2c_get_adapdata(adap);
784 struct inno_hdmi_i2c *i2c = hdmi->i2c;
785 int i, ret = 0;
786
787 mutex_lock(&i2c->lock);
788
789 /* Clear the EDID interrupt flag and unmute the interrupt */
790 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY);
791 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
792
793 for (i = 0; i < num; i++) {
794 DRM_DEV_DEBUG(hdmi->dev,
795 "xfer: num: %d/%d, len: %d, flags: %#x\n",
796 i + 1, num, msgs[i].len, msgs[i].flags);
797
798 if (msgs[i].flags & I2C_M_RD)
799 ret = inno_hdmi_i2c_read(hdmi, &msgs[i]);
800 else
801 ret = inno_hdmi_i2c_write(hdmi, &msgs[i]);
802
803 if (ret < 0)
804 break;
805 }
806
807 if (!ret)
808 ret = num;
809
810 /* Mute HDMI EDID interrupt */
811 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
812
813 mutex_unlock(&i2c->lock);
814
815 return ret;
816}
817
818static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter)
819{
820 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
821}
822
823static const struct i2c_algorithm inno_hdmi_algorithm = {
824 .master_xfer = inno_hdmi_i2c_xfer,
825 .functionality = inno_hdmi_i2c_func,
826};
827
828static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi)
829{
830 struct i2c_adapter *adap;
831 struct inno_hdmi_i2c *i2c;
832 int ret;
833
834 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
835 if (!i2c)
836 return ERR_PTR(-ENOMEM);
837
838 mutex_init(&i2c->lock);
839 init_completion(&i2c->cmp);
840
841 adap = &i2c->adap;
842 adap->owner = THIS_MODULE;
843 adap->dev.parent = hdmi->dev;
844 adap->dev.of_node = hdmi->dev->of_node;
845 adap->algo = &inno_hdmi_algorithm;
846 strscpy(adap->name, "Inno HDMI", sizeof(adap->name));
847 i2c_set_adapdata(adap, hdmi);
848
849 ret = i2c_add_adapter(adap);
850 if (ret) {
851 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
852 devm_kfree(hdmi->dev, i2c);
853 return ERR_PTR(ret);
854 }
855
856 hdmi->i2c = i2c;
857
858 DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
859
860 return adap;
861}
862
863static int inno_hdmi_bind(struct device *dev, struct device *master,
864 void *data)
865{
866 struct platform_device *pdev = to_platform_device(dev);
867 struct drm_device *drm = data;
868 struct inno_hdmi *hdmi;
869 const struct inno_hdmi_variant *variant;
870 int irq;
871 int ret;
872
873 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
874 if (!hdmi)
875 return -ENOMEM;
876
877 hdmi->dev = dev;
878
879 variant = of_device_get_match_data(hdmi->dev);
880 if (!variant)
881 return -EINVAL;
882
883 hdmi->variant = variant;
884
885 hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
886 if (IS_ERR(hdmi->regs))
887 return PTR_ERR(hdmi->regs);
888
889 hdmi->pclk = devm_clk_get(hdmi->dev, "pclk");
890 if (IS_ERR(hdmi->pclk)) {
891 DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI pclk clk\n");
892 return PTR_ERR(hdmi->pclk);
893 }
894
895 ret = clk_prepare_enable(hdmi->pclk);
896 if (ret) {
897 DRM_DEV_ERROR(hdmi->dev,
898 "Cannot enable HDMI pclk clock: %d\n", ret);
899 return ret;
900 }
901
902 hdmi->refclk = devm_clk_get_optional(hdmi->dev, "ref");
903 if (IS_ERR(hdmi->refclk)) {
904 DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI reference clock\n");
905 ret = PTR_ERR(hdmi->refclk);
906 goto err_disable_pclk;
907 }
908
909 ret = clk_prepare_enable(hdmi->refclk);
910 if (ret) {
911 DRM_DEV_ERROR(hdmi->dev,
912 "Cannot enable HDMI reference clock: %d\n", ret);
913 goto err_disable_pclk;
914 }
915
916 irq = platform_get_irq(pdev, 0);
917 if (irq < 0) {
918 ret = irq;
919 goto err_disable_clk;
920 }
921
922 inno_hdmi_reset(hdmi);
923
924 hdmi->ddc = inno_hdmi_i2c_adapter(hdmi);
925 if (IS_ERR(hdmi->ddc)) {
926 ret = PTR_ERR(hdmi->ddc);
927 hdmi->ddc = NULL;
928 goto err_disable_clk;
929 }
930
931 /*
932 * When the controller isn't configured to an accurate
933 * video timing and there is no reference clock available,
934 * then the TMDS clock source would be switched to PCLK_HDMI,
935 * so we need to init the TMDS rate to PCLK rate, and
936 * reconfigure the DDC clock.
937 */
938 if (hdmi->refclk)
939 inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->refclk));
940 else
941 inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->pclk));
942
943 ret = inno_hdmi_register(drm, hdmi);
944 if (ret)
945 goto err_put_adapter;
946
947 dev_set_drvdata(dev, hdmi);
948
949 /* Unmute hotplug interrupt */
950 hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1));
951
952 ret = devm_request_threaded_irq(dev, irq, inno_hdmi_hardirq,
953 inno_hdmi_irq, IRQF_SHARED,
954 dev_name(dev), hdmi);
955 if (ret < 0)
956 goto err_cleanup_hdmi;
957
958 return 0;
959err_cleanup_hdmi:
960 hdmi->connector.funcs->destroy(&hdmi->connector);
961 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
962err_put_adapter:
963 i2c_put_adapter(hdmi->ddc);
964err_disable_clk:
965 clk_disable_unprepare(hdmi->refclk);
966err_disable_pclk:
967 clk_disable_unprepare(hdmi->pclk);
968 return ret;
969}
970
971static void inno_hdmi_unbind(struct device *dev, struct device *master,
972 void *data)
973{
974 struct inno_hdmi *hdmi = dev_get_drvdata(dev);
975
976 hdmi->connector.funcs->destroy(&hdmi->connector);
977 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
978
979 i2c_put_adapter(hdmi->ddc);
980 clk_disable_unprepare(hdmi->refclk);
981 clk_disable_unprepare(hdmi->pclk);
982}
983
984static const struct component_ops inno_hdmi_ops = {
985 .bind = inno_hdmi_bind,
986 .unbind = inno_hdmi_unbind,
987};
988
989static int inno_hdmi_probe(struct platform_device *pdev)
990{
991 return component_add(&pdev->dev, &inno_hdmi_ops);
992}
993
994static void inno_hdmi_remove(struct platform_device *pdev)
995{
996 component_del(&pdev->dev, &inno_hdmi_ops);
997}
998
999static const struct inno_hdmi_variant rk3036_inno_hdmi_variant = {
1000 .phy_configs = rk3036_hdmi_phy_configs,
1001 .default_phy_config = &rk3036_hdmi_phy_configs[1],
1002};
1003
1004static const struct inno_hdmi_variant rk3128_inno_hdmi_variant = {
1005 .phy_configs = rk3128_hdmi_phy_configs,
1006 .default_phy_config = &rk3128_hdmi_phy_configs[1],
1007};
1008
1009static const struct of_device_id inno_hdmi_dt_ids[] = {
1010 { .compatible = "rockchip,rk3036-inno-hdmi",
1011 .data = &rk3036_inno_hdmi_variant,
1012 },
1013 { .compatible = "rockchip,rk3128-inno-hdmi",
1014 .data = &rk3128_inno_hdmi_variant,
1015 },
1016 {},
1017};
1018MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids);
1019
1020struct platform_driver inno_hdmi_driver = {
1021 .probe = inno_hdmi_probe,
1022 .remove_new = inno_hdmi_remove,
1023 .driver = {
1024 .name = "innohdmi-rockchip",
1025 .of_match_table = inno_hdmi_dt_ids,
1026 },
1027};