tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY
8
9maintainers:
10 - Richard Zhu <hongxing.zhu@nxp.com>
11
12properties:
13 compatible:
14 enum:
15 - fsl,imx8qm-hsio
16 - fsl,imx8qxp-hsio
17 reg:
18 items:
19 - description: Base address and length of the PHY block
20 - description: HSIO control and status registers(CSR) of the PHY
21 - description: HSIO CSR of the controller bound to the PHY
22 - description: HSIO CSR for MISC
23
24 reg-names:
25 items:
26 - const: reg
27 - const: phy
28 - const: ctrl
29 - const: misc
30
31 "#phy-cells":
32 const: 3
33 description:
34 The first defines lane index.
35 The second defines the type of the PHY refer to the include phy.h.
36 The third defines the controller index, indicated which controller
37 is bound to the lane.
38
39 clocks:
40 minItems: 5
41 maxItems: 14
42
43 clock-names:
44 minItems: 5
45 maxItems: 14
46
47 fsl,hsio-cfg:
48 description: |
49 Specifies the use case of the HSIO module in the hardware design.
50 Regarding the design of i.MX8QM HSIO subsystem, HSIO module can be
51 confiured as following three use cases.
52 +---------------------------------------+
53 | | i.MX8QM |
54 |------------------|--------------------|
55 | | Lane0| Lane1| Lane2|
56 |------------------|------|------|------|
57 | pciea-x2-sata | PCIEA| PCIEA| SATA |
58 |------------------|------|------|------|
59 | pciea-x2-pcieb | PCIEA| PCIEA| PCIEB|
60 |------------------|------|------|------|
61 | pciea-pcieb-sata | PCIEA| PCIEB| SATA |
62 +---------------------------------------+
63 $ref: /schemas/types.yaml#/definitions/string
64 enum: [ pciea-x2-sata, pciea-x2-pcieb, pciea-pcieb-sata]
65 default: pciea-pcieb-sata
66
67 fsl,refclk-pad-mode:
68 description:
69 Specifies the mode of the refclk pad used. INPUT(PHY refclock is
70 provided externally via the refclk pad) or OUTPUT(PHY refclock is
71 derived from SoC internal source and provided on the refclk pad).
72 This property not exists means unused(PHY refclock is derived from
73 SoC internal source).
74 $ref: /schemas/types.yaml#/definitions/string
75 enum: [ input, output, unused ]
76 default: unused
77
78 power-domains:
79 minItems: 1
80 maxItems: 2
81
82required:
83 - compatible
84 - reg
85 - reg-names
86 - "#phy-cells"
87 - clocks
88 - clock-names
89 - fsl,hsio-cfg
90
91allOf:
92 - if:
93 properties:
94 compatible:
95 contains:
96 enum:
97 - fsl,imx8qxp-hsio
98 then:
99 properties:
100 clock-names:
101 items:
102 - const: pclk0
103 - const: apb_pclk0
104 - const: phy0_crr
105 - const: ctl0_crr
106 - const: misc_crr
107 power-domains:
108 maxItems: 1
109
110 - if:
111 properties:
112 compatible:
113 contains:
114 enum:
115 - fsl,imx8qm-hsio
116 then:
117 properties:
118 clock-names:
119 items:
120 - const: pclk0
121 - const: pclk1
122 - const: apb_pclk0
123 - const: apb_pclk1
124 - const: pclk2
125 - const: epcs_tx
126 - const: epcs_rx
127 - const: apb_pclk2
128 - const: phy0_crr
129 - const: phy1_crr
130 - const: ctl0_crr
131 - const: ctl1_crr
132 - const: ctl2_crr
133 - const: misc_crr
134 power-domains:
135 minItems: 2
136
137additionalProperties: false
138
139examples:
140 - |
141 #include <dt-bindings/clock/imx8-clock.h>
142 #include <dt-bindings/clock/imx8-lpcg.h>
143 #include <dt-bindings/firmware/imx/rsrc.h>
144 #include <dt-bindings/phy/phy-imx8-pcie.h>
145
146 phy@5f1a0000 {
147 compatible = "fsl,imx8qxp-hsio";
148 reg = <0x5f1a0000 0x10000>,
149 <0x5f120000 0x10000>,
150 <0x5f140000 0x10000>,
151 <0x5f160000 0x10000>;
152 reg-names = "reg", "phy", "ctrl", "misc";
153 clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>,
154 <&phyx1_lpcg IMX_LPCG_CLK_4>,
155 <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,
156 <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,
157 <&misc_crr5_lpcg IMX_LPCG_CLK_4>;
158 clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr", "misc_crr";
159 power-domains = <&pd IMX_SC_R_SERDES_1>;
160 #phy-cells = <3>;
161 fsl,hsio-cfg = "pciea-pcieb-sata";
162 fsl,refclk-pad-mode = "input";
163 };
164...