tjh.dev
Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (C) 2015 - 2016 Thomas Körper, esd electronic system design gmbh
3 * Copyright (C) 2017 - 2023 Stefan Mätje, esd electronics gmbh
4 */
5
6#include <linux/bits.h>
7#include <linux/can/dev.h>
8#include <linux/kernel.h>
9#include <linux/netdevice.h>
10#include <linux/units.h>
11
12#define ACC_TS_FREQ_80MHZ (80 * HZ_PER_MHZ)
13#define ACC_I2C_ADDON_DETECT_DELAY_MS 10
14
15/* esdACC Overview Module */
16#define ACC_OV_OF_PROBE 0x0000
17#define ACC_OV_OF_VERSION 0x0004
18#define ACC_OV_OF_INFO 0x0008
19#define ACC_OV_OF_CANCORE_FREQ 0x000c
20#define ACC_OV_OF_TS_FREQ_LO 0x0010
21#define ACC_OV_OF_TS_FREQ_HI 0x0014
22#define ACC_OV_OF_IRQ_STATUS_CORES 0x0018
23#define ACC_OV_OF_TS_CURR_LO 0x001c
24#define ACC_OV_OF_TS_CURR_HI 0x0020
25#define ACC_OV_OF_IRQ_STATUS 0x0028
26#define ACC_OV_OF_MODE 0x002c
27#define ACC_OV_OF_BM_IRQ_COUNTER 0x0070
28#define ACC_OV_OF_BM_IRQ_MASK 0x0074
29#define ACC_OV_OF_MSI_DATA 0x0080
30#define ACC_OV_OF_MSI_ADDRESSOFFSET 0x0084
31
32/* Feature flags are contained in the upper 16 bit of the version
33 * register at ACC_OV_OF_VERSION but only used with these masks after
34 * extraction into an extra variable => (xx - 16).
35 */
36#define ACC_OV_REG_FEAT_MASK_CANFD BIT(27 - 16)
37#define ACC_OV_REG_FEAT_MASK_NEW_PSC BIT(28 - 16)
38
39#define ACC_OV_REG_MODE_MASK_ENDIAN_LITTLE BIT(0)
40#define ACC_OV_REG_MODE_MASK_BM_ENABLE BIT(1)
41#define ACC_OV_REG_MODE_MASK_MODE_LED BIT(2)
42#define ACC_OV_REG_MODE_MASK_TIMER_ENABLE BIT(4)
43#define ACC_OV_REG_MODE_MASK_TIMER_ONE_SHOT BIT(5)
44#define ACC_OV_REG_MODE_MASK_TIMER_ABSOLUTE BIT(6)
45#define ACC_OV_REG_MODE_MASK_TIMER GENMASK(6, 4)
46#define ACC_OV_REG_MODE_MASK_TS_SRC GENMASK(8, 7)
47#define ACC_OV_REG_MODE_MASK_I2C_ENABLE BIT(11)
48#define ACC_OV_REG_MODE_MASK_MSI_ENABLE BIT(14)
49#define ACC_OV_REG_MODE_MASK_NEW_PSC_ENABLE BIT(15)
50#define ACC_OV_REG_MODE_MASK_FPGA_RESET BIT(31)
51
52/* esdACC CAN Core Module */
53#define ACC_CORE_OF_CTRL_MODE 0x0000
54#define ACC_CORE_OF_STATUS_IRQ 0x0008
55#define ACC_CORE_OF_BRP 0x000c
56#define ACC_CORE_OF_BTR 0x0010
57#define ACC_CORE_OF_FBTR 0x0014
58#define ACC_CORE_OF_STATUS 0x0030
59#define ACC_CORE_OF_TXFIFO_CONFIG 0x0048
60#define ACC_CORE_OF_TXFIFO_STATUS 0x004c
61#define ACC_CORE_OF_TX_STATUS_IRQ 0x0050
62#define ACC_CORE_OF_TX_ABORT_MASK 0x0054
63#define ACC_CORE_OF_BM_IRQ_COUNTER 0x0070
64#define ACC_CORE_OF_TXFIFO_ID 0x00c0
65#define ACC_CORE_OF_TXFIFO_DLC 0x00c4
66#define ACC_CORE_OF_TXFIFO_DATA_0 0x00c8
67#define ACC_CORE_OF_TXFIFO_DATA_1 0x00cc
68
69#define ACC_REG_CONTROL_MASK_MODE_RESETMODE BIT(0)
70#define ACC_REG_CONTROL_MASK_MODE_LOM BIT(1)
71#define ACC_REG_CONTROL_MASK_MODE_STM BIT(2)
72#define ACC_REG_CONTROL_MASK_MODE_TRANSEN BIT(5)
73#define ACC_REG_CONTROL_MASK_MODE_TS BIT(6)
74#define ACC_REG_CONTROL_MASK_MODE_SCHEDULE BIT(7)
75
76#define ACC_REG_CONTROL_MASK_IE_RXTX BIT(8)
77#define ACC_REG_CONTROL_MASK_IE_TXERROR BIT(9)
78#define ACC_REG_CONTROL_MASK_IE_ERRWARN BIT(10)
79#define ACC_REG_CONTROL_MASK_IE_OVERRUN BIT(11)
80#define ACC_REG_CONTROL_MASK_IE_TSI BIT(12)
81#define ACC_REG_CONTROL_MASK_IE_ERRPASS BIT(13)
82#define ACC_REG_CONTROL_MASK_IE_ALI BIT(14)
83#define ACC_REG_CONTROL_MASK_IE_BUSERR BIT(15)
84
85/* BRP and BTR register layout for CAN-Classic version */
86#define ACC_REG_BRP_CL_MASK_BRP GENMASK(8, 0)
87#define ACC_REG_BTR_CL_MASK_TSEG1 GENMASK(3, 0)
88#define ACC_REG_BTR_CL_MASK_TSEG2 GENMASK(18, 16)
89#define ACC_REG_BTR_CL_MASK_SJW GENMASK(25, 24)
90
91/* BRP and BTR register layout for CAN-FD version */
92#define ACC_REG_BRP_FD_MASK_BRP GENMASK(7, 0)
93#define ACC_REG_BTR_FD_MASK_TSEG1 GENMASK(7, 0)
94#define ACC_REG_BTR_FD_MASK_TSEG2 GENMASK(22, 16)
95#define ACC_REG_BTR_FD_MASK_SJW GENMASK(30, 24)
96
97/* 256 BM_MSGs of 32 byte size */
98#define ACC_CORE_DMAMSG_SIZE 32U
99#define ACC_CORE_DMABUF_SIZE (256U * ACC_CORE_DMAMSG_SIZE)
100
101enum acc_bmmsg_id {
102 BM_MSG_ID_RXTXDONE = 0x01,
103 BM_MSG_ID_TXABORT = 0x02,
104 BM_MSG_ID_OVERRUN = 0x03,
105 BM_MSG_ID_BUSERR = 0x04,
106 BM_MSG_ID_ERRPASSIVE = 0x05,
107 BM_MSG_ID_ERRWARN = 0x06,
108 BM_MSG_ID_TIMESLICE = 0x07,
109 BM_MSG_ID_HWTIMER = 0x08,
110 BM_MSG_ID_HOTPLUG = 0x09,
111};
112
113/* The struct acc_bmmsg_* structure declarations that follow here provide
114 * access to the ring buffer of bus master messages maintained by the FPGA
115 * bus master engine. All bus master messages have the same size of
116 * ACC_CORE_DMAMSG_SIZE and a minimum alignment of ACC_CORE_DMAMSG_SIZE in
117 * memory.
118 *
119 * All structure members are natural aligned. Therefore we should not need
120 * a __packed attribute. All struct acc_bmmsg_* declarations have at least
121 * reserved* members to fill the structure to the full ACC_CORE_DMAMSG_SIZE.
122 *
123 * A failure of this property due padding will be detected at compile time
124 * by static_assert(sizeof(union acc_bmmsg) == ACC_CORE_DMAMSG_SIZE).
125 */
126
127struct acc_bmmsg_rxtxdone {
128 u8 msg_id;
129 u8 txfifo_level;
130 u8 reserved1[2];
131 u8 txtsfifo_level;
132 u8 reserved2[3];
133 u32 id;
134 struct {
135 u8 len;
136 u8 txdfifo_idx;
137 u8 zeroes8;
138 u8 reserved;
139 } acc_dlc;
140 u8 data[CAN_MAX_DLEN];
141 /* Time stamps in struct acc_ov::timestamp_frequency ticks. */
142 u64 ts;
143};
144
145struct acc_bmmsg_txabort {
146 u8 msg_id;
147 u8 txfifo_level;
148 u16 abort_mask;
149 u8 txtsfifo_level;
150 u8 reserved2[1];
151 u16 abort_mask_txts;
152 u64 ts;
153 u32 reserved3[4];
154};
155
156struct acc_bmmsg_overrun {
157 u8 msg_id;
158 u8 txfifo_level;
159 u8 lost_cnt;
160 u8 reserved1;
161 u8 txtsfifo_level;
162 u8 reserved2[3];
163 u64 ts;
164 u32 reserved3[4];
165};
166
167struct acc_bmmsg_buserr {
168 u8 msg_id;
169 u8 txfifo_level;
170 u8 ecc;
171 u8 reserved1;
172 u8 txtsfifo_level;
173 u8 reserved2[3];
174 u64 ts;
175 u32 reg_status;
176 u32 reg_btr;
177 u32 reserved3[2];
178};
179
180struct acc_bmmsg_errstatechange {
181 u8 msg_id;
182 u8 txfifo_level;
183 u8 reserved1[2];
184 u8 txtsfifo_level;
185 u8 reserved2[3];
186 u64 ts;
187 u32 reg_status;
188 u32 reserved3[3];
189};
190
191struct acc_bmmsg_timeslice {
192 u8 msg_id;
193 u8 txfifo_level;
194 u8 reserved1[2];
195 u8 txtsfifo_level;
196 u8 reserved2[3];
197 u64 ts;
198 u32 reserved3[4];
199};
200
201struct acc_bmmsg_hwtimer {
202 u8 msg_id;
203 u8 reserved1[3];
204 u32 reserved2[1];
205 u64 timer;
206 u32 reserved3[4];
207};
208
209struct acc_bmmsg_hotplug {
210 u8 msg_id;
211 u8 reserved1[3];
212 u32 reserved2[7];
213};
214
215union acc_bmmsg {
216 u8 msg_id;
217 struct acc_bmmsg_rxtxdone rxtxdone;
218 struct acc_bmmsg_txabort txabort;
219 struct acc_bmmsg_overrun overrun;
220 struct acc_bmmsg_buserr buserr;
221 struct acc_bmmsg_errstatechange errstatechange;
222 struct acc_bmmsg_timeslice timeslice;
223 struct acc_bmmsg_hwtimer hwtimer;
224};
225
226/* Check size of union acc_bmmsg to be of expected size. */
227static_assert(sizeof(union acc_bmmsg) == ACC_CORE_DMAMSG_SIZE);
228
229struct acc_bmfifo {
230 const union acc_bmmsg *messages;
231 /* irq_cnt points to an u32 value where the esdACC FPGA deposits
232 * the bm_fifo head index in coherent DMA memory. Only bits 7..0
233 * are valid. Use READ_ONCE() to access this memory location.
234 */
235 const u32 *irq_cnt;
236 u32 local_irq_cnt;
237 u32 msg_fifo_tail;
238};
239
240struct acc_core {
241 void __iomem *addr;
242 struct net_device *netdev;
243 struct acc_bmfifo bmfifo;
244 u8 tx_fifo_size;
245 u8 tx_fifo_head;
246 u8 tx_fifo_tail;
247};
248
249struct acc_ov {
250 void __iomem *addr;
251 struct acc_bmfifo bmfifo;
252 u32 timestamp_frequency;
253 u32 core_frequency;
254 u16 version;
255 u16 features;
256 u8 total_cores;
257 u8 active_cores;
258};
259
260struct acc_net_priv {
261 struct can_priv can; /* must be the first member! */
262 struct acc_core *core;
263 struct acc_ov *ov;
264};
265
266static inline u32 acc_read32(struct acc_core *core, unsigned short offs)
267{
268 return ioread32be(core->addr + offs);
269}
270
271static inline void acc_write32(struct acc_core *core,
272 unsigned short offs, u32 v)
273{
274 iowrite32be(v, core->addr + offs);
275}
276
277static inline void acc_write32_noswap(struct acc_core *core,
278 unsigned short offs, u32 v)
279{
280 iowrite32(v, core->addr + offs);
281}
282
283static inline void acc_set_bits(struct acc_core *core,
284 unsigned short offs, u32 mask)
285{
286 u32 v = acc_read32(core, offs);
287
288 v |= mask;
289 acc_write32(core, offs, v);
290}
291
292static inline void acc_clear_bits(struct acc_core *core,
293 unsigned short offs, u32 mask)
294{
295 u32 v = acc_read32(core, offs);
296
297 v &= ~mask;
298 acc_write32(core, offs, v);
299}
300
301static inline int acc_resetmode_entered(struct acc_core *core)
302{
303 u32 ctrl = acc_read32(core, ACC_CORE_OF_CTRL_MODE);
304
305 return (ctrl & ACC_REG_CONTROL_MASK_MODE_RESETMODE) != 0;
306}
307
308static inline u32 acc_ov_read32(struct acc_ov *ov, unsigned short offs)
309{
310 return ioread32be(ov->addr + offs);
311}
312
313static inline void acc_ov_write32(struct acc_ov *ov,
314 unsigned short offs, u32 v)
315{
316 iowrite32be(v, ov->addr + offs);
317}
318
319static inline void acc_ov_set_bits(struct acc_ov *ov,
320 unsigned short offs, u32 b)
321{
322 u32 v = acc_ov_read32(ov, offs);
323
324 v |= b;
325 acc_ov_write32(ov, offs, v);
326}
327
328static inline void acc_ov_clear_bits(struct acc_ov *ov,
329 unsigned short offs, u32 b)
330{
331 u32 v = acc_ov_read32(ov, offs);
332
333 v &= ~b;
334 acc_ov_write32(ov, offs, v);
335}
336
337static inline void acc_reset_fpga(struct acc_ov *ov)
338{
339 acc_ov_write32(ov, ACC_OV_OF_MODE, ACC_OV_REG_MODE_MASK_FPGA_RESET);
340
341 /* (Re-)start and wait for completion of addon detection on the I^2C bus */
342 acc_ov_set_bits(ov, ACC_OV_OF_MODE, ACC_OV_REG_MODE_MASK_I2C_ENABLE);
343 mdelay(ACC_I2C_ADDON_DETECT_DELAY_MS);
344}
345
346void acc_init_ov(struct acc_ov *ov, struct device *dev);
347void acc_init_bm_ptr(struct acc_ov *ov, struct acc_core *cores,
348 const void *mem);
349int acc_open(struct net_device *netdev);
350int acc_close(struct net_device *netdev);
351netdev_tx_t acc_start_xmit(struct sk_buff *skb, struct net_device *netdev);
352int acc_get_berr_counter(const struct net_device *netdev,
353 struct can_berr_counter *bec);
354int acc_set_mode(struct net_device *netdev, enum can_mode mode);
355int acc_set_bittiming(struct net_device *netdev);
356irqreturn_t acc_card_interrupt(struct acc_ov *ov, struct acc_core *cores);