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linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * nested.c - nested mode translation support
4 *
5 * Copyright (C) 2023 Intel Corporation
6 *
7 * Author: Lu Baolu <baolu.lu@linux.intel.com>
8 * Jacob Pan <jacob.jun.pan@linux.intel.com>
9 * Yi Liu <yi.l.liu@intel.com>
10 */
11
12#define pr_fmt(fmt) "DMAR: " fmt
13
14#include <linux/iommu.h>
15#include <linux/pci.h>
16#include <linux/pci-ats.h>
17
18#include "iommu.h"
19#include "pasid.h"
20
21static int intel_nested_attach_dev(struct iommu_domain *domain,
22 struct device *dev)
23{
24 struct device_domain_info *info = dev_iommu_priv_get(dev);
25 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
26 struct intel_iommu *iommu = info->iommu;
27 unsigned long flags;
28 int ret = 0;
29
30 if (info->domain)
31 device_block_translation(dev);
32
33 if (iommu->agaw < dmar_domain->s2_domain->agaw) {
34 dev_err_ratelimited(dev, "Adjusted guest address width not compatible\n");
35 return -ENODEV;
36 }
37
38 /*
39 * Stage-1 domain cannot work alone, it is nested on a s2_domain.
40 * The s2_domain will be used in nested translation, hence needs
41 * to ensure the s2_domain is compatible with this IOMMU.
42 */
43 ret = prepare_domain_attach_device(&dmar_domain->s2_domain->domain, dev);
44 if (ret) {
45 dev_err_ratelimited(dev, "s2 domain is not compatible\n");
46 return ret;
47 }
48
49 ret = domain_attach_iommu(dmar_domain, iommu);
50 if (ret) {
51 dev_err_ratelimited(dev, "Failed to attach domain to iommu\n");
52 return ret;
53 }
54
55 ret = cache_tag_assign_domain(dmar_domain, dev, IOMMU_NO_PASID);
56 if (ret)
57 goto detach_iommu;
58
59 ret = intel_pasid_setup_nested(iommu, dev,
60 IOMMU_NO_PASID, dmar_domain);
61 if (ret)
62 goto unassign_tag;
63
64 info->domain = dmar_domain;
65 spin_lock_irqsave(&dmar_domain->lock, flags);
66 list_add(&info->link, &dmar_domain->devices);
67 spin_unlock_irqrestore(&dmar_domain->lock, flags);
68
69 domain_update_iotlb(dmar_domain);
70
71 return 0;
72unassign_tag:
73 cache_tag_unassign_domain(dmar_domain, dev, IOMMU_NO_PASID);
74detach_iommu:
75 domain_detach_iommu(dmar_domain, iommu);
76
77 return ret;
78}
79
80static void intel_nested_domain_free(struct iommu_domain *domain)
81{
82 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
83 struct dmar_domain *s2_domain = dmar_domain->s2_domain;
84
85 spin_lock(&s2_domain->s1_lock);
86 list_del(&dmar_domain->s2_link);
87 spin_unlock(&s2_domain->s1_lock);
88 kfree(dmar_domain);
89}
90
91static int intel_nested_cache_invalidate_user(struct iommu_domain *domain,
92 struct iommu_user_data_array *array)
93{
94 struct dmar_domain *dmar_domain = to_dmar_domain(domain);
95 struct iommu_hwpt_vtd_s1_invalidate inv_entry;
96 u32 index, processed = 0;
97 int ret = 0;
98
99 if (array->type != IOMMU_HWPT_INVALIDATE_DATA_VTD_S1) {
100 ret = -EINVAL;
101 goto out;
102 }
103
104 for (index = 0; index < array->entry_num; index++) {
105 ret = iommu_copy_struct_from_user_array(&inv_entry, array,
106 IOMMU_HWPT_INVALIDATE_DATA_VTD_S1,
107 index, __reserved);
108 if (ret)
109 break;
110
111 if ((inv_entry.flags & ~IOMMU_VTD_INV_FLAGS_LEAF) ||
112 inv_entry.__reserved) {
113 ret = -EOPNOTSUPP;
114 break;
115 }
116
117 if (!IS_ALIGNED(inv_entry.addr, VTD_PAGE_SIZE) ||
118 ((inv_entry.npages == U64_MAX) && inv_entry.addr)) {
119 ret = -EINVAL;
120 break;
121 }
122
123 cache_tag_flush_range(dmar_domain, inv_entry.addr,
124 inv_entry.addr + nrpages_to_size(inv_entry.npages) - 1,
125 inv_entry.flags & IOMMU_VTD_INV_FLAGS_LEAF);
126 processed++;
127 }
128
129out:
130 array->entry_num = processed;
131 return ret;
132}
133
134static const struct iommu_domain_ops intel_nested_domain_ops = {
135 .attach_dev = intel_nested_attach_dev,
136 .free = intel_nested_domain_free,
137 .cache_invalidate_user = intel_nested_cache_invalidate_user,
138};
139
140struct iommu_domain *intel_nested_domain_alloc(struct iommu_domain *parent,
141 const struct iommu_user_data *user_data)
142{
143 struct dmar_domain *s2_domain = to_dmar_domain(parent);
144 struct iommu_hwpt_vtd_s1 vtd;
145 struct dmar_domain *domain;
146 int ret;
147
148 /* Must be nested domain */
149 if (user_data->type != IOMMU_HWPT_DATA_VTD_S1)
150 return ERR_PTR(-EOPNOTSUPP);
151 if (parent->ops != intel_iommu_ops.default_domain_ops ||
152 !s2_domain->nested_parent)
153 return ERR_PTR(-EINVAL);
154
155 ret = iommu_copy_struct_from_user(&vtd, user_data,
156 IOMMU_HWPT_DATA_VTD_S1, __reserved);
157 if (ret)
158 return ERR_PTR(ret);
159
160 domain = kzalloc(sizeof(*domain), GFP_KERNEL_ACCOUNT);
161 if (!domain)
162 return ERR_PTR(-ENOMEM);
163
164 domain->use_first_level = true;
165 domain->s2_domain = s2_domain;
166 domain->s1_pgtbl = vtd.pgtbl_addr;
167 domain->s1_cfg = vtd;
168 domain->domain.ops = &intel_nested_domain_ops;
169 domain->domain.type = IOMMU_DOMAIN_NESTED;
170 INIT_LIST_HEAD(&domain->devices);
171 INIT_LIST_HEAD(&domain->dev_pasids);
172 INIT_LIST_HEAD(&domain->cache_tags);
173 spin_lock_init(&domain->lock);
174 spin_lock_init(&domain->cache_lock);
175 xa_init(&domain->iommu_array);
176
177 spin_lock(&s2_domain->s1_lock);
178 list_add(&domain->s2_link, &s2_domain->s1_domains);
179 spin_unlock(&s2_domain->s1_lock);
180
181 return &domain->domain;
182}