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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012 Regents of the University of California
4 */
5
6#ifndef _ASM_RISCV_PROCESSOR_H
7#define _ASM_RISCV_PROCESSOR_H
8
9#include <linux/const.h>
10#include <linux/cache.h>
11#include <linux/prctl.h>
12
13#include <vdso/processor.h>
14
15#include <asm/ptrace.h>
16
17/*
18 * addr is a hint to the maximum userspace address that mmap should provide, so
19 * this macro needs to return the largest address space available so that
20 * mmap_end < addr, being mmap_end the top of that address space.
21 * See Documentation/arch/riscv/vm-layout.rst for more details.
22 */
23#define arch_get_mmap_end(addr, len, flags) \
24({ \
25 unsigned long mmap_end; \
26 typeof(addr) _addr = (addr); \
27 if ((_addr) == 0 || is_compat_task() || \
28 ((_addr + len) > BIT(VA_BITS - 1))) \
29 mmap_end = STACK_TOP_MAX; \
30 else \
31 mmap_end = (_addr + len); \
32 mmap_end; \
33})
34
35#define arch_get_mmap_base(addr, base) \
36({ \
37 unsigned long mmap_base; \
38 typeof(addr) _addr = (addr); \
39 typeof(base) _base = (base); \
40 unsigned long rnd_gap = DEFAULT_MAP_WINDOW - (_base); \
41 if ((_addr) == 0 || is_compat_task() || \
42 ((_addr + len) > BIT(VA_BITS - 1))) \
43 mmap_base = (_base); \
44 else \
45 mmap_base = (_addr + len) - rnd_gap; \
46 mmap_base; \
47})
48
49#ifdef CONFIG_64BIT
50#define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1))
51#define STACK_TOP_MAX TASK_SIZE_64
52#else
53#define DEFAULT_MAP_WINDOW TASK_SIZE
54#define STACK_TOP_MAX TASK_SIZE
55#endif
56#define STACK_ALIGN 16
57
58#define STACK_TOP DEFAULT_MAP_WINDOW
59
60/*
61 * This decides where the kernel will search for a free chunk of vm
62 * space during mmap's.
63 */
64#ifdef CONFIG_64BIT
65#define TASK_UNMAPPED_BASE PAGE_ALIGN((UL(1) << MMAP_MIN_VA_BITS) / 3)
66#else
67#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
68#endif
69
70#ifndef __ASSEMBLY__
71#include <linux/cpumask.h>
72
73struct task_struct;
74struct pt_regs;
75
76/*
77 * We use a flag to track in-kernel Vector context. Currently the flag has the
78 * following meaning:
79 *
80 * - bit 0: indicates whether the in-kernel Vector context is active. The
81 * activation of this state disables the preemption. On a non-RT kernel, it
82 * also disable bh.
83 * - bits 8: is used for tracking preemptible kernel-mode Vector, when
84 * RISCV_ISA_V_PREEMPTIVE is enabled. Calling kernel_vector_begin() does not
85 * disable the preemption if the thread's kernel_vstate.datap is allocated.
86 * Instead, the kernel set this bit field. Then the trap entry/exit code
87 * knows if we are entering/exiting the context that owns preempt_v.
88 * - 0: the task is not using preempt_v
89 * - 1: the task is actively using preempt_v. But whether does the task own
90 * the preempt_v context is decided by bits in RISCV_V_CTX_DEPTH_MASK.
91 * - bit 16-23 are RISCV_V_CTX_DEPTH_MASK, used by context tracking routine
92 * when preempt_v starts:
93 * - 0: the task is actively using, and own preempt_v context.
94 * - non-zero: the task was using preempt_v, but then took a trap within.
95 * Thus, the task does not own preempt_v. Any use of Vector will have to
96 * save preempt_v, if dirty, and fallback to non-preemptible kernel-mode
97 * Vector.
98 * - bit 30: The in-kernel preempt_v context is saved, and requries to be
99 * restored when returning to the context that owns the preempt_v.
100 * - bit 31: The in-kernel preempt_v context is dirty, as signaled by the
101 * trap entry code. Any context switches out-of current task need to save
102 * it to the task's in-kernel V context. Also, any traps nesting on-top-of
103 * preempt_v requesting to use V needs a save.
104 */
105#define RISCV_V_CTX_DEPTH_MASK 0x00ff0000
106
107#define RISCV_V_CTX_UNIT_DEPTH 0x00010000
108#define RISCV_KERNEL_MODE_V 0x00000001
109#define RISCV_PREEMPT_V 0x00000100
110#define RISCV_PREEMPT_V_DIRTY 0x80000000
111#define RISCV_PREEMPT_V_NEED_RESTORE 0x40000000
112
113/* CPU-specific state of a task */
114struct thread_struct {
115 /* Callee-saved registers */
116 unsigned long ra;
117 unsigned long sp; /* Kernel mode stack */
118 unsigned long s[12]; /* s[0]: frame pointer */
119 struct __riscv_d_ext_state fstate;
120 unsigned long bad_cause;
121 u32 riscv_v_flags;
122 u32 vstate_ctrl;
123 struct __riscv_v_ext_state vstate;
124 unsigned long align_ctl;
125 struct __riscv_v_ext_state kernel_vstate;
126#ifdef CONFIG_SMP
127 /* Flush the icache on migration */
128 bool force_icache_flush;
129 /* A forced icache flush is not needed if migrating to the previous cpu. */
130 unsigned int prev_cpu;
131#endif
132};
133
134/* Whitelist the fstate from the task_struct for hardened usercopy */
135static inline void arch_thread_struct_whitelist(unsigned long *offset,
136 unsigned long *size)
137{
138 *offset = offsetof(struct thread_struct, fstate);
139 *size = sizeof_field(struct thread_struct, fstate);
140}
141
142#define INIT_THREAD { \
143 .sp = sizeof(init_stack) + (long)&init_stack, \
144 .align_ctl = PR_UNALIGN_NOPRINT, \
145}
146
147#define task_pt_regs(tsk) \
148 ((struct pt_regs *)(task_stack_page(tsk) + THREAD_SIZE \
149 - ALIGN(sizeof(struct pt_regs), STACK_ALIGN)))
150
151#define KSTK_EIP(tsk) (task_pt_regs(tsk)->epc)
152#define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp)
153
154
155/* Do necessary setup to start up a newly executed thread. */
156extern void start_thread(struct pt_regs *regs,
157 unsigned long pc, unsigned long sp);
158
159extern unsigned long __get_wchan(struct task_struct *p);
160
161
162static inline void wait_for_interrupt(void)
163{
164 __asm__ __volatile__ ("wfi");
165}
166
167extern phys_addr_t dma32_phys_limit;
168
169struct device_node;
170int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);
171int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid);
172int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
173
174extern void riscv_fill_hwcap(void);
175extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
176
177extern unsigned long signal_minsigstksz __ro_after_init;
178
179#ifdef CONFIG_RISCV_ISA_V
180/* Userspace interface for PR_RISCV_V_{SET,GET}_VS prctl()s: */
181#define RISCV_V_SET_CONTROL(arg) riscv_v_vstate_ctrl_set_current(arg)
182#define RISCV_V_GET_CONTROL() riscv_v_vstate_ctrl_get_current()
183extern long riscv_v_vstate_ctrl_set_current(unsigned long arg);
184extern long riscv_v_vstate_ctrl_get_current(void);
185#endif /* CONFIG_RISCV_ISA_V */
186
187extern int get_unalign_ctl(struct task_struct *tsk, unsigned long addr);
188extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
189
190#define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr))
191#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
192
193#define RISCV_SET_ICACHE_FLUSH_CTX(arg1, arg2) riscv_set_icache_flush_ctx(arg1, arg2)
194extern int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long per_thread);
195
196#endif /* __ASSEMBLY__ */
197
198#endif /* _ASM_RISCV_PROCESSOR_H */