tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

kernel / drivers / phy / qualcomm / phy-qcom-qmp-pcie.c
at v6.10-rc7 4128 lines 173 kB view raw
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk.h> 7#include <linux/clk-provider.h> 8#include <linux/delay.h> 9#include <linux/err.h> 10#include <linux/io.h> 11#include <linux/iopoll.h> 12#include <linux/kernel.h> 13#include <linux/mfd/syscon.h> 14#include <linux/module.h> 15#include <linux/of.h> 16#include <linux/of_address.h> 17#include <linux/phy/pcie.h> 18#include <linux/phy/phy.h> 19#include <linux/platform_device.h> 20#include <linux/regmap.h> 21#include <linux/regulator/consumer.h> 22#include <linux/reset.h> 23#include <linux/slab.h> 24 25#include <dt-bindings/phy/phy-qcom-qmp.h> 26 27#include "phy-qcom-qmp-common.h" 28 29#include "phy-qcom-qmp.h" 30#include "phy-qcom-qmp-pcs-misc-v3.h" 31#include "phy-qcom-qmp-pcs-pcie-v4.h" 32#include "phy-qcom-qmp-pcs-pcie-v4_20.h" 33#include "phy-qcom-qmp-pcs-pcie-v5.h" 34#include "phy-qcom-qmp-pcs-pcie-v5_20.h" 35#include "phy-qcom-qmp-pcs-pcie-v6.h" 36#include "phy-qcom-qmp-pcs-pcie-v6_20.h" 37#include "phy-qcom-qmp-pcie-qhp.h" 38 39#define PHY_INIT_COMPLETE_TIMEOUT 10000 40 41/* set of registers with offsets different per-PHY */ 42enum qphy_reg_layout { 43 /* PCS registers */ 44 QPHY_SW_RESET, 45 QPHY_START_CTRL, 46 QPHY_PCS_STATUS, 47 QPHY_PCS_POWER_DOWN_CONTROL, 48 /* Keep last to ensure regs_layout arrays are properly initialized */ 49 QPHY_LAYOUT_SIZE 50}; 51 52static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { 53 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, 54 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, 55 [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS, 56 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, 57}; 58 59static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { 60 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 61 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 62 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 63 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 64}; 65 66static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 67 [QPHY_SW_RESET] = 0x00, 68 [QPHY_START_CTRL] = 0x08, 69 [QPHY_PCS_STATUS] = 0x2ac, 70 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 71}; 72 73static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { 74 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 75 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 76 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 77 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 78}; 79 80static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 81 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 82 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 83 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 84 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 85}; 86 87static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { 88 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 89 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 90 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 91 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 92}; 93 94static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 95 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 96 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 97 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 98 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 99 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 100 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 101 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 102 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 103 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 104 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 105 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 106 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 107 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 108 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 109 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 110 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 111 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 112 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 113 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 114 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 137}; 138 139static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 140 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 141 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 142 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 143 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 144}; 145 146static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 147 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 148 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 149 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 150 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 151 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 152 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 153 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 154 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 155 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 156 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 157 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 158 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 159 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 160 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 161}; 162 163static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 164 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 165 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 166 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 167 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 168 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 169 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 170 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 171 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 172 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 173 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 174}; 175 176static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 177 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 178 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 179 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 180 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 181 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 182 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 183 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 184 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 185 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 186 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 187 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 188 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 189 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 190 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 191 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 192 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 193 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 194 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 195 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 196 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 197 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 198 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 199 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 200 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 201 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 202 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 203 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 204 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 205 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 206 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 207 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 208 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 209 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 210 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 211 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 212 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 213 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 214 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 215 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 216 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 217 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 218 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 219 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 220 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 221 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 222 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 223}; 224 225static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 226 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 227 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 228 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 229}; 230 231static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 232 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 233 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 234 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 235 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 236 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 237 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 238 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 239 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 240 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 241 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 242 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 243 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 244 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 245 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 246 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 247 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 248 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 249 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 262}; 263 264static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 265 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 266 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 267 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 268 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 269 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 270 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 271 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 272}; 273 274static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 275 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 276 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 277 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 278 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 279 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 280 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 281 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 282 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 283 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 284}; 285 286static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 287 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 288 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 289 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 290 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 291 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 292 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 293 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 294 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 295 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 296 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 297 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 298 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 299 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 300 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 301 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 302 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 303 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 304 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 305 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 306 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 307 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 308 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 309 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 310 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 311 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 312 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 313 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 314 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 315 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 316 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 317 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 318 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 319 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 320 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 321 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 322 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 323 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 324 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 325 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 326 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 327}; 328 329static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 330 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 331 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 332 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 333 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 334 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 335 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 336}; 337 338static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 339 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 340 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 341 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 342 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 343 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 344 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 345 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 346}; 347 348static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 349 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 350 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 351 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 352 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 353 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 354 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 355 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 356 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 357 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 358 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 359 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 360}; 361 362static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 363 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 364 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 365 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 366 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 367 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 368 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 369 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 370 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 371 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 372 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 373 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 374 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 375 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 376 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 377 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 378 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 379 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 380 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 381 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 382 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 383 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 384 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 385 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 386 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 387 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 388 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 389 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 390 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 391 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 392 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 393 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 394 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 395 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 396 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 397 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 398 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 399 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 400 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 401 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 402 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 403 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 404 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 405 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 406 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 407 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 408 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 409 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 410 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 411 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 412 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 413 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 414 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 415 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 416 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 417 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 418 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 419 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 420}; 421 422static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 423 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 424 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 425 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 426 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 427}; 428 429static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 430 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 431 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 432 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 433 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 434 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 435 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 436 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 437 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 438 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 439 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 440 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 441 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 442 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 443 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 444 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 445 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 446 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 447 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 460}; 461 462static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 463 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 464 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 465 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 466 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 467 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 468 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 469 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 470 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 471 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 472 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 473 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 474}; 475 476static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { 477 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 478 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 479 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 480 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 481 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 482 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 490}; 491 492static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 493 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 494 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 495 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 496 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 497 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 498 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 499 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 500 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 501 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 502 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 503 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 504 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 505 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 506 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 507 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 535}; 536 537static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 538 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 539 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 540 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 541 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 542}; 543 544static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 545 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 546 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 547 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 548 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 549 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 550 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 551 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 552 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 553 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 554 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 555 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 556 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 557 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 558 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 559 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 560 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 561}; 562 563static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 564 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 565 566 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 567 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 568 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 569 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 570 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 571 572 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 573 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 574 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 575 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 576 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 577 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 578 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 579 580 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 583 584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 585}; 586 587static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 593}; 594 595static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 596 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 597 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 598 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 599 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 600 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 601 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 602 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 603 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 604 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 605 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 606 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 607 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 608 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 609 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 610 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 611 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 612 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 613 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 614 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 615 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 616 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 617 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 618 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 619 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 620 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 621 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 622 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 623 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 624 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 625 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 626 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 627 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 628 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 629 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 630 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 631 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 632 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 633 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 634 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 635 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 636 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 637 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 638 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 639 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 640 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 641}; 642 643static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 644 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 645 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 646 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 647 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 648 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 649 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 650 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 651 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 652 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 653 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 654 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 655 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 656 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 657 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 658 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 659 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 660 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 661 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 662 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 663 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 664 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 665 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 666 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 667 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 668 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 669 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 670 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 671 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 672 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 673 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 674 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 675 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 676 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 677 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 678 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 679 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 680 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 681 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 682 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 683 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 700}; 701 702static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 710}; 711 712static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 713 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 714 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 715 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 716 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 717 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 718 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 719 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 720 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 721 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 722 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 723 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 724 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 725 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 726 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 727 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 728 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 729 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 730 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 731 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 732 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 733 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 734 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 735 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 737 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 755}; 756 757static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 758 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 759 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 760}; 761 762static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 763 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 764 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 765 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 766 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 767 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 768 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 769 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 770 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 771 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 772 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 773 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 774 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 775 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 776 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 777 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 778 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 779 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 780 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 799}; 800 801static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 802 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 803 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 804 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 805 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 806 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 807}; 808 809static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 810 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 811 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 812 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 813 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 814 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 815 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 816 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 817}; 818 819static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = { 820 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 821 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 822 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 823 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 824 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 825 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 826 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 827 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 828 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 829 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 830 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 831 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 832 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 833 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 834 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 835 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 836 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 837 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 838 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 839 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 840 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 841 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 842 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 843 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 844 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 845 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 846 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 847 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 848 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 849 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 850 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 851 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 852 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 853 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 854 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 855 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 856 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9), 857 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 858 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94), 859 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 860 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 861}; 862 863static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 864 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 865}; 866 867static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = { 868 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 869}; 870 871static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = { 872 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 873}; 874 875static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = { 876 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 877 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 878 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 879 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 880 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 881}; 882 883static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = { 884 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 885 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 886 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 887 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 888 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 889 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 890 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 891 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 892 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 893 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 894 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 895 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 896 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 897 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 898 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 899 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 900 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 901 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 902}; 903 904static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = { 905 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 906 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 907 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 908}; 909 910static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 911 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 912 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 913 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 914 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 915}; 916 917static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = { 918 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 919 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 920 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 921 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 922 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 923 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 924}; 925 926static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = { 927 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 928 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 929 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 930 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 931 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 932 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 933 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 934 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 935 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 936 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 937 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 938 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 939 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 940 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 941 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 942 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 943 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 944}; 945 946static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = { 947 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 948 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88), 949 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 950 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f), 951}; 952 953static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 954 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 955 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 956 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 957 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 958}; 959 960static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = { 961 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 962 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 963 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 964 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 965 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 966 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 967 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 968 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 969 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 970 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 971 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 972 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 973 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 974 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 975 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 976 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 977 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 978 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 979 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 980 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 981 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 982 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 983 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 984 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 985 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 986 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 987 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 988 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 989 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 990 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 991 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 992 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), 993 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 994 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 995 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 996 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 997 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 998 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 999 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1000 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1001 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1002 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 1003 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 1004 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 1005 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 1006}; 1007 1008static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 1009 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 1010 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88), 1011 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00), 1012 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f), 1013 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4), 1014 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 1015 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 1016 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 1017 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32), 1018 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 1019 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 1020 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1021 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1022 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1023 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1024 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1025 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1026 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1027 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1028 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1029}; 1030 1031static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = { 1032 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1033 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), 1034 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 1035 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10), 1036 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 1037 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 1038}; 1039 1040static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = { 1041 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 1042 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 1043 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 1044 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 1045 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 1046 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 1047 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00), 1048 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15), 1049 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01), 1050 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01), 1051 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45), 1052 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b), 1053 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 1054 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1055 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 1056 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 1057 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1058 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39), 1059 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), 1060 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), 1061 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 1062 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 1063 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), 1064 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 1065 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 1066 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4), 1067 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4), 1068 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 1069 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 1070 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b), 1071 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 1072 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 1073}; 1074 1075static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = { 1076 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), 1077 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), 1078 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), 1079 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), 1080}; 1081 1082static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1083 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 1084 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), 1085 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), 1086 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), 1087 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), 1088 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), 1089 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), 1090 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), 1091 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), 1092 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f), 1093 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2), 1094 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), 1095}; 1096 1097static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 1098 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1099 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1100 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 1101 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1102 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 1103 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 1104 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 1105 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 1106 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1107 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1108 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 1109 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 1110 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 1111 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 1112 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 1113 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 1114 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 1115 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 1116 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 1117 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 1118 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 1119 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 1120 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1121 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1122 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1123 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1124 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1125 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1126 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1127 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1128 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1129 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1130 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1131 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1132 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1133 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1134 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1135 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1136 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1137 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1138 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1139}; 1140 1141static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 1142 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 1143}; 1144 1145static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 1146 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1147 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 1148 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1149}; 1150 1151static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 1152 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1153 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1154 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 1155 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1156 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1157 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 1158 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 1159 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 1160 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1161 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1162 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1163 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1164 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 1165 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1166 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1167 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 1168 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1169 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1170 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1171 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1172 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 1173 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1174 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1175 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1176 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1177 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1178 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1179 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1180 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 1181 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1182}; 1183 1184static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 1185 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 1186 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 1187 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1188 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 1189 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 1190 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 1191}; 1192 1193static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 1194 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1195 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 1196 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1197}; 1198 1199static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 1200 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1201 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 1202}; 1203 1204static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 1205 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1206 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1207 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1208 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 1209 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1210 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1211 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1212}; 1213 1214static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1215 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1216 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 1217}; 1218 1219static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 1220 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 1221}; 1222 1223static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 1224 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 1225 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 1226 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 1227 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1228}; 1229 1230static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 1231 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 1232 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 1233}; 1234 1235static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1236 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 1237 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1238}; 1239 1240static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 1241 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 1242 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1243 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 1244 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 1245 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1246 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1247 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1248 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1249 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1250 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1251 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1252 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1253 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1254 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1255}; 1256 1257static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = { 1258 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1259 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1260 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1261 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce), 1262 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b), 1263 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1264 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1265 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1266 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a), 1267 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10), 1268 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1269 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1270 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1271 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1272 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1273 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1274 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1275 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04), 1276 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d), 1277 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a), 1278 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a), 1279 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3), 1280 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0), 1281 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05), 1282 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), 1283 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), 1284 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), 1285 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1286 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1287 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1288 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8), 1289 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20), 1290}; 1291 1292static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { 1293 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 1294 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 1295 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 1296 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 1297 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 1298 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 1299 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 1300 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 1301 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 1302 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 1303 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 1304 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 1305 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 1306 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 1307 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1308 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1309 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1310 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1311 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1312 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1313 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1314 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1315 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1316 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1317 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1318}; 1319 1320static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1321 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1322 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1323 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1324 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1325 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1326}; 1327 1328static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1329 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1330 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1331 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1332 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1333 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1334 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1335 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1336 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1337 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1338 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1339 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1340 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1341 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1342 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1343 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1344 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1345 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1346 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1347 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1348 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1349 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1350 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1351 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1352 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1353 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1354}; 1355 1356static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1357 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1358 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1359 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1360 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1361}; 1362 1363static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1364 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1365 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1366 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1367 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1368 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1369}; 1370 1371static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = { 1372 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1373 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1374}; 1375 1376static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = { 1377 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1378 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1379}; 1380 1381static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = { 1382 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1383 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1384 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1385 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1386 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1387 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1388 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1389 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1390 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1391 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1392 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1393 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1394 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1395 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1396 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1397 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1398 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1399 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1400 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1401 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1402 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1403 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1404 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1405 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1406 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1407 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1408 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1409 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1410 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1411 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1412 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1413 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1414 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00), 1415 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1416}; 1417 1418static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = { 1419 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1420 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1421 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00), 1422 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00), 1423 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00), 1424 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1425 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1426 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12), 1427}; 1428 1429static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = { 1430 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1431 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06), 1432 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06), 1433 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e), 1434 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e), 1435 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1436 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1437 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02), 1438 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d), 1439 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44), 1440 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00), 1441 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 1442 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1443 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74), 1444 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 1445 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c), 1446 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03), 1447 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 1448 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04), 1449 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1450 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1451 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1452 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64), 1453 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1454 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1455 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1456 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c), 1457 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1458 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1459 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1460 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1461 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1462 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1463 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1464 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1465 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1466 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1467 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1468 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1469 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1470 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1471 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1472 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1473 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00), 1474 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1475 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1476 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1477 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1478 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac), 1479 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1480 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1481 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07), 1482 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1483 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 1484 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5), 1485 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee), 1486 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1487 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1488 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1489 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1490 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1491 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28), 1492 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1493}; 1494 1495static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = { 1496 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 1497 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa), 1498 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d), 1499 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 1500 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 1501}; 1502 1503static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = { 1504 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1505 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1506 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1507 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d), 1508 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1509 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1510 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1511 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1512}; 1513 1514static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = { 1515 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1516 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1517 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1518 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1519 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1520 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1521 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1522 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1523 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1524 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1525 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1526 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1527 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1528 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1529 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1530 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1531 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1532 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1533 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1534 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1535 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1536 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1537 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1538 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1539 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1540 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1541 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1542 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1543 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1544 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1545 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1546 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1547 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1548 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1549 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1550 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1551 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1552 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1553 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1554 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1555 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1556}; 1557 1558static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 1559 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1560}; 1561 1562static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 1563 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1564 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1565 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1566 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1567 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 1568}; 1569 1570static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = { 1571 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1572 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1573 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1574 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1575 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1576 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1577 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1578 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1579 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1580 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1581 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1582 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1583 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1584 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1585}; 1586 1587static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = { 1588 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1589 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1590 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 1591 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1592 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1593 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 1594 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1595 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1596}; 1597 1598static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = { 1599 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1600 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1601 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1602}; 1603 1604static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1605 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1606 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1607 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1608 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1609}; 1610 1611static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = { 1612 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1613 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1614 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1615 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1616 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1617}; 1618 1619static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = { 1620 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1621 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1622 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1623 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1624}; 1625 1626static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = { 1627 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 1628 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 1629 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1630}; 1631 1632static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = { 1633 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 1634 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 1635 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 1636 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1637 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1638 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1639}; 1640 1641static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = { 1642 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f), 1643}; 1644 1645static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 1646 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1647 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1648 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1649 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1650 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1651 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1652 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1653 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1654 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1655 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1656 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1657 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1658 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1659}; 1660 1661static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { 1662 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1663 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1664 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1665 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1666 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1667 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1668 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1669 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1670 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1671 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1672 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1673 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1674 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1675 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1676 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1677 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1678 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1679 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1680 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1681 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 1682 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1683 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1684 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1685 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1686 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 1687 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1688 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1689 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 1690}; 1691 1692static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 1693 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1694 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1695 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1696 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1697}; 1698 1699static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 1700 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1701 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1702 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1703 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1704 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1705 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1706 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1707 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1708 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 1709 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1710 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1711 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 1712 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1713 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 1714 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 1715 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 1716 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1717 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1718 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1719 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1720 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1721 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1722 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1723 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1724 1725 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1726 1727 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1728 1729 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1730 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1731 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1732 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1733 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1734 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1735 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1736 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1737 1738 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1739 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1740 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1741 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1742 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1743 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1744 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1745 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1746 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1747}; 1748 1749static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 1750 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 1751 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 1752 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 1753 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99), 1754}; 1755 1756static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1757 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1758 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1759 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1760 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1761}; 1762 1763static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 1764 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1765 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1766 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00), 1767}; 1768 1769static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { 1770 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1771 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1772 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1773 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1774 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1775 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1776 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1777 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1778 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1779 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1780 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1781 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1782 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1783 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1784 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1785 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1786 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1787 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1788 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1789 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1790}; 1791 1792static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { 1793 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1794}; 1795 1796static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = { 1797 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1798 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1799 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1800 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 1801 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1802 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93), 1803 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 1804 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 1805 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 1806 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 1807 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 1808 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 1809 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1810 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1811 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1812 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1813 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 1814 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1815 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 1816 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 1817 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 1818 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 1819 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 1820 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1821 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34), 1822 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 1823 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 1824 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1825 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 1826 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 1827 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 1828 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1829 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1830 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1831 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1832 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 1833 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), 1834 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1835}; 1836 1837static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = { 1838 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15), 1839 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 1840 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02), 1841 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 1842 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18), 1843}; 1844 1845static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = { 1846 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1847 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11), 1848 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), 1849 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf), 1850 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7), 1851 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea), 1852 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), 1853 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 1854 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 1855 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a), 1856 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89), 1857 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 1858 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94), 1859 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), 1860 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), 1861 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), 1862 QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00), 1863 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), 1864 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), 1865 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 1866 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 1867 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 1868 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c), 1869 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 1870 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 1871}; 1872 1873static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = { 1874 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05), 1875 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77), 1876 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b), 1877 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f), 1878 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c), 1879}; 1880 1881static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1882 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e), 1883 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27), 1884 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 1885 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1886 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1887 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1888}; 1889 1890static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = { 1891 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 1892 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1893 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 1894 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1895 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1896 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1897 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 1898 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 1899 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 1900 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 1901 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 1902 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 1903 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 1904 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 1905 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1906 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1907 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1908 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1909 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1910 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 1911 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 1912 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1913 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 1914 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 1915 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1916 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1917 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1918 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1919 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1920 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1921 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 1922 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), 1923 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 1924 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 1925 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1926 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 1927 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 1928 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1929 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1930 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1931 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1932 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 1933 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 1934 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 1935 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 1936}; 1937 1938static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 1939 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 1940 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00), 1941 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), 1942 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), 1943 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), 1944 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 1945 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 1946 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 1947 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38), 1948 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 1949 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 1950 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1951 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1952 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1953 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1954 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1955 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1956 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1957 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1958 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1959 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), 1960}; 1961 1962static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = { 1963 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1964 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), 1965 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 1966 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00), 1967 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 1968 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 1969}; 1970 1971static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = { 1972 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 1973 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 1974 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 1975 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 1976 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 1977 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 1978 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1979 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 1980 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), 1981 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1982 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 1983 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1984 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 1985 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 1986 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 1987 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 1988 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), 1989 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), 1990 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 1991 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 1992 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), 1993 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 1994 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 1995 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb), 1996 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb), 1997 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0), 1998 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 1999 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78), 2000 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 2001 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 2002 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), 2003}; 2004 2005static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = { 2006 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 2007 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), 2008 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), 2009 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), 2010 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), 2011 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), 2012 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), 2013}; 2014 2015static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 2016 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 2017 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), 2018 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), 2019 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), 2020 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), 2021 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), 2022 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), 2023 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), 2024 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), 2025 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), 2026 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), 2027 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f), 2028 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2), 2029 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), 2030}; 2031 2032static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = { 2033 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a), 2034 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 2035 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 2036 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 2037 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82), 2038 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 2039 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 2040 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 2041 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2042 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 2043 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 2044 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2045 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3), 2046 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3), 2047 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00), 2048 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 2049 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06), 2050 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 2051 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 2052 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23), 2053 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b), 2054 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 2055 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 2056 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43), 2057 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 2058 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 2059}; 2060 2061static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = { 2062 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 2063 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2064 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 2065 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 2066 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2067 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 2068 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2069 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 2070 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 2071 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 2072 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 2073 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 2074 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2075 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 2076}; 2077 2078static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl[] = { 2079 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 2080 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2081 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2082 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2083 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2084 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 2085 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 2086 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2087 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2088 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2089 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2090 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2091 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2092 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 2094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2095 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 2100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 2104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 2105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 2106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 2107}; 2108 2109static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = { 2110 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 2111 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2112 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9a), 2113 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), 2114 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92), 2115 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), 2116 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), 2117 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x99), 2118 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 2119 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a), 2120 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb), 2121 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92), 2122 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec), 2123 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), 2124 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), 2125 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 2126 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3), 2127 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8), 2128 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec), 2129 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6), 2130 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83), 2131 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5), 2132 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e), 2133 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 2134 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 2135 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 2136 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), 2137 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2138 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2139 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2140 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2141 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2142 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2143 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2144 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2145 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2146 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 2147 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 2148 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), 2149 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), 2150 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), 2151 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08), 2152 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2153 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), 2154 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 2155 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 2156 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05), 2157 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 2158 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 2159}; 2160 2161static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_tx_tbl[] = { 2162 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 2163 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 2164 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 2165 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 2166 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x0f), 2167}; 2168 2169static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_misc_tbl[] = { 2170 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 2171 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 2172 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 2173 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 2174}; 2175 2176static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = { 2177 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 2178 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2179 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2180}; 2181 2182static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl[] = { 2183 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 2184 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 2185 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 2186 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 2187 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 2188 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66), 2189}; 2190 2191static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = { 2192 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 2193 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 2194 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), 2195 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2196 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 2197 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05), 2198 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 2199 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2200 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), 2201 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 2202 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2203 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2204 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2205 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2206 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2207 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2208 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2209 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2210 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2211 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 2212 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x99), 2213 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), 2214 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92), 2215 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), 2216 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), 2217 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00), 2218 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20), 2219 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a), 2220 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6), 2221 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92), 2222 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0), 2223 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), 2224 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), 2225 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 2226 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3), 2227 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6), 2228 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xee), 2229 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd2), 2230 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83), 2231 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf9), 2232 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x3d), 2233 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 2234 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 2235 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 2236 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), 2237 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), 2238 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 2239 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), 2240 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08), 2241}; 2242 2243static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl[] = { 2244 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 2245 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 2246 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 2247 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66), 2248}; 2249 2250static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = { 2251 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 2252 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2253 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2254 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2255 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 2256 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 2257 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2258 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 2259 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2260 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 2261 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 2262 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 2263 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 2264 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 2265 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2266 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 2267}; 2268 2269 2270static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[] = { 2271 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 2272 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2273 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2274 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2275 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2276 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 2277 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 2278 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2279 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2280 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2281 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2282 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2283 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 2284 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2285 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2286 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2287 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2288 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2289 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 2290 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2291 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2292 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2293 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 2294 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 2295 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 2296 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 2297}; 2298 2299static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = { 2300 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 2301 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 2302 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 2303 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 2304 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 2305 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 2306 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 2307 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 2308 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 2309 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 2310 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 2311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 2312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 2313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 2315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 2316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 2317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 2318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 2319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 2320}; 2321 2322static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = { 2323 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_MX_CTRL7, 0x00), 2324 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_SW_CTRL7, 0x00), 2325}; 2326 2327struct qmp_pcie_offsets { 2328 u16 serdes; 2329 u16 pcs; 2330 u16 pcs_misc; 2331 u16 tx; 2332 u16 rx; 2333 u16 tx2; 2334 u16 rx2; 2335 u16 ln_shrd; 2336}; 2337 2338struct qmp_phy_cfg_tbls { 2339 const struct qmp_phy_init_tbl *serdes; 2340 int serdes_num; 2341 const struct qmp_phy_init_tbl *tx; 2342 int tx_num; 2343 const struct qmp_phy_init_tbl *rx; 2344 int rx_num; 2345 const struct qmp_phy_init_tbl *pcs; 2346 int pcs_num; 2347 const struct qmp_phy_init_tbl *pcs_misc; 2348 int pcs_misc_num; 2349 const struct qmp_phy_init_tbl *ln_shrd; 2350 int ln_shrd_num; 2351}; 2352 2353/* struct qmp_phy_cfg - per-PHY initialization config */ 2354struct qmp_phy_cfg { 2355 int lanes; 2356 2357 const struct qmp_pcie_offsets *offsets; 2358 2359 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 2360 const struct qmp_phy_cfg_tbls tbls; 2361 /* 2362 * Additional init sequences for PHY blocks, providing additional 2363 * register programming. They are used for providing separate sequences 2364 * for the Root Complex and End Point use cases. 2365 * 2366 * If EP mode is not supported, both tables can be left unset. 2367 */ 2368 const struct qmp_phy_cfg_tbls *tbls_rc; 2369 const struct qmp_phy_cfg_tbls *tbls_ep; 2370 2371 const struct qmp_phy_init_tbl *serdes_4ln_tbl; 2372 int serdes_4ln_num; 2373 2374 /* resets to be requested */ 2375 const char * const *reset_list; 2376 int num_resets; 2377 /* regulators to be requested */ 2378 const char * const *vreg_list; 2379 int num_vregs; 2380 2381 /* array of registers with different offsets */ 2382 const unsigned int *regs; 2383 2384 unsigned int pwrdn_ctrl; 2385 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 2386 unsigned int phy_status; 2387 2388 bool skip_start_delay; 2389 2390 bool has_nocsr_reset; 2391 2392 /* QMP PHY pipe clock interface rate */ 2393 unsigned long pipe_clock_rate; 2394 2395 /* QMP PHY AUX clock interface rate */ 2396 unsigned long aux_clock_rate; 2397}; 2398 2399struct qmp_pcie { 2400 struct device *dev; 2401 2402 const struct qmp_phy_cfg *cfg; 2403 bool tcsr_4ln_config; 2404 2405 void __iomem *serdes; 2406 void __iomem *pcs; 2407 void __iomem *pcs_misc; 2408 void __iomem *tx; 2409 void __iomem *rx; 2410 void __iomem *tx2; 2411 void __iomem *rx2; 2412 void __iomem *ln_shrd; 2413 2414 void __iomem *port_b; 2415 2416 struct clk_bulk_data *clks; 2417 struct clk_bulk_data pipe_clks[2]; 2418 int num_pipe_clks; 2419 2420 struct reset_control_bulk_data *resets; 2421 struct reset_control *nocsr_reset; 2422 struct regulator_bulk_data *vregs; 2423 2424 struct phy *phy; 2425 int mode; 2426 2427 struct clk_fixed_rate pipe_clk_fixed; 2428 struct clk_fixed_rate aux_clk_fixed; 2429}; 2430 2431static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 2432{ 2433 u32 reg; 2434 2435 reg = readl(base + offset); 2436 reg |= val; 2437 writel(reg, base + offset); 2438 2439 /* ensure that above write is through */ 2440 readl(base + offset); 2441} 2442 2443static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 2444{ 2445 u32 reg; 2446 2447 reg = readl(base + offset); 2448 reg &= ~val; 2449 writel(reg, base + offset); 2450 2451 /* ensure that above write is through */ 2452 readl(base + offset); 2453} 2454 2455/* list of clocks required by phy */ 2456static const char * const qmp_pciephy_clk_l[] = { 2457 "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", 2458}; 2459 2460/* list of regulators */ 2461static const char * const qmp_phy_vreg_l[] = { 2462 "vdda-phy", "vdda-pll", 2463}; 2464 2465static const char * const sm8550_qmp_phy_vreg_l[] = { 2466 "vdda-phy", "vdda-pll", "vdda-qref", 2467}; 2468 2469/* list of resets */ 2470static const char * const ipq8074_pciephy_reset_l[] = { 2471 "phy", "common", 2472}; 2473 2474static const char * const sdm845_pciephy_reset_l[] = { 2475 "phy", 2476}; 2477 2478static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = { 2479 .serdes = 0, 2480 .pcs = 0x1800, 2481 .tx = 0x0800, 2482 /* no .rx for QHP */ 2483}; 2484 2485static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = { 2486 .serdes = 0, 2487 .pcs = 0x0800, 2488 .tx = 0x0200, 2489 .rx = 0x0400, 2490}; 2491 2492static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = { 2493 .serdes = 0, 2494 .pcs = 0x0800, 2495 .pcs_misc = 0x0600, 2496 .tx = 0x0200, 2497 .rx = 0x0400, 2498}; 2499 2500static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = { 2501 .serdes = 0, 2502 .pcs = 0x0800, 2503 .pcs_misc = 0x0c00, 2504 .tx = 0x0200, 2505 .rx = 0x0400, 2506}; 2507 2508static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = { 2509 .serdes = 0, 2510 .pcs = 0x0a00, 2511 .pcs_misc = 0x0e00, 2512 .tx = 0x0200, 2513 .rx = 0x0400, 2514 .tx2 = 0x0600, 2515 .rx2 = 0x0800, 2516}; 2517 2518static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = { 2519 .serdes = 0x1000, 2520 .pcs = 0x1200, 2521 .pcs_misc = 0x1600, 2522 .tx = 0x0000, 2523 .rx = 0x0200, 2524 .tx2 = 0x0800, 2525 .rx2 = 0x0a00, 2526}; 2527 2528static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { 2529 .serdes = 0, 2530 .pcs = 0x0200, 2531 .pcs_misc = 0x0600, 2532 .tx = 0x0e00, 2533 .rx = 0x1000, 2534 .tx2 = 0x1600, 2535 .rx2 = 0x1800, 2536}; 2537 2538static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = { 2539 .serdes = 0x1000, 2540 .pcs = 0x1200, 2541 .pcs_misc = 0x1400, 2542 .tx = 0x0000, 2543 .rx = 0x0200, 2544 .tx2 = 0x0800, 2545 .rx2 = 0x0a00, 2546}; 2547 2548static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = { 2549 .serdes = 0x2000, 2550 .pcs = 0x2200, 2551 .pcs_misc = 0x2400, 2552 .tx = 0x0, 2553 .rx = 0x0200, 2554 .tx2 = 0x3800, 2555 .rx2 = 0x3a00, 2556}; 2557 2558static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = { 2559 .serdes = 0x1000, 2560 .pcs = 0x1200, 2561 .pcs_misc = 0x1400, 2562 .tx = 0x0000, 2563 .rx = 0x0200, 2564 .tx2 = 0x0800, 2565 .rx2 = 0x0a00, 2566 .ln_shrd = 0x0e00, 2567}; 2568 2569static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 2570 .lanes = 1, 2571 2572 .offsets = &qmp_pcie_offsets_v2, 2573 2574 .tbls = { 2575 .serdes = ipq8074_pcie_serdes_tbl, 2576 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 2577 .tx = ipq8074_pcie_tx_tbl, 2578 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 2579 .rx = ipq8074_pcie_rx_tbl, 2580 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 2581 .pcs = ipq8074_pcie_pcs_tbl, 2582 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 2583 }, 2584 .reset_list = ipq8074_pciephy_reset_l, 2585 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 2586 .vreg_list = NULL, 2587 .num_vregs = 0, 2588 .regs = pciephy_v2_regs_layout, 2589 2590 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2591 .phy_status = PHYSTATUS, 2592}; 2593 2594static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 2595 .lanes = 1, 2596 2597 .offsets = &qmp_pcie_offsets_v4x1, 2598 2599 .tbls = { 2600 .serdes = ipq8074_pcie_gen3_serdes_tbl, 2601 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 2602 .tx = ipq8074_pcie_gen3_tx_tbl, 2603 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 2604 .rx = ipq8074_pcie_gen3_rx_tbl, 2605 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 2606 .pcs = ipq8074_pcie_gen3_pcs_tbl, 2607 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 2608 .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl, 2609 .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl), 2610 }, 2611 .reset_list = ipq8074_pciephy_reset_l, 2612 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 2613 .vreg_list = NULL, 2614 .num_vregs = 0, 2615 .regs = pciephy_v4_regs_layout, 2616 2617 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2618 .phy_status = PHYSTATUS, 2619 2620 .pipe_clock_rate = 250000000, 2621}; 2622 2623static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 2624 .lanes = 1, 2625 2626 .offsets = &qmp_pcie_offsets_v4x1, 2627 2628 .tbls = { 2629 .serdes = ipq6018_pcie_serdes_tbl, 2630 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 2631 .tx = ipq6018_pcie_tx_tbl, 2632 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 2633 .rx = ipq6018_pcie_rx_tbl, 2634 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 2635 .pcs = ipq6018_pcie_pcs_tbl, 2636 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 2637 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 2638 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 2639 }, 2640 .reset_list = ipq8074_pciephy_reset_l, 2641 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 2642 .vreg_list = NULL, 2643 .num_vregs = 0, 2644 .regs = pciephy_v4_regs_layout, 2645 2646 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2647 .phy_status = PHYSTATUS, 2648}; 2649 2650static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 2651 .lanes = 1, 2652 2653 .offsets = &qmp_pcie_offsets_v3, 2654 2655 .tbls = { 2656 .serdes = sdm845_qmp_pcie_serdes_tbl, 2657 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 2658 .tx = sdm845_qmp_pcie_tx_tbl, 2659 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 2660 .rx = sdm845_qmp_pcie_rx_tbl, 2661 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 2662 .pcs = sdm845_qmp_pcie_pcs_tbl, 2663 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 2664 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 2665 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 2666 }, 2667 .reset_list = sdm845_pciephy_reset_l, 2668 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2669 .vreg_list = qmp_phy_vreg_l, 2670 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2671 .regs = pciephy_v3_regs_layout, 2672 2673 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2674 .phy_status = PHYSTATUS, 2675}; 2676 2677static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 2678 .lanes = 1, 2679 2680 .offsets = &qmp_pcie_offsets_qhp, 2681 2682 .tbls = { 2683 .serdes = sdm845_qhp_pcie_serdes_tbl, 2684 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 2685 .tx = sdm845_qhp_pcie_tx_tbl, 2686 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 2687 .pcs = sdm845_qhp_pcie_pcs_tbl, 2688 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 2689 }, 2690 .reset_list = sdm845_pciephy_reset_l, 2691 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2692 .vreg_list = qmp_phy_vreg_l, 2693 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2694 .regs = sdm845_qhp_pciephy_regs_layout, 2695 2696 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2697 .phy_status = PHYSTATUS, 2698}; 2699 2700static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 2701 .lanes = 1, 2702 2703 .offsets = &qmp_pcie_offsets_v4x1, 2704 2705 .tbls = { 2706 .serdes = sm8250_qmp_pcie_serdes_tbl, 2707 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 2708 .tx = sm8250_qmp_pcie_tx_tbl, 2709 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 2710 .rx = sm8250_qmp_pcie_rx_tbl, 2711 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 2712 .pcs = sm8250_qmp_pcie_pcs_tbl, 2713 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 2714 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 2715 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 2716 }, 2717 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2718 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 2719 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 2720 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 2721 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 2722 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 2723 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 2724 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 2725 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 2726 }, 2727 .reset_list = sdm845_pciephy_reset_l, 2728 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2729 .vreg_list = qmp_phy_vreg_l, 2730 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2731 .regs = pciephy_v4_regs_layout, 2732 2733 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2734 .phy_status = PHYSTATUS, 2735}; 2736 2737static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 2738 .lanes = 2, 2739 2740 .offsets = &qmp_pcie_offsets_v4x2, 2741 2742 .tbls = { 2743 .serdes = sm8250_qmp_pcie_serdes_tbl, 2744 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 2745 .tx = sm8250_qmp_pcie_tx_tbl, 2746 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 2747 .rx = sm8250_qmp_pcie_rx_tbl, 2748 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 2749 .pcs = sm8250_qmp_pcie_pcs_tbl, 2750 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 2751 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 2752 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 2753 }, 2754 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2755 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 2756 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 2757 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 2758 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 2759 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 2760 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 2761 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 2762 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 2763 }, 2764 .reset_list = sdm845_pciephy_reset_l, 2765 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2766 .vreg_list = qmp_phy_vreg_l, 2767 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2768 .regs = pciephy_v4_regs_layout, 2769 2770 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2771 .phy_status = PHYSTATUS, 2772}; 2773 2774static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 2775 .lanes = 1, 2776 2777 .offsets = &qmp_pcie_offsets_v3, 2778 2779 .tbls = { 2780 .serdes = msm8998_pcie_serdes_tbl, 2781 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 2782 .tx = msm8998_pcie_tx_tbl, 2783 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 2784 .rx = msm8998_pcie_rx_tbl, 2785 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 2786 .pcs = msm8998_pcie_pcs_tbl, 2787 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 2788 }, 2789 .reset_list = ipq8074_pciephy_reset_l, 2790 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 2791 .vreg_list = qmp_phy_vreg_l, 2792 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2793 .regs = pciephy_v3_regs_layout, 2794 2795 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2796 .phy_status = PHYSTATUS, 2797 2798 .skip_start_delay = true, 2799}; 2800 2801static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 2802 .lanes = 2, 2803 2804 .offsets = &qmp_pcie_offsets_v4x2, 2805 2806 .tbls = { 2807 .serdes = sc8180x_qmp_pcie_serdes_tbl, 2808 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 2809 .tx = sc8180x_qmp_pcie_tx_tbl, 2810 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 2811 .rx = sc8180x_qmp_pcie_rx_tbl, 2812 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 2813 .pcs = sc8180x_qmp_pcie_pcs_tbl, 2814 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 2815 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 2816 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 2817 }, 2818 .reset_list = sdm845_pciephy_reset_l, 2819 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2820 .vreg_list = qmp_phy_vreg_l, 2821 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2822 .regs = pciephy_v4_regs_layout, 2823 2824 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2825 .phy_status = PHYSTATUS, 2826}; 2827 2828static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { 2829 .lanes = 1, 2830 2831 .offsets = &qmp_pcie_offsets_v5, 2832 2833 .tbls = { 2834 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 2835 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 2836 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl, 2837 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl), 2838 .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl, 2839 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl), 2840 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl, 2841 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl), 2842 .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl, 2843 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl), 2844 }, 2845 2846 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2847 .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl, 2848 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl), 2849 }, 2850 2851 .reset_list = sdm845_pciephy_reset_l, 2852 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2853 .vreg_list = qmp_phy_vreg_l, 2854 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2855 .regs = pciephy_v5_regs_layout, 2856 2857 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2858 .phy_status = PHYSTATUS, 2859}; 2860 2861static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { 2862 .lanes = 2, 2863 2864 .offsets = &qmp_pcie_offsets_v5, 2865 2866 .tbls = { 2867 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 2868 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 2869 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 2870 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 2871 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 2872 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 2873 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 2874 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 2875 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 2876 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 2877 }, 2878 2879 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2880 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 2881 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 2882 }, 2883 2884 .reset_list = sdm845_pciephy_reset_l, 2885 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2886 .vreg_list = qmp_phy_vreg_l, 2887 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2888 .regs = pciephy_v5_regs_layout, 2889 2890 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2891 .phy_status = PHYSTATUS, 2892}; 2893 2894static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { 2895 .lanes = 4, 2896 2897 .offsets = &qmp_pcie_offsets_v5, 2898 2899 .tbls = { 2900 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 2901 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 2902 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 2903 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 2904 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 2905 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 2906 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 2907 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 2908 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 2909 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 2910 }, 2911 2912 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2913 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 2914 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 2915 }, 2916 2917 .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl, 2918 .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl), 2919 2920 .reset_list = sdm845_pciephy_reset_l, 2921 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2922 .vreg_list = qmp_phy_vreg_l, 2923 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2924 .regs = pciephy_v5_regs_layout, 2925 2926 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2927 .phy_status = PHYSTATUS, 2928}; 2929 2930static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 2931 .lanes = 2, 2932 2933 .offsets = &qmp_pcie_offsets_v4_20, 2934 2935 .tbls = { 2936 .serdes = sdx55_qmp_pcie_serdes_tbl, 2937 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 2938 .tx = sdx55_qmp_pcie_tx_tbl, 2939 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 2940 .rx = sdx55_qmp_pcie_rx_tbl, 2941 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 2942 .pcs = sdx55_qmp_pcie_pcs_tbl, 2943 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 2944 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 2945 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 2946 }, 2947 2948 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2949 .serdes = sdx55_qmp_pcie_rc_serdes_tbl, 2950 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl), 2951 .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl, 2952 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl), 2953 }, 2954 2955 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 2956 .serdes = sdx55_qmp_pcie_ep_serdes_tbl, 2957 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), 2958 .pcs_misc = sdx55_qmp_pcie_ep_pcs_misc_tbl, 2959 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl), 2960 }, 2961 2962 .reset_list = sdm845_pciephy_reset_l, 2963 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2964 .vreg_list = qmp_phy_vreg_l, 2965 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2966 .regs = pciephy_v4_regs_layout, 2967 2968 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2969 .phy_status = PHYSTATUS_4_20, 2970}; 2971 2972static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { 2973 .lanes = 1, 2974 2975 .offsets = &qmp_pcie_offsets_v5, 2976 2977 .tbls = { 2978 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 2979 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 2980 .tx = sm8350_qmp_gen3x1_pcie_tx_tbl, 2981 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl), 2982 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 2983 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 2984 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 2985 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 2986 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 2987 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 2988 }, 2989 2990 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2991 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, 2992 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), 2993 .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl, 2994 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl), 2995 }, 2996 2997 .reset_list = sdm845_pciephy_reset_l, 2998 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2999 .vreg_list = qmp_phy_vreg_l, 3000 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3001 .regs = pciephy_v5_regs_layout, 3002 3003 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3004 .phy_status = PHYSTATUS, 3005}; 3006 3007static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { 3008 .lanes = 2, 3009 3010 .offsets = &qmp_pcie_offsets_v5, 3011 3012 .tbls = { 3013 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 3014 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 3015 .tx = sm8350_qmp_gen3x2_pcie_tx_tbl, 3016 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl), 3017 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 3018 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 3019 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 3020 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 3021 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 3022 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 3023 }, 3024 3025 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3026 .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl, 3027 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl), 3028 .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl, 3029 .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl), 3030 }, 3031 3032 .reset_list = sdm845_pciephy_reset_l, 3033 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3034 .vreg_list = qmp_phy_vreg_l, 3035 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3036 .regs = pciephy_v5_regs_layout, 3037 3038 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3039 .phy_status = PHYSTATUS, 3040}; 3041 3042static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = { 3043 .lanes = 2, 3044 3045 .offsets = &qmp_pcie_offsets_v6_20, 3046 3047 .tbls = { 3048 .serdes = sdx65_qmp_pcie_serdes_tbl, 3049 .serdes_num = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl), 3050 .tx = sdx65_qmp_pcie_tx_tbl, 3051 .tx_num = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl), 3052 .rx = sdx65_qmp_pcie_rx_tbl, 3053 .rx_num = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl), 3054 .pcs = sdx65_qmp_pcie_pcs_tbl, 3055 .pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl), 3056 .pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl, 3057 .pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl), 3058 }, 3059 .reset_list = sdm845_pciephy_reset_l, 3060 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3061 .vreg_list = qmp_phy_vreg_l, 3062 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3063 .regs = pciephy_v6_regs_layout, 3064 3065 .pwrdn_ctrl = SW_PWRDN, 3066 .phy_status = PHYSTATUS_4_20, 3067}; 3068 3069static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 3070 .lanes = 1, 3071 3072 .offsets = &qmp_pcie_offsets_v5, 3073 3074 .tbls = { 3075 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 3076 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 3077 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 3078 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 3079 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 3080 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 3081 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 3082 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 3083 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 3084 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 3085 }, 3086 3087 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3088 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, 3089 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), 3090 .rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl, 3091 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl), 3092 }, 3093 3094 .reset_list = sdm845_pciephy_reset_l, 3095 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3096 .vreg_list = qmp_phy_vreg_l, 3097 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3098 .regs = pciephy_v5_regs_layout, 3099 3100 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3101 .phy_status = PHYSTATUS, 3102}; 3103 3104static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 3105 .lanes = 2, 3106 3107 .offsets = &qmp_pcie_offsets_v5_20, 3108 3109 .tbls = { 3110 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 3111 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 3112 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 3113 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 3114 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 3115 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 3116 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 3117 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 3118 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 3119 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 3120 }, 3121 3122 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3123 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 3124 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 3125 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 3126 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 3127 }, 3128 3129 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 3130 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 3131 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 3132 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 3133 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 3134 }, 3135 3136 .reset_list = sdm845_pciephy_reset_l, 3137 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3138 .vreg_list = qmp_phy_vreg_l, 3139 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3140 .regs = pciephy_v5_regs_layout, 3141 3142 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3143 .phy_status = PHYSTATUS_4_20, 3144 3145 /* 20MHz PHY AUX Clock */ 3146 .aux_clock_rate = 20000000, 3147}; 3148 3149static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = { 3150 .lanes = 2, 3151 3152 .offsets = &qmp_pcie_offsets_v5, 3153 3154 .tbls = { 3155 .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl, 3156 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), 3157 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, 3158 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), 3159 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, 3160 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), 3161 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, 3162 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), 3163 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, 3164 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), 3165 }, 3166 .reset_list = sdm845_pciephy_reset_l, 3167 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3168 .vreg_list = qmp_phy_vreg_l, 3169 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3170 .regs = pciephy_v5_regs_layout, 3171 3172 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3173 .phy_status = PHYSTATUS, 3174}; 3175 3176static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { 3177 .lanes = 2, 3178 3179 .offsets = &qmp_pcie_offsets_v6_20, 3180 3181 .tbls = { 3182 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, 3183 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), 3184 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, 3185 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), 3186 .rx = sm8550_qmp_gen4x2_pcie_rx_tbl, 3187 .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl), 3188 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, 3189 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), 3190 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, 3191 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), 3192 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, 3193 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), 3194 }, 3195 .reset_list = sdm845_pciephy_reset_l, 3196 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3197 .vreg_list = sm8550_qmp_phy_vreg_l, 3198 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 3199 .regs = pciephy_v6_regs_layout, 3200 3201 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3202 .phy_status = PHYSTATUS_4_20, 3203 .has_nocsr_reset = true, 3204 3205 /* 20MHz PHY AUX Clock */ 3206 .aux_clock_rate = 20000000, 3207}; 3208 3209static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { 3210 .lanes = 2, 3211 3212 .offsets = &qmp_pcie_offsets_v6_20, 3213 3214 .tbls = { 3215 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, 3216 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), 3217 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, 3218 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), 3219 .rx = sm8650_qmp_gen4x2_pcie_rx_tbl, 3220 .rx_num = ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl), 3221 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, 3222 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), 3223 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, 3224 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), 3225 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, 3226 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), 3227 }, 3228 .reset_list = sdm845_pciephy_reset_l, 3229 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3230 .vreg_list = sm8550_qmp_phy_vreg_l, 3231 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 3232 .regs = pciephy_v6_regs_layout, 3233 3234 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3235 .phy_status = PHYSTATUS_4_20, 3236 .has_nocsr_reset = true, 3237 3238 /* 20MHz PHY AUX Clock */ 3239 .aux_clock_rate = 20000000, 3240}; 3241 3242static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { 3243 .lanes = 2, 3244 .offsets = &qmp_pcie_offsets_v5_20, 3245 3246 .tbls = { 3247 .serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl, 3248 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl), 3249 .tx = sa8775p_qmp_gen4_pcie_tx_tbl, 3250 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), 3251 .rx = sa8775p_qmp_gen4x2_pcie_rx_alt_tbl, 3252 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rx_alt_tbl), 3253 .pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl, 3254 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl), 3255 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, 3256 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), 3257 }, 3258 3259 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3260 .serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl, 3261 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl), 3262 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, 3263 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), 3264 }, 3265 3266 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 3267 .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl, 3268 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl), 3269 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 3270 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 3271 .pcs = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl, 3272 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl), 3273 }, 3274 3275 .reset_list = sdm845_pciephy_reset_l, 3276 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3277 .vreg_list = qmp_phy_vreg_l, 3278 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3279 .regs = pciephy_v5_regs_layout, 3280 3281 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3282 .phy_status = PHYSTATUS_4_20, 3283}; 3284 3285static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = { 3286 .lanes = 4, 3287 .offsets = &qmp_pcie_offsets_v5_30, 3288 3289 .tbls = { 3290 .serdes = sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl, 3291 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl), 3292 .tx = sa8775p_qmp_gen4_pcie_tx_tbl, 3293 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), 3294 .rx = sa8775p_qmp_gen4x4_pcie_rx_alt_tbl, 3295 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rx_alt_tbl), 3296 .pcs = sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl, 3297 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl), 3298 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, 3299 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), 3300 }, 3301 3302 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3303 .serdes = sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl, 3304 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl), 3305 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, 3306 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), 3307 }, 3308 3309 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 3310 .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl, 3311 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl), 3312 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 3313 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 3314 }, 3315 3316 .reset_list = sdm845_pciephy_reset_l, 3317 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3318 .vreg_list = qmp_phy_vreg_l, 3319 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3320 .regs = pciephy_v5_regs_layout, 3321 3322 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3323 .phy_status = PHYSTATUS_4_20, 3324}; 3325 3326static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { 3327 .lanes = 2, 3328 3329 .offsets = &qmp_pcie_offsets_v6_20, 3330 3331 .tbls = { 3332 .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl, 3333 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl), 3334 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl, 3335 .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl), 3336 .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl, 3337 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl), 3338 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl, 3339 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl), 3340 .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl, 3341 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl), 3342 .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl, 3343 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl), 3344 }, 3345 .reset_list = sdm845_pciephy_reset_l, 3346 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3347 .vreg_list = sm8550_qmp_phy_vreg_l, 3348 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 3349 .regs = pciephy_v6_regs_layout, 3350 3351 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3352 .phy_status = PHYSTATUS_4_20, 3353 .has_nocsr_reset = true, 3354}; 3355 3356static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 3357{ 3358 const struct qmp_phy_cfg *cfg = qmp->cfg; 3359 const struct qmp_pcie_offsets *offs = cfg->offsets; 3360 void __iomem *tx3, *rx3, *tx4, *rx4; 3361 3362 tx3 = qmp->port_b + offs->tx; 3363 rx3 = qmp->port_b + offs->rx; 3364 tx4 = qmp->port_b + offs->tx2; 3365 rx4 = qmp->port_b + offs->rx2; 3366 3367 qmp_configure_lane(tx3, tbls->tx, tbls->tx_num, 1); 3368 qmp_configure_lane(rx3, tbls->rx, tbls->rx_num, 1); 3369 3370 qmp_configure_lane(tx4, tbls->tx, tbls->tx_num, 2); 3371 qmp_configure_lane(rx4, tbls->rx, tbls->rx_num, 2); 3372} 3373 3374static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 3375{ 3376 const struct qmp_phy_cfg *cfg = qmp->cfg; 3377 void __iomem *serdes = qmp->serdes; 3378 void __iomem *tx = qmp->tx; 3379 void __iomem *rx = qmp->rx; 3380 void __iomem *tx2 = qmp->tx2; 3381 void __iomem *rx2 = qmp->rx2; 3382 void __iomem *pcs = qmp->pcs; 3383 void __iomem *pcs_misc = qmp->pcs_misc; 3384 void __iomem *ln_shrd = qmp->ln_shrd; 3385 3386 if (!tbls) 3387 return; 3388 3389 qmp_configure(serdes, tbls->serdes, tbls->serdes_num); 3390 3391 qmp_configure_lane(tx, tbls->tx, tbls->tx_num, 1); 3392 qmp_configure_lane(rx, tbls->rx, tbls->rx_num, 1); 3393 3394 if (cfg->lanes >= 2) { 3395 qmp_configure_lane(tx2, tbls->tx, tbls->tx_num, 2); 3396 qmp_configure_lane(rx2, tbls->rx, tbls->rx_num, 2); 3397 } 3398 3399 qmp_configure(pcs, tbls->pcs, tbls->pcs_num); 3400 qmp_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 3401 3402 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 3403 qmp_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); 3404 qmp_pcie_init_port_b(qmp, tbls); 3405 } 3406 3407 qmp_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); 3408} 3409 3410static int qmp_pcie_init(struct phy *phy) 3411{ 3412 struct qmp_pcie *qmp = phy_get_drvdata(phy); 3413 const struct qmp_phy_cfg *cfg = qmp->cfg; 3414 int ret; 3415 3416 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 3417 if (ret) { 3418 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 3419 return ret; 3420 } 3421 3422 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 3423 if (ret) { 3424 dev_err(qmp->dev, "reset assert failed\n"); 3425 goto err_disable_regulators; 3426 } 3427 3428 ret = reset_control_assert(qmp->nocsr_reset); 3429 if (ret) { 3430 dev_err(qmp->dev, "no-csr reset assert failed\n"); 3431 goto err_assert_reset; 3432 } 3433 3434 usleep_range(200, 300); 3435 3436 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 3437 if (ret) { 3438 dev_err(qmp->dev, "reset deassert failed\n"); 3439 goto err_assert_reset; 3440 } 3441 3442 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); 3443 if (ret) 3444 goto err_assert_reset; 3445 3446 return 0; 3447 3448err_assert_reset: 3449 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 3450err_disable_regulators: 3451 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 3452 3453 return ret; 3454} 3455 3456static int qmp_pcie_exit(struct phy *phy) 3457{ 3458 struct qmp_pcie *qmp = phy_get_drvdata(phy); 3459 const struct qmp_phy_cfg *cfg = qmp->cfg; 3460 3461 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 3462 3463 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); 3464 3465 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 3466 3467 return 0; 3468} 3469 3470static int qmp_pcie_power_on(struct phy *phy) 3471{ 3472 struct qmp_pcie *qmp = phy_get_drvdata(phy); 3473 const struct qmp_phy_cfg *cfg = qmp->cfg; 3474 const struct qmp_phy_cfg_tbls *mode_tbls; 3475 void __iomem *pcs = qmp->pcs; 3476 void __iomem *status; 3477 unsigned int mask, val; 3478 int ret; 3479 3480 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 3481 cfg->pwrdn_ctrl); 3482 3483 if (qmp->mode == PHY_MODE_PCIE_RC) 3484 mode_tbls = cfg->tbls_rc; 3485 else 3486 mode_tbls = cfg->tbls_ep; 3487 3488 qmp_pcie_init_registers(qmp, &cfg->tbls); 3489 qmp_pcie_init_registers(qmp, mode_tbls); 3490 3491 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); 3492 if (ret) 3493 return ret; 3494 3495 ret = reset_control_deassert(qmp->nocsr_reset); 3496 if (ret) { 3497 dev_err(qmp->dev, "no-csr reset deassert failed\n"); 3498 goto err_disable_pipe_clk; 3499 } 3500 3501 /* Pull PHY out of reset state */ 3502 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 3503 3504 /* start SerDes and Phy-Coding-Sublayer */ 3505 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 3506 3507 if (!cfg->skip_start_delay) 3508 usleep_range(1000, 1200); 3509 3510 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 3511 mask = cfg->phy_status; 3512 ret = readl_poll_timeout(status, val, !(val & mask), 200, 3513 PHY_INIT_COMPLETE_TIMEOUT); 3514 if (ret) { 3515 dev_err(qmp->dev, "phy initialization timed-out\n"); 3516 goto err_disable_pipe_clk; 3517 } 3518 3519 return 0; 3520 3521err_disable_pipe_clk: 3522 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 3523 3524 return ret; 3525} 3526 3527static int qmp_pcie_power_off(struct phy *phy) 3528{ 3529 struct qmp_pcie *qmp = phy_get_drvdata(phy); 3530 const struct qmp_phy_cfg *cfg = qmp->cfg; 3531 3532 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 3533 3534 /* PHY reset */ 3535 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 3536 3537 /* stop SerDes and Phy-Coding-Sublayer */ 3538 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 3539 SERDES_START | PCS_START); 3540 3541 /* Put PHY into POWER DOWN state: active low */ 3542 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 3543 cfg->pwrdn_ctrl); 3544 3545 return 0; 3546} 3547 3548static int qmp_pcie_enable(struct phy *phy) 3549{ 3550 int ret; 3551 3552 ret = qmp_pcie_init(phy); 3553 if (ret) 3554 return ret; 3555 3556 ret = qmp_pcie_power_on(phy); 3557 if (ret) 3558 qmp_pcie_exit(phy); 3559 3560 return ret; 3561} 3562 3563static int qmp_pcie_disable(struct phy *phy) 3564{ 3565 int ret; 3566 3567 ret = qmp_pcie_power_off(phy); 3568 if (ret) 3569 return ret; 3570 3571 return qmp_pcie_exit(phy); 3572} 3573 3574static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 3575{ 3576 struct qmp_pcie *qmp = phy_get_drvdata(phy); 3577 3578 switch (submode) { 3579 case PHY_MODE_PCIE_RC: 3580 case PHY_MODE_PCIE_EP: 3581 qmp->mode = submode; 3582 break; 3583 default: 3584 dev_err(&phy->dev, "Unsupported submode %d\n", submode); 3585 return -EINVAL; 3586 } 3587 3588 return 0; 3589} 3590 3591static const struct phy_ops qmp_pcie_phy_ops = { 3592 .power_on = qmp_pcie_enable, 3593 .power_off = qmp_pcie_disable, 3594 .set_mode = qmp_pcie_set_mode, 3595 .owner = THIS_MODULE, 3596}; 3597 3598static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) 3599{ 3600 const struct qmp_phy_cfg *cfg = qmp->cfg; 3601 struct device *dev = qmp->dev; 3602 int num = cfg->num_vregs; 3603 int i; 3604 3605 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 3606 if (!qmp->vregs) 3607 return -ENOMEM; 3608 3609 for (i = 0; i < num; i++) 3610 qmp->vregs[i].supply = cfg->vreg_list[i]; 3611 3612 return devm_regulator_bulk_get(dev, num, qmp->vregs); 3613} 3614 3615static int qmp_pcie_reset_init(struct qmp_pcie *qmp) 3616{ 3617 const struct qmp_phy_cfg *cfg = qmp->cfg; 3618 struct device *dev = qmp->dev; 3619 int i; 3620 int ret; 3621 3622 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 3623 sizeof(*qmp->resets), GFP_KERNEL); 3624 if (!qmp->resets) 3625 return -ENOMEM; 3626 3627 for (i = 0; i < cfg->num_resets; i++) 3628 qmp->resets[i].id = cfg->reset_list[i]; 3629 3630 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 3631 if (ret) 3632 return dev_err_probe(dev, ret, "failed to get resets\n"); 3633 3634 if (cfg->has_nocsr_reset) { 3635 qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr"); 3636 if (IS_ERR(qmp->nocsr_reset)) 3637 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), 3638 "failed to get no-csr reset\n"); 3639 } 3640 3641 return 0; 3642} 3643 3644static int qmp_pcie_clk_init(struct qmp_pcie *qmp) 3645{ 3646 struct device *dev = qmp->dev; 3647 int num = ARRAY_SIZE(qmp_pciephy_clk_l); 3648 int i; 3649 3650 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 3651 if (!qmp->clks) 3652 return -ENOMEM; 3653 3654 for (i = 0; i < num; i++) 3655 qmp->clks[i].id = qmp_pciephy_clk_l[i]; 3656 3657 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 3658} 3659 3660static void phy_clk_release_provider(void *res) 3661{ 3662 of_clk_del_provider(res); 3663} 3664 3665/* 3666 * Register a fixed rate pipe clock. 3667 * 3668 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 3669 * controls it. The <s>_pipe_clk coming out of the GCC is requested 3670 * by the PHY driver for its operations. 3671 * We register the <s>_pipe_clksrc here. The gcc driver takes care 3672 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 3673 * Below picture shows this relationship. 3674 * 3675 * +---------------+ 3676 * | PHY block |<<---------------------------------------+ 3677 * | | | 3678 * | +-------+ | +-----+ | 3679 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 3680 * clk | +-------+ | +-----+ 3681 * +---------------+ 3682 */ 3683static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) 3684{ 3685 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 3686 struct clk_init_data init = { }; 3687 int ret; 3688 3689 ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name); 3690 if (ret) { 3691 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 3692 return ret; 3693 } 3694 3695 init.ops = &clk_fixed_rate_ops; 3696 3697 /* 3698 * Controllers using QMP PHY-s use 125MHz pipe clock interface 3699 * unless other frequency is specified in the PHY config. 3700 */ 3701 if (qmp->cfg->pipe_clock_rate) 3702 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; 3703 else 3704 fixed->fixed_rate = 125000000; 3705 3706 fixed->hw.init = &init; 3707 3708 return devm_clk_hw_register(qmp->dev, &fixed->hw); 3709} 3710 3711/* 3712 * Register a fixed rate PHY aux clock. 3713 * 3714 * The <s>_phy_aux_clksrc generated by PHY goes to the GCC that gate 3715 * controls it. The <s>_phy_aux_clk coming out of the GCC is requested 3716 * by the PHY driver for its operations. 3717 * We register the <s>_phy_aux_clksrc here. The gcc driver takes care 3718 * of assigning this <s>_phy_aux_clksrc as parent to <s>_phy_aux_clk. 3719 * Below picture shows this relationship. 3720 * 3721 * +---------------+ 3722 * | PHY block |<<---------------------------------------------+ 3723 * | | | 3724 * | +-------+ | +-----+ | 3725 * I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+ 3726 * clk | +-------+ | +-----+ 3727 * +---------------+ 3728 */ 3729static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np) 3730{ 3731 struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed; 3732 struct clk_init_data init = { }; 3733 int ret; 3734 3735 ret = of_property_read_string_index(np, "clock-output-names", 1, &init.name); 3736 if (ret) { 3737 dev_err(qmp->dev, "%pOFn: No clock-output-names index 1\n", np); 3738 return ret; 3739 } 3740 3741 init.ops = &clk_fixed_rate_ops; 3742 3743 fixed->fixed_rate = qmp->cfg->aux_clock_rate; 3744 fixed->hw.init = &init; 3745 3746 return devm_clk_hw_register(qmp->dev, &fixed->hw); 3747} 3748 3749static struct clk_hw *qmp_pcie_clk_hw_get(struct of_phandle_args *clkspec, void *data) 3750{ 3751 struct qmp_pcie *qmp = data; 3752 3753 /* Support legacy bindings */ 3754 if (!clkspec->args_count) 3755 return &qmp->pipe_clk_fixed.hw; 3756 3757 switch (clkspec->args[0]) { 3758 case QMP_PCIE_PIPE_CLK: 3759 return &qmp->pipe_clk_fixed.hw; 3760 case QMP_PCIE_PHY_AUX_CLK: 3761 return &qmp->aux_clk_fixed.hw; 3762 } 3763 3764 return ERR_PTR(-EINVAL); 3765} 3766 3767static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np) 3768{ 3769 int ret; 3770 3771 ret = phy_pipe_clk_register(qmp, np); 3772 if (ret) 3773 return ret; 3774 3775 if (qmp->cfg->aux_clock_rate) { 3776 ret = phy_aux_clk_register(qmp, np); 3777 if (ret) 3778 return ret; 3779 3780 ret = of_clk_add_hw_provider(np, qmp_pcie_clk_hw_get, qmp); 3781 if (ret) 3782 return ret; 3783 } else { 3784 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw); 3785 if (ret) 3786 return ret; 3787 } 3788 3789 /* 3790 * Roll a devm action because the clock provider is the child node, but 3791 * the child node is not actually a device. 3792 */ 3793 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 3794} 3795 3796static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np) 3797{ 3798 struct platform_device *pdev = to_platform_device(qmp->dev); 3799 const struct qmp_phy_cfg *cfg = qmp->cfg; 3800 struct device *dev = qmp->dev; 3801 struct clk *clk; 3802 3803 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 3804 if (IS_ERR(qmp->serdes)) 3805 return PTR_ERR(qmp->serdes); 3806 3807 /* 3808 * Get memory resources for the PHY: 3809 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 3810 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 3811 * For single lane PHYs: pcs_misc (optional) -> 3. 3812 */ 3813 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 3814 if (IS_ERR(qmp->tx)) 3815 return PTR_ERR(qmp->tx); 3816 3817 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 3818 qmp->rx = qmp->tx; 3819 else 3820 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 3821 if (IS_ERR(qmp->rx)) 3822 return PTR_ERR(qmp->rx); 3823 3824 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 3825 if (IS_ERR(qmp->pcs)) 3826 return PTR_ERR(qmp->pcs); 3827 3828 if (cfg->lanes >= 2) { 3829 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 3830 if (IS_ERR(qmp->tx2)) 3831 return PTR_ERR(qmp->tx2); 3832 3833 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 3834 if (IS_ERR(qmp->rx2)) 3835 return PTR_ERR(qmp->rx2); 3836 3837 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 3838 } else { 3839 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 3840 } 3841 3842 if (IS_ERR(qmp->pcs_misc) && 3843 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 3844 qmp->pcs_misc = qmp->pcs + 0x400; 3845 3846 if (IS_ERR(qmp->pcs_misc)) { 3847 if (cfg->tbls.pcs_misc || 3848 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || 3849 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { 3850 return PTR_ERR(qmp->pcs_misc); 3851 } 3852 } 3853 3854 clk = devm_get_clk_from_child(dev, np, NULL); 3855 if (IS_ERR(clk)) { 3856 return dev_err_probe(dev, PTR_ERR(clk), 3857 "failed to get pipe clock\n"); 3858 } 3859 3860 qmp->num_pipe_clks = 1; 3861 qmp->pipe_clks[0].id = "pipe"; 3862 qmp->pipe_clks[0].clk = clk; 3863 3864 return 0; 3865} 3866 3867static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp) 3868{ 3869 struct regmap *tcsr; 3870 unsigned int args[2]; 3871 int ret; 3872 3873 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, 3874 "qcom,4ln-config-sel", 3875 ARRAY_SIZE(args), args); 3876 if (IS_ERR(tcsr)) { 3877 ret = PTR_ERR(tcsr); 3878 if (ret == -ENOENT) 3879 return 0; 3880 3881 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); 3882 return ret; 3883 } 3884 3885 ret = regmap_test_bits(tcsr, args[0], BIT(args[1])); 3886 if (ret < 0) { 3887 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); 3888 return ret; 3889 } 3890 3891 qmp->tcsr_4ln_config = ret; 3892 3893 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); 3894 3895 return 0; 3896} 3897 3898static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) 3899{ 3900 struct platform_device *pdev = to_platform_device(qmp->dev); 3901 const struct qmp_phy_cfg *cfg = qmp->cfg; 3902 const struct qmp_pcie_offsets *offs = cfg->offsets; 3903 struct device *dev = qmp->dev; 3904 void __iomem *base; 3905 int ret; 3906 3907 if (!offs) 3908 return -EINVAL; 3909 3910 ret = qmp_pcie_get_4ln_config(qmp); 3911 if (ret) 3912 return ret; 3913 3914 base = devm_platform_ioremap_resource(pdev, 0); 3915 if (IS_ERR(base)) 3916 return PTR_ERR(base); 3917 3918 qmp->serdes = base + offs->serdes; 3919 qmp->pcs = base + offs->pcs; 3920 qmp->pcs_misc = base + offs->pcs_misc; 3921 qmp->tx = base + offs->tx; 3922 qmp->rx = base + offs->rx; 3923 3924 if (cfg->lanes >= 2) { 3925 qmp->tx2 = base + offs->tx2; 3926 qmp->rx2 = base + offs->rx2; 3927 } 3928 3929 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 3930 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); 3931 if (IS_ERR(qmp->port_b)) 3932 return PTR_ERR(qmp->port_b); 3933 } 3934 3935 if (cfg->tbls.ln_shrd) 3936 qmp->ln_shrd = base + offs->ln_shrd; 3937 3938 qmp->num_pipe_clks = 2; 3939 qmp->pipe_clks[0].id = "pipe"; 3940 qmp->pipe_clks[1].id = "pipediv2"; 3941 3942 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); 3943 if (ret) 3944 return ret; 3945 3946 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); 3947 if (ret) 3948 return ret; 3949 3950 return 0; 3951} 3952 3953static int qmp_pcie_probe(struct platform_device *pdev) 3954{ 3955 struct device *dev = &pdev->dev; 3956 struct phy_provider *phy_provider; 3957 struct device_node *np; 3958 struct qmp_pcie *qmp; 3959 int ret; 3960 3961 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 3962 if (!qmp) 3963 return -ENOMEM; 3964 3965 qmp->dev = dev; 3966 3967 qmp->cfg = of_device_get_match_data(dev); 3968 if (!qmp->cfg) 3969 return -EINVAL; 3970 3971 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); 3972 WARN_ON_ONCE(!qmp->cfg->phy_status); 3973 3974 ret = qmp_pcie_clk_init(qmp); 3975 if (ret) 3976 return ret; 3977 3978 ret = qmp_pcie_reset_init(qmp); 3979 if (ret) 3980 return ret; 3981 3982 ret = qmp_pcie_vreg_init(qmp); 3983 if (ret) 3984 return ret; 3985 3986 /* Check for legacy binding with child node. */ 3987 np = of_get_next_available_child(dev->of_node, NULL); 3988 if (np) { 3989 ret = qmp_pcie_parse_dt_legacy(qmp, np); 3990 } else { 3991 np = of_node_get(dev->of_node); 3992 ret = qmp_pcie_parse_dt(qmp); 3993 } 3994 if (ret) 3995 goto err_node_put; 3996 3997 ret = qmp_pcie_register_clocks(qmp, np); 3998 if (ret) 3999 goto err_node_put; 4000 4001 qmp->mode = PHY_MODE_PCIE_RC; 4002 4003 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); 4004 if (IS_ERR(qmp->phy)) { 4005 ret = PTR_ERR(qmp->phy); 4006 dev_err(dev, "failed to create PHY: %d\n", ret); 4007 goto err_node_put; 4008 } 4009 4010 phy_set_drvdata(qmp->phy, qmp); 4011 4012 of_node_put(np); 4013 4014 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 4015 4016 return PTR_ERR_OR_ZERO(phy_provider); 4017 4018err_node_put: 4019 of_node_put(np); 4020 return ret; 4021} 4022 4023static const struct of_device_id qmp_pcie_of_match_table[] = { 4024 { 4025 .compatible = "qcom,ipq6018-qmp-pcie-phy", 4026 .data = &ipq6018_pciephy_cfg, 4027 }, { 4028 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 4029 .data = &ipq8074_pciephy_gen3_cfg, 4030 }, { 4031 .compatible = "qcom,ipq8074-qmp-pcie-phy", 4032 .data = &ipq8074_pciephy_cfg, 4033 }, { 4034 .compatible = "qcom,msm8998-qmp-pcie-phy", 4035 .data = &msm8998_pciephy_cfg, 4036 }, { 4037 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy", 4038 .data = &sa8775p_qmp_gen4x2_pciephy_cfg, 4039 }, { 4040 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy", 4041 .data = &sa8775p_qmp_gen4x4_pciephy_cfg, 4042 }, { 4043 .compatible = "qcom,sc8180x-qmp-pcie-phy", 4044 .data = &sc8180x_pciephy_cfg, 4045 }, { 4046 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy", 4047 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg, 4048 }, { 4049 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy", 4050 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg, 4051 }, { 4052 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy", 4053 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg, 4054 }, { 4055 .compatible = "qcom,sdm845-qhp-pcie-phy", 4056 .data = &sdm845_qhp_pciephy_cfg, 4057 }, { 4058 .compatible = "qcom,sdm845-qmp-pcie-phy", 4059 .data = &sdm845_qmp_pciephy_cfg, 4060 }, { 4061 .compatible = "qcom,sdx55-qmp-pcie-phy", 4062 .data = &sdx55_qmp_pciephy_cfg, 4063 }, { 4064 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy", 4065 .data = &sdx65_qmp_pciephy_cfg, 4066 }, { 4067 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy", 4068 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 4069 }, { 4070 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy", 4071 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 4072 }, { 4073 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 4074 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 4075 }, { 4076 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 4077 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 4078 }, { 4079 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 4080 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 4081 }, { 4082 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy", 4083 .data = &sm8350_qmp_gen3x1_pciephy_cfg, 4084 }, { 4085 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy", 4086 .data = &sm8350_qmp_gen3x2_pciephy_cfg, 4087 }, { 4088 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 4089 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 4090 }, { 4091 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 4092 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 4093 }, { 4094 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy", 4095 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 4096 }, { 4097 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy", 4098 .data = &sm8550_qmp_gen4x2_pciephy_cfg, 4099 }, { 4100 .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy", 4101 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 4102 }, { 4103 .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy", 4104 .data = &sm8650_qmp_gen4x2_pciephy_cfg, 4105 }, { 4106 .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy", 4107 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 4108 }, { 4109 .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy", 4110 .data = &x1e80100_qmp_gen4x2_pciephy_cfg, 4111 }, 4112 { }, 4113}; 4114MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 4115 4116static struct platform_driver qmp_pcie_driver = { 4117 .probe = qmp_pcie_probe, 4118 .driver = { 4119 .name = "qcom-qmp-pcie-phy", 4120 .of_match_table = qmp_pcie_of_match_table, 4121 }, 4122}; 4123 4124module_platform_driver(qmp_pcie_driver); 4125 4126MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 4127MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 4128MODULE_LICENSE("GPL v2");