tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: GPL-2.0
2#
3# For a description of the syntax of this configuration file,
4# see Documentation/kbuild/kconfig-language.rst.
5#
6
7config OPENRISC
8 def_bool y
9 select ARCH_32BIT_OFF_T
10 select ARCH_HAS_DMA_SET_UNCACHED
11 select ARCH_HAS_DMA_CLEAR_UNCACHED
12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
13 select COMMON_CLK
14 select OF
15 select OF_EARLY_FLATTREE
16 select IRQ_DOMAIN
17 select GPIOLIB
18 select HAVE_ARCH_TRACEHOOK
19 select SPARSE_IRQ
20 select GENERIC_IRQ_CHIP
21 select GENERIC_IRQ_PROBE
22 select GENERIC_IRQ_SHOW
23 select GENERIC_PCI_IOMAP
24 select GENERIC_IOREMAP
25 select GENERIC_CPU_DEVICES
26 select HAVE_PCI
27 select HAVE_UID16
28 select HAVE_PAGE_SIZE_8KB
29 select GENERIC_ATOMIC64
30 select GENERIC_CLOCKEVENTS_BROADCAST
31 select GENERIC_SMP_IDLE_THREAD
32 select MODULES_USE_ELF_RELA
33 select HAVE_DEBUG_STACKOVERFLOW
34 select OR1K_PIC
35 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
36 select ARCH_USE_QUEUED_RWLOCKS
37 select OMPIC if SMP
38 select PCI_DOMAINS_GENERIC if PCI
39 select PCI_MSI if PCI
40 select ARCH_WANT_FRAME_POINTERS
41 select GENERIC_IRQ_MULTI_HANDLER
42 select MMU_GATHER_NO_RANGE if MMU
43 select TRACE_IRQFLAGS_SUPPORT
44
45config CPU_BIG_ENDIAN
46 def_bool y
47
48config MMU
49 def_bool y
50
51config GENERIC_HWEIGHT
52 def_bool y
53
54config NO_IOPORT_MAP
55 def_bool y
56
57# For now, use generic checksum functions
58#These can be reimplemented in assembly later if so inclined
59config GENERIC_CSUM
60 def_bool y
61
62config STACKTRACE_SUPPORT
63 def_bool y
64
65config LOCKDEP_SUPPORT
66 def_bool y
67
68menu "Processor type and features"
69
70choice
71 prompt "Subarchitecture"
72 default OR1K_1200
73
74config OR1K_1200
75 bool "OR1200"
76 help
77 Generic OpenRISC 1200 architecture
78
79endchoice
80
81config DCACHE_WRITETHROUGH
82 bool "Have write through data caches"
83 default n
84 help
85 Select this if your implementation features write through data caches.
86 Selecting 'N' here will allow the kernel to force flushing of data
87 caches at relevant times. Most OpenRISC implementations support write-
88 through data caches.
89
90 If unsure say N here
91
92config OPENRISC_BUILTIN_DTB
93 string "Builtin DTB"
94 default ""
95
96menu "Class II Instructions"
97
98config OPENRISC_HAVE_INST_FF1
99 bool "Have instruction l.ff1"
100 default y
101 help
102 Select this if your implementation has the Class II instruction l.ff1
103
104config OPENRISC_HAVE_INST_FL1
105 bool "Have instruction l.fl1"
106 default y
107 help
108 Select this if your implementation has the Class II instruction l.fl1
109
110config OPENRISC_HAVE_INST_MUL
111 bool "Have instruction l.mul for hardware multiply"
112 default y
113 help
114 Select this if your implementation has a hardware multiply instruction
115
116config OPENRISC_HAVE_INST_DIV
117 bool "Have instruction l.div for hardware divide"
118 default y
119 help
120 Select this if your implementation has a hardware divide instruction
121
122config OPENRISC_HAVE_INST_CMOV
123 bool "Have instruction l.cmov for conditional move"
124 default n
125 help
126 This config enables gcc to generate l.cmov instructions when compiling
127 the kernel which in general will improve performance and reduce the
128 binary size.
129
130 Select this if your implementation has support for the Class II
131 l.cmov conistional move instruction.
132
133 Say N if you are unsure.
134
135config OPENRISC_HAVE_INST_ROR
136 bool "Have instruction l.ror for rotate right"
137 default n
138 help
139 This config enables gcc to generate l.ror instructions when compiling
140 the kernel which in general will improve performance and reduce the
141 binary size.
142
143 Select this if your implementation has support for the Class II
144 l.ror rotate right instruction.
145
146 Say N if you are unsure.
147
148config OPENRISC_HAVE_INST_RORI
149 bool "Have instruction l.rori for rotate right with immediate"
150 default n
151 help
152 This config enables gcc to generate l.rori instructions when compiling
153 the kernel which in general will improve performance and reduce the
154 binary size.
155
156 Select this if your implementation has support for the Class II
157 l.rori rotate right with immediate instruction.
158
159 Say N if you are unsure.
160
161config OPENRISC_HAVE_INST_SEXT
162 bool "Have instructions l.ext* for sign extension"
163 default n
164 help
165 This config enables gcc to generate l.ext* instructions when compiling
166 the kernel which in general will improve performance and reduce the
167 binary size.
168
169 Select this if your implementation has support for the Class II
170 l.exths, l.extbs, l.exthz and l.extbz size extend instructions.
171
172 Say N if you are unsure.
173
174endmenu
175
176config NR_CPUS
177 int "Maximum number of CPUs (2-32)"
178 range 2 32
179 depends on SMP
180 default "2"
181
182config SMP
183 bool "Symmetric Multi-Processing support"
184 help
185 This enables support for systems with more than one CPU. If you have
186 a system with only one CPU, say N. If you have a system with more
187 than one CPU, say Y.
188
189 If you don't know what to do here, say N.
190
191config FPU
192 bool "FPU support"
193 default y
194 help
195 Say N here if you want to disable all floating-point related procedures
196 in the kernel and reduce binary size.
197
198 If you don't know what to do here, say Y.
199
200source "kernel/Kconfig.hz"
201
202config OPENRISC_NO_SPR_SR_DSX
203 bool "use SPR_SR_DSX software emulation" if OR1K_1200
204 default y
205 help
206 SPR_SR_DSX bit is status register bit indicating whether
207 the last exception has happened in delay slot.
208
209 OpenRISC architecture makes it optional to have it implemented
210 in hardware and the OR1200 does not have it.
211
212 Say N here if you know that your OpenRISC processor has
213 SPR_SR_DSX bit implemented. Say Y if you are unsure.
214
215config OPENRISC_HAVE_SHADOW_GPRS
216 bool "Support for shadow gpr files" if !SMP
217 default y if SMP
218 help
219 Say Y here if your OpenRISC processor features shadowed
220 register files. They will in such case be used as a
221 scratch reg storage on exception entry.
222
223 On SMP systems, this feature is mandatory.
224 On a unicore system it's safe to say N here if you are unsure.
225
226config CMDLINE
227 string "Default kernel command string"
228 default ""
229 help
230 On some architectures there is currently no way for the boot loader
231 to pass arguments to the kernel. For these architectures, you should
232 supply some command-line options at build time by entering them
233 here.
234
235menu "Debugging options"
236
237config JUMP_UPON_UNHANDLED_EXCEPTION
238 bool "Try to die gracefully"
239 default y
240 help
241 Now this puts kernel into infinite loop after first oops. Till
242 your kernel crashes this doesn't have any influence.
243
244 Say Y if you are unsure.
245
246config OPENRISC_ESR_EXCEPTION_BUG_CHECK
247 bool "Check for possible ESR exception bug"
248 default n
249 help
250 This option enables some checks that might expose some problems
251 in kernel.
252
253 Say N if you are unsure.
254
255endmenu
256
257endmenu