tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI controller
8
9maintainers:
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12allOf:
13 - $ref: "../dsi-controller.yaml#"
14
15properties:
16 compatible:
17 enum:
18 - qcom,mdss-dsi-ctrl
19 - qcom,dsi-ctrl-6g-qcm2290
20
21 reg:
22 maxItems: 1
23
24 reg-names:
25 const: dsi_ctrl
26
27 interrupts:
28 maxItems: 1
29
30 clocks:
31 items:
32 - description: Display byte clock
33 - description: Display byte interface clock
34 - description: Display pixel clock
35 - description: Display escape clock
36 - description: Display AHB clock
37 - description: Display AXI clock
38
39 clock-names:
40 items:
41 - const: byte
42 - const: byte_intf
43 - const: pixel
44 - const: core
45 - const: iface
46 - const: bus
47
48 phys:
49 maxItems: 1
50
51 phy-names:
52 const: dsi
53
54 "#address-cells": true
55
56 "#size-cells": true
57
58 syscon-sfpb:
59 description: A phandle to mmss_sfpb syscon node (only for DSIv2).
60 $ref: "/schemas/types.yaml#/definitions/phandle"
61
62 qcom,dual-dsi-mode:
63 type: boolean
64 description: |
65 Indicates if the DSI controller is driving a panel which needs
66 2 DSI links.
67
68 assigned-clocks:
69 maxItems: 2
70 description: |
71 Parents of "byte" and "pixel" for the given platform.
72
73 assigned-clock-parents:
74 maxItems: 2
75 description: |
76 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
77
78 power-domains:
79 maxItems: 1
80
81 operating-points-v2: true
82
83 ports:
84 $ref: "/schemas/graph.yaml#/properties/ports"
85 description: |
86 Contains DSI controller input and output ports as children, each
87 containing one endpoint subnode.
88
89 properties:
90 port@0:
91 $ref: "/schemas/graph.yaml#/$defs/port-base"
92 unevaluatedProperties: false
93 description: |
94 Input endpoints of the controller.
95 properties:
96 endpoint:
97 $ref: /schemas/media/video-interfaces.yaml#
98 unevaluatedProperties: false
99 properties:
100 data-lanes:
101 maxItems: 4
102 minItems: 4
103 items:
104 enum: [ 0, 1, 2, 3 ]
105
106 port@1:
107 $ref: "/schemas/graph.yaml#/$defs/port-base"
108 unevaluatedProperties: false
109 description: |
110 Output endpoints of the controller.
111 properties:
112 endpoint:
113 $ref: /schemas/media/video-interfaces.yaml#
114 unevaluatedProperties: false
115 properties:
116 data-lanes:
117 maxItems: 4
118 minItems: 4
119 items:
120 enum: [ 0, 1, 2, 3 ]
121
122 required:
123 - port@0
124 - port@1
125
126required:
127 - compatible
128 - reg
129 - reg-names
130 - interrupts
131 - clocks
132 - clock-names
133 - phys
134 - phy-names
135 - assigned-clocks
136 - assigned-clock-parents
137 - power-domains
138 - operating-points-v2
139 - ports
140
141additionalProperties: false
142
143examples:
144 - |
145 #include <dt-bindings/interrupt-controller/arm-gic.h>
146 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
147 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
148 #include <dt-bindings/power/qcom-rpmpd.h>
149
150 dsi@ae94000 {
151 compatible = "qcom,mdss-dsi-ctrl";
152 reg = <0x0ae94000 0x400>;
153 reg-names = "dsi_ctrl";
154
155 #address-cells = <1>;
156 #size-cells = <0>;
157
158 interrupt-parent = <&mdss>;
159 interrupts = <4>;
160
161 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
162 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
163 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
164 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
165 <&dispcc DISP_CC_MDSS_AHB_CLK>,
166 <&dispcc DISP_CC_MDSS_AXI_CLK>;
167 clock-names = "byte",
168 "byte_intf",
169 "pixel",
170 "core",
171 "iface",
172 "bus";
173
174 phys = <&dsi0_phy>;
175 phy-names = "dsi";
176
177 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
178 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
179
180 power-domains = <&rpmhpd SC7180_CX>;
181 operating-points-v2 = <&dsi_opp_table>;
182
183 ports {
184 #address-cells = <1>;
185 #size-cells = <0>;
186
187 port@0 {
188 reg = <0>;
189 dsi0_in: endpoint {
190 remote-endpoint = <&dpu_intf1_out>;
191 };
192 };
193
194 port@1 {
195 reg = <1>;
196 dsi0_out: endpoint {
197 remote-endpoint = <&sn65dsi86_in>;
198 data-lanes = <0 1 2 3>;
199 };
200 };
201 };
202 };
203...