tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Socionext Inc.
4 */
5
6#include <linux/clk.h>
7#include <linux/console.h>
8#include <linux/module.h>
9#include <linux/of_irq.h>
10#include <linux/platform_device.h>
11#include <linux/serial_core.h>
12#include <linux/tty.h>
13#include <linux/tty_flip.h>
14
15#define USIO_NAME "mlb-usio-uart"
16#define USIO_UART_DEV_NAME "ttyUSI"
17
18static struct uart_port mlb_usio_ports[CONFIG_SERIAL_MILBEAUT_USIO_PORTS];
19
20#define RX 0
21#define TX 1
22static int mlb_usio_irq[CONFIG_SERIAL_MILBEAUT_USIO_PORTS][2];
23
24#define MLB_USIO_REG_SMR 0
25#define MLB_USIO_REG_SCR 1
26#define MLB_USIO_REG_ESCR 2
27#define MLB_USIO_REG_SSR 3
28#define MLB_USIO_REG_DR 4
29#define MLB_USIO_REG_BGR 6
30#define MLB_USIO_REG_FCR 12
31#define MLB_USIO_REG_FBYTE 14
32
33#define MLB_USIO_SMR_SOE BIT(0)
34#define MLB_USIO_SMR_SBL BIT(3)
35#define MLB_USIO_SCR_TXE BIT(0)
36#define MLB_USIO_SCR_RXE BIT(1)
37#define MLB_USIO_SCR_TBIE BIT(2)
38#define MLB_USIO_SCR_TIE BIT(3)
39#define MLB_USIO_SCR_RIE BIT(4)
40#define MLB_USIO_SCR_UPCL BIT(7)
41#define MLB_USIO_ESCR_L_8BIT 0
42#define MLB_USIO_ESCR_L_5BIT 1
43#define MLB_USIO_ESCR_L_6BIT 2
44#define MLB_USIO_ESCR_L_7BIT 3
45#define MLB_USIO_ESCR_P BIT(3)
46#define MLB_USIO_ESCR_PEN BIT(4)
47#define MLB_USIO_ESCR_FLWEN BIT(7)
48#define MLB_USIO_SSR_TBI BIT(0)
49#define MLB_USIO_SSR_TDRE BIT(1)
50#define MLB_USIO_SSR_RDRF BIT(2)
51#define MLB_USIO_SSR_ORE BIT(3)
52#define MLB_USIO_SSR_FRE BIT(4)
53#define MLB_USIO_SSR_PE BIT(5)
54#define MLB_USIO_SSR_REC BIT(7)
55#define MLB_USIO_SSR_BRK BIT(8)
56#define MLB_USIO_FCR_FE1 BIT(0)
57#define MLB_USIO_FCR_FE2 BIT(1)
58#define MLB_USIO_FCR_FCL1 BIT(2)
59#define MLB_USIO_FCR_FCL2 BIT(3)
60#define MLB_USIO_FCR_FSET BIT(4)
61#define MLB_USIO_FCR_FTIE BIT(9)
62#define MLB_USIO_FCR_FDRQ BIT(10)
63#define MLB_USIO_FCR_FRIIE BIT(11)
64
65static void mlb_usio_stop_tx(struct uart_port *port)
66{
67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
68 port->membase + MLB_USIO_REG_FCR);
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE,
70 port->membase + MLB_USIO_REG_SCR);
71}
72
73static void mlb_usio_tx_chars(struct uart_port *port)
74{
75 struct circ_buf *xmit = &port->state->xmit;
76 int count;
77
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
79 port->membase + MLB_USIO_REG_FCR);
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) &
81 ~(MLB_USIO_SCR_TIE | MLB_USIO_SCR_TBIE),
82 port->membase + MLB_USIO_REG_SCR);
83
84 if (port->x_char) {
85 writew(port->x_char, port->membase + MLB_USIO_REG_DR);
86 port->icount.tx++;
87 port->x_char = 0;
88 return;
89 }
90 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
91 mlb_usio_stop_tx(port);
92 return;
93 }
94
95 count = port->fifosize -
96 (readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff);
97
98 do {
99 writew(xmit->buf[xmit->tail], port->membase + MLB_USIO_REG_DR);
100
101 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
102 port->icount.tx++;
103 if (uart_circ_empty(xmit))
104 break;
105
106 } while (--count > 0);
107
108 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FDRQ,
109 port->membase + MLB_USIO_REG_FCR);
110
111 writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
112 port->membase + MLB_USIO_REG_SCR);
113
114 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
115 uart_write_wakeup(port);
116
117 if (uart_circ_empty(xmit))
118 mlb_usio_stop_tx(port);
119}
120
121static void mlb_usio_start_tx(struct uart_port *port)
122{
123 u16 fcr = readw(port->membase + MLB_USIO_REG_FCR);
124
125 writew(fcr | MLB_USIO_FCR_FTIE, port->membase + MLB_USIO_REG_FCR);
126 if (!(fcr & MLB_USIO_FCR_FDRQ))
127 return;
128
129 writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
130 port->membase + MLB_USIO_REG_SCR);
131
132 if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
133 mlb_usio_tx_chars(port);
134}
135
136static void mlb_usio_stop_rx(struct uart_port *port)
137{
138 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_RIE,
139 port->membase + MLB_USIO_REG_SCR);
140}
141
142static void mlb_usio_enable_ms(struct uart_port *port)
143{
144 writeb(readb(port->membase + MLB_USIO_REG_SCR) |
145 MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE,
146 port->membase + MLB_USIO_REG_SCR);
147}
148
149static void mlb_usio_rx_chars(struct uart_port *port)
150{
151 struct tty_port *ttyport = &port->state->port;
152 unsigned long flag = 0;
153 char ch = 0;
154 u8 status;
155 int max_count = 2;
156
157 while (max_count--) {
158 status = readb(port->membase + MLB_USIO_REG_SSR);
159
160 if (!(status & MLB_USIO_SSR_RDRF))
161 break;
162
163 if (!(status & (MLB_USIO_SSR_ORE | MLB_USIO_SSR_FRE |
164 MLB_USIO_SSR_PE))) {
165 ch = readw(port->membase + MLB_USIO_REG_DR);
166 flag = TTY_NORMAL;
167 port->icount.rx++;
168 if (uart_handle_sysrq_char(port, ch))
169 continue;
170 uart_insert_char(port, status, MLB_USIO_SSR_ORE,
171 ch, flag);
172 continue;
173 }
174 if (status & MLB_USIO_SSR_PE)
175 port->icount.parity++;
176 if (status & MLB_USIO_SSR_ORE)
177 port->icount.overrun++;
178 status &= port->read_status_mask;
179 if (status & MLB_USIO_SSR_BRK) {
180 flag = TTY_BREAK;
181 ch = 0;
182 } else
183 if (status & MLB_USIO_SSR_PE) {
184 flag = TTY_PARITY;
185 ch = 0;
186 } else
187 if (status & MLB_USIO_SSR_FRE) {
188 flag = TTY_FRAME;
189 ch = 0;
190 }
191 if (flag)
192 uart_insert_char(port, status, MLB_USIO_SSR_ORE,
193 ch, flag);
194
195 writeb(readb(port->membase + MLB_USIO_REG_SSR) |
196 MLB_USIO_SSR_REC,
197 port->membase + MLB_USIO_REG_SSR);
198
199 max_count = readw(port->membase + MLB_USIO_REG_FBYTE) >> 8;
200 writew(readw(port->membase + MLB_USIO_REG_FCR) |
201 MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
202 port->membase + MLB_USIO_REG_FCR);
203 }
204
205 tty_flip_buffer_push(ttyport);
206}
207
208static irqreturn_t mlb_usio_rx_irq(int irq, void *dev_id)
209{
210 struct uart_port *port = dev_id;
211
212 spin_lock(&port->lock);
213 mlb_usio_rx_chars(port);
214 spin_unlock(&port->lock);
215
216 return IRQ_HANDLED;
217}
218
219static irqreturn_t mlb_usio_tx_irq(int irq, void *dev_id)
220{
221 struct uart_port *port = dev_id;
222
223 spin_lock(&port->lock);
224 if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
225 mlb_usio_tx_chars(port);
226 spin_unlock(&port->lock);
227
228 return IRQ_HANDLED;
229}
230
231static unsigned int mlb_usio_tx_empty(struct uart_port *port)
232{
233 return (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI) ?
234 TIOCSER_TEMT : 0;
235}
236
237static void mlb_usio_set_mctrl(struct uart_port *port, unsigned int mctrl)
238{
239}
240
241static unsigned int mlb_usio_get_mctrl(struct uart_port *port)
242{
243 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
244
245}
246
247static void mlb_usio_break_ctl(struct uart_port *port, int break_state)
248{
249}
250
251static int mlb_usio_startup(struct uart_port *port)
252{
253 const char *portname = to_platform_device(port->dev)->name;
254 unsigned long flags;
255 int ret, index = port->line;
256 unsigned char escr;
257
258 ret = request_irq(mlb_usio_irq[index][RX], mlb_usio_rx_irq,
259 0, portname, port);
260 if (ret)
261 return ret;
262 ret = request_irq(mlb_usio_irq[index][TX], mlb_usio_tx_irq,
263 0, portname, port);
264 if (ret) {
265 free_irq(mlb_usio_irq[index][RX], port);
266 return ret;
267 }
268
269 escr = readb(port->membase + MLB_USIO_REG_ESCR);
270 if (of_property_read_bool(port->dev->of_node, "auto-flow-control"))
271 escr |= MLB_USIO_ESCR_FLWEN;
272 spin_lock_irqsave(&port->lock, flags);
273 writeb(0, port->membase + MLB_USIO_REG_SCR);
274 writeb(escr, port->membase + MLB_USIO_REG_ESCR);
275 writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
276 writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
277 writew(0, port->membase + MLB_USIO_REG_FCR);
278 writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2,
279 port->membase + MLB_USIO_REG_FCR);
280 writew(MLB_USIO_FCR_FE1 | MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
281 port->membase + MLB_USIO_REG_FCR);
282 writew(0, port->membase + MLB_USIO_REG_FBYTE);
283 writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
284
285 writeb(MLB_USIO_SCR_TXE | MLB_USIO_SCR_RIE | MLB_USIO_SCR_TBIE |
286 MLB_USIO_SCR_RXE, port->membase + MLB_USIO_REG_SCR);
287 spin_unlock_irqrestore(&port->lock, flags);
288
289 return 0;
290}
291
292static void mlb_usio_shutdown(struct uart_port *port)
293{
294 int index = port->line;
295
296 free_irq(mlb_usio_irq[index][RX], port);
297 free_irq(mlb_usio_irq[index][TX], port);
298}
299
300static void mlb_usio_set_termios(struct uart_port *port,
301 struct ktermios *termios,
302 const struct ktermios *old)
303{
304 unsigned int escr, smr = MLB_USIO_SMR_SOE;
305 unsigned long flags, baud, quot;
306
307 switch (termios->c_cflag & CSIZE) {
308 case CS5:
309 escr = MLB_USIO_ESCR_L_5BIT;
310 break;
311 case CS6:
312 escr = MLB_USIO_ESCR_L_6BIT;
313 break;
314 case CS7:
315 escr = MLB_USIO_ESCR_L_7BIT;
316 break;
317 case CS8:
318 default:
319 escr = MLB_USIO_ESCR_L_8BIT;
320 break;
321 }
322
323 if (termios->c_cflag & CSTOPB)
324 smr |= MLB_USIO_SMR_SBL;
325
326 if (termios->c_cflag & PARENB) {
327 escr |= MLB_USIO_ESCR_PEN;
328 if (termios->c_cflag & PARODD)
329 escr |= MLB_USIO_ESCR_P;
330 }
331 /* Set hard flow control */
332 if (of_property_read_bool(port->dev->of_node, "auto-flow-control") ||
333 (termios->c_cflag & CRTSCTS))
334 escr |= MLB_USIO_ESCR_FLWEN;
335
336 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
337 if (baud > 1)
338 quot = port->uartclk / baud - 1;
339 else
340 quot = 0;
341
342 spin_lock_irqsave(&port->lock, flags);
343 uart_update_timeout(port, termios->c_cflag, baud);
344 port->read_status_mask = MLB_USIO_SSR_ORE | MLB_USIO_SSR_RDRF |
345 MLB_USIO_SSR_TDRE;
346 if (termios->c_iflag & INPCK)
347 port->read_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
348
349 port->ignore_status_mask = 0;
350 if (termios->c_iflag & IGNPAR)
351 port->ignore_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
352 if ((termios->c_iflag & IGNBRK) && (termios->c_iflag & IGNPAR))
353 port->ignore_status_mask |= MLB_USIO_SSR_ORE;
354 if ((termios->c_cflag & CREAD) == 0)
355 port->ignore_status_mask |= MLB_USIO_SSR_RDRF;
356
357 writeb(0, port->membase + MLB_USIO_REG_SCR);
358 writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
359 writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
360 writew(0, port->membase + MLB_USIO_REG_FCR);
361 writeb(smr, port->membase + MLB_USIO_REG_SMR);
362 writeb(escr, port->membase + MLB_USIO_REG_ESCR);
363 writew(quot, port->membase + MLB_USIO_REG_BGR);
364 writew(0, port->membase + MLB_USIO_REG_FCR);
365 writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2 | MLB_USIO_FCR_FE1 |
366 MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
367 port->membase + MLB_USIO_REG_FCR);
368 writew(0, port->membase + MLB_USIO_REG_FBYTE);
369 writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
370 writeb(MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE | MLB_USIO_SCR_TBIE |
371 MLB_USIO_SCR_TXE, port->membase + MLB_USIO_REG_SCR);
372 spin_unlock_irqrestore(&port->lock, flags);
373}
374
375static const char *mlb_usio_type(struct uart_port *port)
376{
377 return ((port->type == PORT_MLB_USIO) ? USIO_NAME : NULL);
378}
379
380static void mlb_usio_config_port(struct uart_port *port, int flags)
381{
382 if (flags & UART_CONFIG_TYPE)
383 port->type = PORT_MLB_USIO;
384}
385
386static const struct uart_ops mlb_usio_ops = {
387 .tx_empty = mlb_usio_tx_empty,
388 .set_mctrl = mlb_usio_set_mctrl,
389 .get_mctrl = mlb_usio_get_mctrl,
390 .stop_tx = mlb_usio_stop_tx,
391 .start_tx = mlb_usio_start_tx,
392 .stop_rx = mlb_usio_stop_rx,
393 .enable_ms = mlb_usio_enable_ms,
394 .break_ctl = mlb_usio_break_ctl,
395 .startup = mlb_usio_startup,
396 .shutdown = mlb_usio_shutdown,
397 .set_termios = mlb_usio_set_termios,
398 .type = mlb_usio_type,
399 .config_port = mlb_usio_config_port,
400};
401
402#ifdef CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE
403
404static void mlb_usio_console_putchar(struct uart_port *port, unsigned char c)
405{
406 while (!(readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TDRE))
407 cpu_relax();
408
409 writew(c, port->membase + MLB_USIO_REG_DR);
410}
411
412static void mlb_usio_console_write(struct console *co, const char *s,
413 unsigned int count)
414{
415 struct uart_port *port = &mlb_usio_ports[co->index];
416
417 uart_console_write(port, s, count, mlb_usio_console_putchar);
418}
419
420static int __init mlb_usio_console_setup(struct console *co, char *options)
421{
422 struct uart_port *port;
423 int baud = 115200;
424 int parity = 'n';
425 int flow = 'n';
426 int bits = 8;
427
428 if (co->index >= CONFIG_SERIAL_MILBEAUT_USIO_PORTS)
429 return -ENODEV;
430
431 port = &mlb_usio_ports[co->index];
432 if (!port->membase)
433 return -ENODEV;
434
435
436 if (options)
437 uart_parse_options(options, &baud, &parity, &bits, &flow);
438
439 if (of_property_read_bool(port->dev->of_node, "auto-flow-control"))
440 flow = 'r';
441
442 return uart_set_options(port, co, baud, parity, bits, flow);
443}
444
445
446static struct uart_driver mlb_usio_uart_driver;
447static struct console mlb_usio_console = {
448 .name = USIO_UART_DEV_NAME,
449 .write = mlb_usio_console_write,
450 .device = uart_console_device,
451 .setup = mlb_usio_console_setup,
452 .flags = CON_PRINTBUFFER,
453 .index = -1,
454 .data = &mlb_usio_uart_driver,
455};
456
457static int __init mlb_usio_console_init(void)
458{
459 register_console(&mlb_usio_console);
460 return 0;
461}
462console_initcall(mlb_usio_console_init);
463
464
465static void mlb_usio_early_console_write(struct console *co, const char *s,
466 u_int count)
467{
468 struct earlycon_device *dev = co->data;
469
470 uart_console_write(&dev->port, s, count, mlb_usio_console_putchar);
471}
472
473static int __init mlb_usio_early_console_setup(struct earlycon_device *device,
474 const char *opt)
475{
476 if (!device->port.membase)
477 return -ENODEV;
478 device->con->write = mlb_usio_early_console_write;
479 return 0;
480}
481
482OF_EARLYCON_DECLARE(mlb_usio, "socionext,milbeaut-usio-uart",
483 mlb_usio_early_console_setup);
484
485#define USIO_CONSOLE (&mlb_usio_console)
486#else
487#define USIO_CONSOLE NULL
488#endif
489
490static struct uart_driver mlb_usio_uart_driver = {
491 .owner = THIS_MODULE,
492 .driver_name = USIO_NAME,
493 .dev_name = USIO_UART_DEV_NAME,
494 .cons = USIO_CONSOLE,
495 .nr = CONFIG_SERIAL_MILBEAUT_USIO_PORTS,
496};
497
498static int mlb_usio_probe(struct platform_device *pdev)
499{
500 struct clk *clk = devm_clk_get(&pdev->dev, NULL);
501 struct uart_port *port;
502 struct resource *res;
503 int index = 0;
504 int ret;
505
506 if (IS_ERR(clk)) {
507 dev_err(&pdev->dev, "Missing clock\n");
508 return PTR_ERR(clk);
509 }
510 ret = clk_prepare_enable(clk);
511 if (ret) {
512 dev_err(&pdev->dev, "Clock enable failed: %d\n", ret);
513 return ret;
514 }
515 of_property_read_u32(pdev->dev.of_node, "index", &index);
516 port = &mlb_usio_ports[index];
517
518 port->private_data = (void *)clk;
519 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
520 if (res == NULL) {
521 dev_err(&pdev->dev, "Missing regs\n");
522 ret = -ENODEV;
523 goto failed;
524 }
525 port->membase = devm_ioremap(&pdev->dev, res->start,
526 resource_size(res));
527
528 ret = platform_get_irq_byname(pdev, "rx");
529 mlb_usio_irq[index][RX] = ret;
530
531 ret = platform_get_irq_byname(pdev, "tx");
532 mlb_usio_irq[index][TX] = ret;
533
534 port->irq = mlb_usio_irq[index][RX];
535 port->uartclk = clk_get_rate(clk);
536 port->fifosize = 128;
537 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE);
538 port->iotype = UPIO_MEM32;
539 port->flags = UPF_BOOT_AUTOCONF | UPF_SPD_VHI;
540 port->line = index;
541 port->ops = &mlb_usio_ops;
542 port->dev = &pdev->dev;
543
544 ret = uart_add_one_port(&mlb_usio_uart_driver, port);
545 if (ret) {
546 dev_err(&pdev->dev, "Adding port failed: %d\n", ret);
547 goto failed;
548 }
549 return 0;
550
551failed:
552 clk_disable_unprepare(clk);
553
554 return ret;
555}
556
557static int mlb_usio_remove(struct platform_device *pdev)
558{
559 struct uart_port *port = &mlb_usio_ports[pdev->id];
560 struct clk *clk = port->private_data;
561
562 uart_remove_one_port(&mlb_usio_uart_driver, port);
563 clk_disable_unprepare(clk);
564
565 return 0;
566}
567
568static const struct of_device_id mlb_usio_dt_ids[] = {
569 { .compatible = "socionext,milbeaut-usio-uart" },
570 { /* sentinel */ }
571};
572MODULE_DEVICE_TABLE(of, mlb_usio_dt_ids);
573
574static struct platform_driver mlb_usio_driver = {
575 .probe = mlb_usio_probe,
576 .remove = mlb_usio_remove,
577 .driver = {
578 .name = USIO_NAME,
579 .of_match_table = mlb_usio_dt_ids,
580 },
581};
582
583static int __init mlb_usio_init(void)
584{
585 int ret = uart_register_driver(&mlb_usio_uart_driver);
586
587 if (ret) {
588 pr_err("%s: uart registration failed: %d\n", __func__, ret);
589 return ret;
590 }
591 ret = platform_driver_register(&mlb_usio_driver);
592 if (ret) {
593 uart_unregister_driver(&mlb_usio_uart_driver);
594 pr_err("%s: drv registration failed: %d\n", __func__, ret);
595 return ret;
596 }
597
598 return 0;
599}
600
601static void __exit mlb_usio_exit(void)
602{
603 platform_driver_unregister(&mlb_usio_driver);
604 uart_unregister_driver(&mlb_usio_uart_driver);
605}
606
607module_init(mlb_usio_init);
608module_exit(mlb_usio_exit);
609
610MODULE_AUTHOR("SOCIONEXT");
611MODULE_DESCRIPTION("MILBEAUT_USIO/UART Driver");
612MODULE_LICENSE("GPL");