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Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (PCIe)
8
9maintainers:
10 - Vinod Koul <vkoul@kernel.org>
11
12description:
13 QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17 compatible:
18 enum:
19 - qcom,ipq6018-qmp-pcie-phy
20 - qcom,ipq8074-qmp-gen3-pcie-phy
21 - qcom,ipq8074-qmp-pcie-phy
22 - qcom,msm8998-qmp-pcie-phy
23 - qcom,sc8180x-qmp-pcie-phy
24 - qcom,sdm845-qhp-pcie-phy
25 - qcom,sdm845-qmp-pcie-phy
26 - qcom,sdx55-qmp-pcie-phy
27 - qcom,sm8250-qmp-gen3x1-pcie-phy
28 - qcom,sm8250-qmp-gen3x2-pcie-phy
29 - qcom,sm8250-qmp-modem-pcie-phy
30 - qcom,sm8450-qmp-gen3x1-pcie-phy
31 - qcom,sm8450-qmp-gen4x2-pcie-phy
32
33 reg:
34 items:
35 - description: serdes
36
37 "#address-cells":
38 enum: [ 1, 2 ]
39
40 "#size-cells":
41 enum: [ 1, 2 ]
42
43 ranges: true
44
45 clocks:
46 minItems: 2
47 maxItems: 4
48
49 clock-names:
50 minItems: 2
51 maxItems: 4
52
53 resets:
54 minItems: 1
55 maxItems: 2
56
57 reset-names:
58 minItems: 1
59 maxItems: 2
60
61 vdda-phy-supply: true
62
63 vdda-pll-supply: true
64
65 vddp-ref-clk-supply: true
66
67patternProperties:
68 "^phy@[0-9a-f]+$":
69 type: object
70 description: single PHY-provider child node
71 properties:
72 reg:
73 minItems: 3
74 maxItems: 6
75
76 clocks:
77 items:
78 - description: PIPE clock
79
80 clock-names:
81 deprecated: true
82 items:
83 - const: pipe0
84
85 "#clock-cells":
86 const: 0
87
88 clock-output-names:
89 maxItems: 1
90
91 "#phy-cells":
92 const: 0
93
94 required:
95 - reg
96 - clocks
97 - "#clock-cells"
98 - clock-output-names
99 - "#phy-cells"
100
101 additionalProperties: false
102
103required:
104 - compatible
105 - reg
106 - "#address-cells"
107 - "#size-cells"
108 - ranges
109 - clocks
110 - clock-names
111 - resets
112 - reset-names
113
114additionalProperties: false
115
116allOf:
117 - if:
118 properties:
119 compatible:
120 contains:
121 enum:
122 - qcom,msm8998-qmp-pcie-phy
123 then:
124 properties:
125 clocks:
126 maxItems: 3
127 clock-names:
128 items:
129 - const: aux
130 - const: cfg_ahb
131 - const: ref
132 resets:
133 maxItems: 2
134 reset-names:
135 items:
136 - const: phy
137 - const: common
138 required:
139 - vdda-phy-supply
140 - vdda-pll-supply
141
142 - if:
143 properties:
144 compatible:
145 contains:
146 enum:
147 - qcom,ipq6018-qmp-pcie-phy
148 - qcom,ipq8074-qmp-gen3-pcie-phy
149 - qcom,ipq8074-qmp-pcie-phy
150 then:
151 properties:
152 clocks:
153 maxItems: 2
154 clock-names:
155 items:
156 - const: aux
157 - const: cfg_ahb
158 resets:
159 maxItems: 2
160 reset-names:
161 items:
162 - const: phy
163 - const: common
164
165 - if:
166 properties:
167 compatible:
168 contains:
169 enum:
170 - qcom,sc8180x-qmp-pcie-phy
171 - qcom,sdm845-qhp-pcie-phy
172 - qcom,sdm845-qmp-pcie-phy
173 - qcom,sdx55-qmp-pcie-phy
174 - qcom,sm8250-qmp-gen3x1-pcie-phy
175 - qcom,sm8250-qmp-gen3x2-pcie-phy
176 - qcom,sm8250-qmp-modem-pcie-phy
177 - qcom,sm8450-qmp-gen3x1-pcie-phy
178 - qcom,sm8450-qmp-gen4x2-pcie-phy
179 then:
180 properties:
181 clocks:
182 maxItems: 4
183 clock-names:
184 items:
185 - const: aux
186 - const: cfg_ahb
187 - const: ref
188 - const: refgen
189 resets:
190 maxItems: 1
191 reset-names:
192 items:
193 - const: phy
194 required:
195 - vdda-phy-supply
196 - vdda-pll-supply
197
198 - if:
199 properties:
200 compatible:
201 contains:
202 enum:
203 - qcom,sm8250-qmp-gen3x2-pcie-phy
204 - qcom,sm8250-qmp-modem-pcie-phy
205 - qcom,sm8450-qmp-gen4x2-pcie-phy
206 then:
207 patternProperties:
208 "^phy@[0-9a-f]+$":
209 properties:
210 reg:
211 items:
212 - description: TX lane 1
213 - description: RX lane 1
214 - description: PCS
215 - description: TX lane 2
216 - description: RX lane 2
217 - description: PCS_MISC
218
219 - if:
220 properties:
221 compatible:
222 contains:
223 enum:
224 - qcom,sc8180x-qmp-pcie-phy
225 - qcom,sdm845-qmp-pcie-phy
226 - qcom,sdx55-qmp-pcie-phy
227 - qcom,sm8250-qmp-gen3x1-pcie-phy
228 - qcom,sm8450-qmp-gen3x1-pcie-phy
229 then:
230 patternProperties:
231 "^phy@[0-9a-f]+$":
232 properties:
233 reg:
234 items:
235 - description: TX
236 - description: RX
237 - description: PCS
238 - description: PCS_MISC
239
240 - if:
241 properties:
242 compatible:
243 contains:
244 enum:
245 - qcom,ipq6018-qmp-pcie-phy
246 - qcom,ipq8074-qmp-pcie-phy
247 - qcom,msm8998-qmp-pcie-phy
248 - qcom,sdm845-qhp-pcie-phy
249 then:
250 patternProperties:
251 "^phy@[0-9a-f]+$":
252 properties:
253 reg:
254 items:
255 - description: TX
256 - description: RX
257 - description: PCS
258
259examples:
260 - |
261 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
262 phy-wrapper@1c0e000 {
263 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
264 reg = <0x01c0e000 0x1c0>;
265 #address-cells = <1>;
266 #size-cells = <1>;
267 ranges = <0x0 0x01c0e000 0x1000>;
268
269 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
270 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
271 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
272 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
273 clock-names = "aux", "cfg_ahb", "ref", "refgen";
274
275 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
276 reset-names = "phy";
277
278 vdda-phy-supply = <&vreg_l10c_0p88>;
279 vdda-pll-supply = <&vreg_l6b_1p2>;
280
281 phy@200 {
282 reg = <0x200 0x170>,
283 <0x400 0x200>,
284 <0xa00 0x1f0>,
285 <0x600 0x170>,
286 <0x800 0x200>,
287 <0xe00 0xf4>;
288
289 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
290
291 #clock-cells = <0>;
292 clock-output-names = "pcie_1_pipe_clk";
293
294 #phy-cells = <0>;
295 };
296 };