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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm PCI express root complex
8
9maintainers:
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Stanimir Varbanov <svarbanov@mm-sol.com>
12
13description: |
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
16
17properties:
18 compatible:
19 enum:
20 - qcom,pcie-ipq8064
21 - qcom,pcie-ipq8064-v2
22 - qcom,pcie-apq8064
23 - qcom,pcie-apq8084
24 - qcom,pcie-msm8996
25 - qcom,pcie-ipq4019
26 - qcom,pcie-ipq8074
27 - qcom,pcie-qcs404
28 - qcom,pcie-sa8540p
29 - qcom,pcie-sc7280
30 - qcom,pcie-sc8180x
31 - qcom,pcie-sc8280xp
32 - qcom,pcie-sdm845
33 - qcom,pcie-sm8150
34 - qcom,pcie-sm8250
35 - qcom,pcie-sm8450-pcie0
36 - qcom,pcie-sm8450-pcie1
37 - qcom,pcie-ipq6018
38
39 reg:
40 minItems: 4
41 maxItems: 5
42
43 reg-names:
44 minItems: 4
45 maxItems: 5
46
47 interrupts:
48 minItems: 1
49 maxItems: 8
50
51 interrupt-names:
52 minItems: 1
53 maxItems: 8
54
55 # Common definitions for clocks, clock-names and reset.
56 # Platform constraints are described later.
57 clocks:
58 minItems: 3
59 maxItems: 13
60
61 clock-names:
62 minItems: 3
63 maxItems: 13
64
65 resets:
66 minItems: 1
67 maxItems: 12
68
69 resets-names:
70 minItems: 1
71 maxItems: 12
72
73 vdda-supply:
74 description: A phandle to the core analog power supply
75
76 vdda_phy-supply:
77 description: A phandle to the core analog power supply for PHY
78
79 vdda_refclk-supply:
80 description: A phandle to the core analog power supply for IC which generates reference clock
81
82 vddpe-3v3-supply:
83 description: A phandle to the PCIe endpoint power supply
84
85 phys:
86 maxItems: 1
87
88 phy-names:
89 items:
90 - const: pciephy
91
92 power-domains:
93 maxItems: 1
94
95 perst-gpios:
96 description: GPIO controlled connection to PERST# signal
97 maxItems: 1
98
99 wake-gpios:
100 description: GPIO controlled connection to WAKE# signal
101 maxItems: 1
102
103required:
104 - compatible
105 - reg
106 - reg-names
107 - interrupts
108 - interrupt-names
109 - "#interrupt-cells"
110 - interrupt-map-mask
111 - interrupt-map
112 - clocks
113 - clock-names
114
115allOf:
116 - $ref: /schemas/pci/pci-bus.yaml#
117 - if:
118 properties:
119 compatible:
120 contains:
121 enum:
122 - qcom,pcie-apq8064
123 - qcom,pcie-ipq4019
124 - qcom,pcie-ipq8064
125 - qcom,pcie-ipq8064v2
126 - qcom,pcie-ipq8074
127 - qcom,pcie-qcs404
128 then:
129 properties:
130 reg:
131 minItems: 4
132 maxItems: 4
133 reg-names:
134 items:
135 - const: dbi # DesignWare PCIe registers
136 - const: elbi # External local bus interface registers
137 - const: parf # Qualcomm specific registers
138 - const: config # PCIe configuration space
139
140 - if:
141 properties:
142 compatible:
143 contains:
144 enum:
145 - qcom,pcie-ipq6018
146 then:
147 properties:
148 reg:
149 minItems: 5
150 maxItems: 5
151 reg-names:
152 items:
153 - const: dbi # DesignWare PCIe registers
154 - const: elbi # External local bus interface registers
155 - const: atu # ATU address space
156 - const: parf # Qualcomm specific registers
157 - const: config # PCIe configuration space
158
159 - if:
160 properties:
161 compatible:
162 contains:
163 enum:
164 - qcom,pcie-apq8084
165 - qcom,pcie-msm8996
166 - qcom,pcie-sdm845
167 then:
168 properties:
169 reg:
170 minItems: 4
171 maxItems: 4
172 reg-names:
173 items:
174 - const: parf # Qualcomm specific registers
175 - const: dbi # DesignWare PCIe registers
176 - const: elbi # External local bus interface registers
177 - const: config # PCIe configuration space
178
179 - if:
180 properties:
181 compatible:
182 contains:
183 enum:
184 - qcom,pcie-sc7280
185 - qcom,pcie-sc8180x
186 - qcom,pcie-sc8280xp
187 - qcom,pcie-sm8250
188 - qcom,pcie-sm8450-pcie0
189 - qcom,pcie-sm8450-pcie1
190 then:
191 properties:
192 reg:
193 minItems: 5
194 maxItems: 5
195 reg-names:
196 items:
197 - const: parf # Qualcomm specific registers
198 - const: dbi # DesignWare PCIe registers
199 - const: elbi # External local bus interface registers
200 - const: atu # ATU address space
201 - const: config # PCIe configuration space
202
203 - if:
204 properties:
205 compatible:
206 contains:
207 enum:
208 - qcom,pcie-apq8064
209 - qcom,pcie-ipq8064
210 - qcom,pcie-ipq8064v2
211 then:
212 properties:
213 clocks:
214 minItems: 3
215 maxItems: 5
216 clock-names:
217 minItems: 3
218 items:
219 - const: core # Clocks the pcie hw block
220 - const: iface # Configuration AHB clock
221 - const: phy # Clocks the pcie PHY block
222 - const: aux # Clocks the pcie AUX block, not on apq8064
223 - const: ref # Clocks the pcie ref block, not on apq8064
224 resets:
225 minItems: 5
226 maxItems: 6
227 reset-names:
228 minItems: 5
229 items:
230 - const: axi # AXI reset
231 - const: ahb # AHB reset
232 - const: por # POR reset
233 - const: pci # PCI reset
234 - const: phy # PHY reset
235 - const: ext # EXT reset, not on apq8064
236 required:
237 - vdda-supply
238 - vdda_phy-supply
239 - vdda_refclk-supply
240
241 - if:
242 properties:
243 compatible:
244 contains:
245 enum:
246 - qcom,pcie-apq8084
247 then:
248 properties:
249 clocks:
250 minItems: 4
251 maxItems: 4
252 clock-names:
253 items:
254 - const: iface # Configuration AHB clock
255 - const: master_bus # Master AXI clock
256 - const: slave_bus # Slave AXI clock
257 - const: aux # Auxiliary (AUX) clock
258 resets:
259 maxItems: 1
260 reset-names:
261 items:
262 - const: core # Core reset
263
264 - if:
265 properties:
266 compatible:
267 contains:
268 enum:
269 - qcom,pcie-ipq4019
270 then:
271 properties:
272 clocks:
273 minItems: 3
274 maxItems: 3
275 clock-names:
276 items:
277 - const: aux # Auxiliary (AUX) clock
278 - const: master_bus # Master AXI clock
279 - const: slave_bus # Slave AXI clock
280 resets:
281 minItems: 12
282 maxItems: 12
283 reset-names:
284 items:
285 - const: axi_m # AXI master reset
286 - const: axi_s # AXI slave reset
287 - const: pipe # PIPE reset
288 - const: axi_m_vmid # VMID reset
289 - const: axi_s_xpu # XPU reset
290 - const: parf # PARF reset
291 - const: phy # PHY reset
292 - const: axi_m_sticky # AXI sticky reset
293 - const: pipe_sticky # PIPE sticky reset
294 - const: pwr # PWR reset
295 - const: ahb # AHB reset
296 - const: phy_ahb # PHY AHB reset
297
298 - if:
299 properties:
300 compatible:
301 contains:
302 enum:
303 - qcom,pcie-msm8996
304 then:
305 oneOf:
306 - properties:
307 clock-names:
308 items:
309 - const: pipe # Pipe Clock driving internal logic
310 - const: aux # Auxiliary (AUX) clock
311 - const: cfg # Configuration clock
312 - const: bus_master # Master AXI clock
313 - const: bus_slave # Slave AXI clock
314 - properties:
315 clock-names:
316 items:
317 - const: pipe # Pipe Clock driving internal logic
318 - const: bus_master # Master AXI clock
319 - const: bus_slave # Slave AXI clock
320 - const: cfg # Configuration clock
321 - const: aux # Auxiliary (AUX) clock
322 properties:
323 clocks:
324 minItems: 5
325 maxItems: 5
326 resets: false
327 reset-names: false
328
329 - if:
330 properties:
331 compatible:
332 contains:
333 enum:
334 - qcom,pcie-ipq8074
335 then:
336 properties:
337 clocks:
338 minItems: 5
339 maxItems: 5
340 clock-names:
341 items:
342 - const: iface # PCIe to SysNOC BIU clock
343 - const: axi_m # AXI Master clock
344 - const: axi_s # AXI Slave clock
345 - const: ahb # AHB clock
346 - const: aux # Auxiliary clock
347 resets:
348 minItems: 7
349 maxItems: 7
350 reset-names:
351 items:
352 - const: pipe # PIPE reset
353 - const: sleep # Sleep reset
354 - const: sticky # Core Sticky reset
355 - const: axi_m # AXI Master reset
356 - const: axi_s # AXI Slave reset
357 - const: ahb # AHB Reset
358 - const: axi_m_sticky # AXI Master Sticky reset
359
360 - if:
361 properties:
362 compatible:
363 contains:
364 enum:
365 - qcom,pcie-ipq6018
366 then:
367 properties:
368 clocks:
369 minItems: 5
370 maxItems: 5
371 clock-names:
372 items:
373 - const: iface # PCIe to SysNOC BIU clock
374 - const: axi_m # AXI Master clock
375 - const: axi_s # AXI Slave clock
376 - const: axi_bridge # AXI bridge clock
377 - const: rchng
378 resets:
379 minItems: 8
380 maxItems: 8
381 reset-names:
382 items:
383 - const: pipe # PIPE reset
384 - const: sleep # Sleep reset
385 - const: sticky # Core Sticky reset
386 - const: axi_m # AXI Master reset
387 - const: axi_s # AXI Slave reset
388 - const: ahb # AHB Reset
389 - const: axi_m_sticky # AXI Master Sticky reset
390 - const: axi_s_sticky # AXI Slave Sticky reset
391
392 - if:
393 properties:
394 compatible:
395 contains:
396 enum:
397 - qcom,pcie-qcs404
398 then:
399 properties:
400 clocks:
401 minItems: 4
402 maxItems: 4
403 clock-names:
404 items:
405 - const: iface # AHB clock
406 - const: aux # Auxiliary clock
407 - const: master_bus # AXI Master clock
408 - const: slave_bus # AXI Slave clock
409 resets:
410 minItems: 6
411 maxItems: 6
412 reset-names:
413 items:
414 - const: axi_m # AXI Master reset
415 - const: axi_s # AXI Slave reset
416 - const: axi_m_sticky # AXI Master Sticky reset
417 - const: pipe_sticky # PIPE sticky reset
418 - const: pwr # PWR reset
419 - const: ahb # AHB reset
420
421 - if:
422 properties:
423 compatible:
424 contains:
425 enum:
426 - qcom,pcie-sc7280
427 then:
428 properties:
429 clocks:
430 minItems: 13
431 maxItems: 13
432 clock-names:
433 items:
434 - const: pipe # PIPE clock
435 - const: pipe_mux # PIPE MUX
436 - const: phy_pipe # PIPE output clock
437 - const: ref # REFERENCE clock
438 - const: aux # Auxiliary clock
439 - const: cfg # Configuration clock
440 - const: bus_master # Master AXI clock
441 - const: bus_slave # Slave AXI clock
442 - const: slave_q2a # Slave Q2A clock
443 - const: tbu # PCIe TBU clock
444 - const: ddrss_sf_tbu # PCIe SF TBU clock
445 - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
446 - const: aggre1 # Aggre NoC PCIe1 AXI clock
447 resets:
448 maxItems: 1
449 reset-names:
450 items:
451 - const: pci # PCIe core reset
452
453 - if:
454 properties:
455 compatible:
456 contains:
457 enum:
458 - qcom,pcie-sdm845
459 then:
460 oneOf:
461 # Unfortunately the "optional" ref clock is used in the middle of the list
462 - properties:
463 clocks:
464 minItems: 8
465 maxItems: 8
466 clock-names:
467 items:
468 - const: pipe # PIPE clock
469 - const: aux # Auxiliary clock
470 - const: cfg # Configuration clock
471 - const: bus_master # Master AXI clock
472 - const: bus_slave # Slave AXI clock
473 - const: slave_q2a # Slave Q2A clock
474 - const: ref # REFERENCE clock
475 - const: tbu # PCIe TBU clock
476 - properties:
477 clocks:
478 minItems: 7
479 maxItems: 7
480 clock-names:
481 items:
482 - const: pipe # PIPE clock
483 - const: aux # Auxiliary clock
484 - const: cfg # Configuration clock
485 - const: bus_master # Master AXI clock
486 - const: bus_slave # Slave AXI clock
487 - const: slave_q2a # Slave Q2A clock
488 - const: tbu # PCIe TBU clock
489 properties:
490 resets:
491 maxItems: 1
492 reset-names:
493 items:
494 - const: pci # PCIe core reset
495
496 - if:
497 properties:
498 compatible:
499 contains:
500 enum:
501 - qcom,pcie-sc8180x
502 - qcom,pcie-sm8150
503 - qcom,pcie-sm8250
504 then:
505 oneOf:
506 # Unfortunately the "optional" ref clock is used in the middle of the list
507 - properties:
508 clocks:
509 minItems: 9
510 maxItems: 9
511 clock-names:
512 items:
513 - const: pipe # PIPE clock
514 - const: aux # Auxiliary clock
515 - const: cfg # Configuration clock
516 - const: bus_master # Master AXI clock
517 - const: bus_slave # Slave AXI clock
518 - const: slave_q2a # Slave Q2A clock
519 - const: ref # REFERENCE clock
520 - const: tbu # PCIe TBU clock
521 - const: ddrss_sf_tbu # PCIe SF TBU clock
522 - properties:
523 clocks:
524 minItems: 8
525 maxItems: 8
526 clock-names:
527 items:
528 - const: pipe # PIPE clock
529 - const: aux # Auxiliary clock
530 - const: cfg # Configuration clock
531 - const: bus_master # Master AXI clock
532 - const: bus_slave # Slave AXI clock
533 - const: slave_q2a # Slave Q2A clock
534 - const: tbu # PCIe TBU clock
535 - const: ddrss_sf_tbu # PCIe SF TBU clock
536 properties:
537 resets:
538 maxItems: 1
539 reset-names:
540 items:
541 - const: pci # PCIe core reset
542
543 - if:
544 properties:
545 compatible:
546 contains:
547 enum:
548 - qcom,pcie-sm8450-pcie0
549 then:
550 properties:
551 clocks:
552 minItems: 12
553 maxItems: 12
554 clock-names:
555 items:
556 - const: pipe # PIPE clock
557 - const: pipe_mux # PIPE MUX
558 - const: phy_pipe # PIPE output clock
559 - const: ref # REFERENCE clock
560 - const: aux # Auxiliary clock
561 - const: cfg # Configuration clock
562 - const: bus_master # Master AXI clock
563 - const: bus_slave # Slave AXI clock
564 - const: slave_q2a # Slave Q2A clock
565 - const: ddrss_sf_tbu # PCIe SF TBU clock
566 - const: aggre0 # Aggre NoC PCIe0 AXI clock
567 - const: aggre1 # Aggre NoC PCIe1 AXI clock
568 resets:
569 maxItems: 1
570 reset-names:
571 items:
572 - const: pci # PCIe core reset
573
574 - if:
575 properties:
576 compatible:
577 contains:
578 enum:
579 - qcom,pcie-sm8450-pcie1
580 then:
581 properties:
582 clocks:
583 minItems: 11
584 maxItems: 11
585 clock-names:
586 items:
587 - const: pipe # PIPE clock
588 - const: pipe_mux # PIPE MUX
589 - const: phy_pipe # PIPE output clock
590 - const: ref # REFERENCE clock
591 - const: aux # Auxiliary clock
592 - const: cfg # Configuration clock
593 - const: bus_master # Master AXI clock
594 - const: bus_slave # Slave AXI clock
595 - const: slave_q2a # Slave Q2A clock
596 - const: ddrss_sf_tbu # PCIe SF TBU clock
597 - const: aggre1 # Aggre NoC PCIe1 AXI clock
598 resets:
599 maxItems: 1
600 reset-names:
601 items:
602 - const: pci # PCIe core reset
603
604 - if:
605 properties:
606 compatible:
607 contains:
608 enum:
609 - qcom,pcie-sa8540p
610 - qcom,pcie-sc8280xp
611 then:
612 properties:
613 clocks:
614 minItems: 8
615 maxItems: 9
616 clock-names:
617 minItems: 8
618 items:
619 - const: aux # Auxiliary clock
620 - const: cfg # Configuration clock
621 - const: bus_master # Master AXI clock
622 - const: bus_slave # Slave AXI clock
623 - const: slave_q2a # Slave Q2A clock
624 - const: ddrss_sf_tbu # PCIe SF TBU clock
625 - const: noc_aggr_4 # NoC aggregate 4 clock
626 - const: noc_aggr_south_sf # NoC aggregate South SF clock
627 - const: cnoc_qx # Configuration NoC QX clock
628 resets:
629 maxItems: 1
630 reset-names:
631 items:
632 - const: pci # PCIe core reset
633
634 - if:
635 not:
636 properties:
637 compatible:
638 contains:
639 enum:
640 - qcom,pcie-apq8064
641 - qcom,pcie-ipq4019
642 - qcom,pcie-ipq8064
643 - qcom,pcie-ipq8064v2
644 - qcom,pcie-ipq8074
645 - qcom,pcie-qcs404
646 then:
647 required:
648 - power-domains
649
650 - if:
651 not:
652 properties:
653 compatible:
654 contains:
655 enum:
656 - qcom,pcie-msm8996
657 then:
658 required:
659 - resets
660 - reset-names
661
662 - if:
663 properties:
664 compatible:
665 contains:
666 enum:
667 - qcom,pcie-msm8996
668 - qcom,pcie-sc7280
669 - qcom,pcie-sc8180x
670 - qcom,pcie-sdm845
671 - qcom,pcie-sm8150
672 - qcom,pcie-sm8250
673 - qcom,pcie-sm8450-pcie0
674 - qcom,pcie-sm8450-pcie1
675 then:
676 oneOf:
677 - properties:
678 interrupts:
679 maxItems: 1
680 interrupt-names:
681 items:
682 - const: msi
683 - properties:
684 interrupts:
685 minItems: 8
686 interrupt-names:
687 items:
688 - const: msi0
689 - const: msi1
690 - const: msi2
691 - const: msi3
692 - const: msi4
693 - const: msi5
694 - const: msi6
695 - const: msi7
696
697 - if:
698 properties:
699 compatible:
700 contains:
701 enum:
702 - qcom,pcie-sc8280xp
703 then:
704 properties:
705 interrupts:
706 minItems: 4
707 maxItems: 4
708 interrupt-names:
709 items:
710 - const: msi0
711 - const: msi1
712 - const: msi2
713 - const: msi3
714
715 - if:
716 properties:
717 compatible:
718 contains:
719 enum:
720 - qcom,pcie-apq8064
721 - qcom,pcie-apq8084
722 - qcom,pcie-ipq4019
723 - qcom,pcie-ipq6018
724 - qcom,pcie-ipq8064
725 - qcom,pcie-ipq8064-v2
726 - qcom,pcie-ipq8074
727 - qcom,pcie-qcs404
728 - qcom,pcie-sa8540p
729 then:
730 properties:
731 interrupts:
732 maxItems: 1
733 interrupt-names:
734 items:
735 - const: msi
736
737unevaluatedProperties: false
738
739examples:
740 - |
741 #include <dt-bindings/interrupt-controller/arm-gic.h>
742 pcie@1b500000 {
743 compatible = "qcom,pcie-ipq8064";
744 reg = <0x1b500000 0x1000>,
745 <0x1b502000 0x80>,
746 <0x1b600000 0x100>,
747 <0x0ff00000 0x100000>;
748 reg-names = "dbi", "elbi", "parf", "config";
749 device_type = "pci";
750 linux,pci-domain = <0>;
751 bus-range = <0x00 0xff>;
752 num-lanes = <1>;
753 #address-cells = <3>;
754 #size-cells = <2>;
755 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
756 <0x82000000 0 0 0x08000000 0 0x07e00000>;
757 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
758 interrupt-names = "msi";
759 #interrupt-cells = <1>;
760 interrupt-map-mask = <0 0 0 0x7>;
761 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
762 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
763 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
764 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&gcc 41>,
766 <&gcc 43>,
767 <&gcc 44>,
768 <&gcc 42>,
769 <&gcc 248>;
770 clock-names = "core", "iface", "phy", "aux", "ref";
771 resets = <&gcc 27>,
772 <&gcc 26>,
773 <&gcc 25>,
774 <&gcc 24>,
775 <&gcc 23>,
776 <&gcc 22>;
777 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
778 pinctrl-0 = <&pcie_pins_default>;
779 pinctrl-names = "default";
780 vdda-supply = <&pm8921_s3>;
781 vdda_phy-supply = <&pm8921_lvs6>;
782 vdda_refclk-supply = <&ext_3p3v>;
783 };
784 - |
785 #include <dt-bindings/interrupt-controller/arm-gic.h>
786 #include <dt-bindings/gpio/gpio.h>
787 pcie@fc520000 {
788 compatible = "qcom,pcie-apq8084";
789 reg = <0xfc520000 0x2000>,
790 <0xff000000 0x1000>,
791 <0xff001000 0x1000>,
792 <0xff002000 0x2000>;
793 reg-names = "parf", "dbi", "elbi", "config";
794 device_type = "pci";
795 linux,pci-domain = <0>;
796 bus-range = <0x00 0xff>;
797 num-lanes = <1>;
798 #address-cells = <3>;
799 #size-cells = <2>;
800 ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
801 <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
802 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
803 interrupt-names = "msi";
804 #interrupt-cells = <1>;
805 interrupt-map-mask = <0 0 0 0x7>;
806 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
807 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
808 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
809 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&gcc 324>,
811 <&gcc 325>,
812 <&gcc 327>,
813 <&gcc 323>;
814 clock-names = "iface", "master_bus", "slave_bus", "aux";
815 resets = <&gcc 81>;
816 reset-names = "core";
817 power-domains = <&gcc 1>;
818 vdda-supply = <&pma8084_l3>;
819 phys = <&pciephy0>;
820 phy-names = "pciephy";
821 perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
822 pinctrl-0 = <&pcie0_pins_default>;
823 pinctrl-names = "default";
824 };
825...