tjh.dev
Linux kernel mirror (for testing)
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kernel
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linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/err.h>
9#include <linux/io.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14#include <linux/phy/phy.h>
15#include <linux/platform_device.h>
16#include <linux/regmap.h>
17#include <linux/regulator/consumer.h>
18#include <linux/reset.h>
19#include <linux/slab.h>
20
21#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
22#define SLEEPM BIT(0)
23#define OPMODE_MASK GENMASK(4, 3)
24#define OPMODE_NORMAL (0x00)
25#define OPMODE_NONDRIVING BIT(3)
26#define TERMSEL BIT(5)
27
28#define USB2_PHY_USB_PHY_UTMI_CTRL1 (0x40)
29#define XCVRSEL BIT(0)
30
31#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50)
32#define POR BIT(1)
33
34#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
35#define SIDDQ BIT(2)
36#define RETENABLEN BIT(3)
37#define FSEL_MASK GENMASK(6, 4)
38#define FSEL_DEFAULT (0x3 << 4)
39
40#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
41#define VBUSVLDEXTSEL0 BIT(4)
42#define PLLBTUNE BIT(5)
43
44#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c)
45#define VREGBYPASS BIT(0)
46
47#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60)
48#define VBUSVLDEXT0 BIT(0)
49
50#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64)
51#define USB2_AUTO_RESUME BIT(0)
52#define USB2_SUSPEND_N BIT(2)
53#define USB2_SUSPEND_N_SEL BIT(3)
54
55#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0 (0x6c)
56#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1 (0x70)
57#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2 (0x74)
58#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3 (0x78)
59#define PARAM_OVRD_MASK 0xFF
60
61#define USB2_PHY_USB_PHY_CFG0 (0x94)
62#define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0)
63#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
64
65#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0)
66#define REFCLK_SEL_MASK GENMASK(1, 0)
67#define REFCLK_SEL_DEFAULT (0x2 << 0)
68
69#define HS_DISCONNECT_MASK GENMASK(2, 0)
70#define SQUELCH_DETECTOR_MASK GENMASK(7, 5)
71
72#define HS_AMPLITUDE_MASK GENMASK(3, 0)
73#define PREEMPHASIS_DURATION_MASK BIT(5)
74#define PREEMPHASIS_AMPLITUDE_MASK GENMASK(7, 6)
75
76#define HS_RISE_FALL_MASK GENMASK(1, 0)
77#define HS_CROSSOVER_VOLTAGE_MASK GENMASK(3, 2)
78#define HS_OUTPUT_IMPEDANCE_MASK GENMASK(5, 4)
79
80#define LS_FS_OUTPUT_IMPEDANCE_MASK GENMASK(3, 0)
81
82static const char * const qcom_snps_hsphy_vreg_names[] = {
83 "vdda-pll", "vdda33", "vdda18",
84};
85
86#define SNPS_HS_NUM_VREGS ARRAY_SIZE(qcom_snps_hsphy_vreg_names)
87
88struct override_param {
89 s32 value;
90 u8 reg_val;
91};
92
93struct override_param_map {
94 const char *prop_name;
95 const struct override_param *param_table;
96 u8 table_size;
97 u8 reg_offset;
98 u8 param_mask;
99};
100
101struct phy_override_seq {
102 bool need_update;
103 u8 offset;
104 u8 value;
105 u8 mask;
106};
107
108#define NUM_HSPHY_TUNING_PARAMS (9)
109
110/**
111 * struct qcom_snps_hsphy - snps hs phy attributes
112 *
113 * @phy: generic phy
114 * @base: iomapped memory space for snps hs phy
115 *
116 * @cfg_ahb_clk: AHB2PHY interface clock
117 * @ref_clk: phy reference clock
118 * @iface_clk: phy interface clock
119 * @phy_reset: phy reset control
120 * @vregs: regulator supplies bulk data
121 * @phy_initialized: if PHY has been initialized correctly
122 * @mode: contains the current mode the PHY is in
123 */
124struct qcom_snps_hsphy {
125 struct phy *phy;
126 void __iomem *base;
127
128 struct clk *cfg_ahb_clk;
129 struct clk *ref_clk;
130 struct reset_control *phy_reset;
131 struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS];
132
133 bool phy_initialized;
134 enum phy_mode mode;
135 struct phy_override_seq update_seq_cfg[NUM_HSPHY_TUNING_PARAMS];
136};
137
138static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
139 u32 mask, u32 val)
140{
141 u32 reg;
142
143 reg = readl_relaxed(base + offset);
144 reg &= ~mask;
145 reg |= val & mask;
146 writel_relaxed(reg, base + offset);
147
148 /* Ensure above write is completed */
149 readl_relaxed(base + offset);
150}
151
152static int qcom_snps_hsphy_suspend(struct qcom_snps_hsphy *hsphy)
153{
154 dev_dbg(&hsphy->phy->dev, "Suspend QCOM SNPS PHY\n");
155
156 if (hsphy->mode == PHY_MODE_USB_HOST) {
157 /* Enable auto-resume to meet remote wakeup timing */
158 qcom_snps_hsphy_write_mask(hsphy->base,
159 USB2_PHY_USB_PHY_HS_PHY_CTRL2,
160 USB2_AUTO_RESUME,
161 USB2_AUTO_RESUME);
162 usleep_range(500, 1000);
163 qcom_snps_hsphy_write_mask(hsphy->base,
164 USB2_PHY_USB_PHY_HS_PHY_CTRL2,
165 0, USB2_AUTO_RESUME);
166 }
167
168 clk_disable_unprepare(hsphy->cfg_ahb_clk);
169 return 0;
170}
171
172static int qcom_snps_hsphy_resume(struct qcom_snps_hsphy *hsphy)
173{
174 int ret;
175
176 dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n");
177
178 ret = clk_prepare_enable(hsphy->cfg_ahb_clk);
179 if (ret) {
180 dev_err(&hsphy->phy->dev, "failed to enable cfg ahb clock\n");
181 return ret;
182 }
183
184 return 0;
185}
186
187static int __maybe_unused qcom_snps_hsphy_runtime_suspend(struct device *dev)
188{
189 struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);
190
191 if (!hsphy->phy_initialized)
192 return 0;
193
194 qcom_snps_hsphy_suspend(hsphy);
195 return 0;
196}
197
198static int __maybe_unused qcom_snps_hsphy_runtime_resume(struct device *dev)
199{
200 struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);
201
202 if (!hsphy->phy_initialized)
203 return 0;
204
205 qcom_snps_hsphy_resume(hsphy);
206 return 0;
207}
208
209static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode,
210 int submode)
211{
212 struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
213
214 hsphy->mode = mode;
215 return 0;
216}
217
218static const struct override_param hs_disconnect_sc7280[] = {
219 { -272, 0 },
220 { 0, 1 },
221 { 317, 2 },
222 { 630, 3 },
223 { 973, 4 },
224 { 1332, 5 },
225 { 1743, 6 },
226 { 2156, 7 },
227};
228
229static const struct override_param squelch_det_threshold_sc7280[] = {
230 { -2090, 7 },
231 { -1560, 6 },
232 { -1030, 5 },
233 { -530, 4 },
234 { 0, 3 },
235 { 530, 2 },
236 { 1060, 1 },
237 { 1590, 0 },
238};
239
240static const struct override_param hs_amplitude_sc7280[] = {
241 { -660, 0 },
242 { -440, 1 },
243 { -220, 2 },
244 { 0, 3 },
245 { 230, 4 },
246 { 440, 5 },
247 { 650, 6 },
248 { 890, 7 },
249 { 1110, 8 },
250 { 1330, 9 },
251 { 1560, 10 },
252 { 1780, 11 },
253 { 2000, 12 },
254 { 2220, 13 },
255 { 2430, 14 },
256 { 2670, 15 },
257};
258
259static const struct override_param preemphasis_duration_sc7280[] = {
260 { 10000, 1 },
261 { 20000, 0 },
262};
263
264static const struct override_param preemphasis_amplitude_sc7280[] = {
265 { 10000, 1 },
266 { 20000, 2 },
267 { 30000, 3 },
268 { 40000, 0 },
269};
270
271static const struct override_param hs_rise_fall_time_sc7280[] = {
272 { -4100, 3 },
273 { 0, 2 },
274 { 2810, 1 },
275 { 5430, 0 },
276};
277
278static const struct override_param hs_crossover_voltage_sc7280[] = {
279 { -31000, 1 },
280 { 0, 3 },
281 { 28000, 2 },
282};
283
284static const struct override_param hs_output_impedance_sc7280[] = {
285 { -2300000, 3 },
286 { 0, 2 },
287 { 2600000, 1 },
288 { 6100000, 0 },
289};
290
291static const struct override_param ls_fs_output_impedance_sc7280[] = {
292 { -1053, 15 },
293 { -557, 7 },
294 { 0, 3 },
295 { 612, 1 },
296 { 1310, 0 },
297};
298
299static const struct override_param_map sc7280_snps_7nm_phy[] = {
300 {
301 "qcom,hs-disconnect-bp",
302 hs_disconnect_sc7280,
303 ARRAY_SIZE(hs_disconnect_sc7280),
304 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0,
305 HS_DISCONNECT_MASK
306 },
307 {
308 "qcom,squelch-detector-bp",
309 squelch_det_threshold_sc7280,
310 ARRAY_SIZE(squelch_det_threshold_sc7280),
311 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0,
312 SQUELCH_DETECTOR_MASK
313 },
314 {
315 "qcom,hs-amplitude-bp",
316 hs_amplitude_sc7280,
317 ARRAY_SIZE(hs_amplitude_sc7280),
318 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1,
319 HS_AMPLITUDE_MASK
320 },
321 {
322 "qcom,pre-emphasis-duration-bp",
323 preemphasis_duration_sc7280,
324 ARRAY_SIZE(preemphasis_duration_sc7280),
325 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1,
326 PREEMPHASIS_DURATION_MASK,
327 },
328 {
329 "qcom,pre-emphasis-amplitude-bp",
330 preemphasis_amplitude_sc7280,
331 ARRAY_SIZE(preemphasis_amplitude_sc7280),
332 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1,
333 PREEMPHASIS_AMPLITUDE_MASK,
334 },
335 {
336 "qcom,hs-rise-fall-time-bp",
337 hs_rise_fall_time_sc7280,
338 ARRAY_SIZE(hs_rise_fall_time_sc7280),
339 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2,
340 HS_RISE_FALL_MASK
341 },
342 {
343 "qcom,hs-crossover-voltage-microvolt",
344 hs_crossover_voltage_sc7280,
345 ARRAY_SIZE(hs_crossover_voltage_sc7280),
346 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2,
347 HS_CROSSOVER_VOLTAGE_MASK
348 },
349 {
350 "qcom,hs-output-impedance-micro-ohms",
351 hs_output_impedance_sc7280,
352 ARRAY_SIZE(hs_output_impedance_sc7280),
353 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2,
354 HS_OUTPUT_IMPEDANCE_MASK,
355 },
356 {
357 "qcom,ls-fs-output-impedance-bp",
358 ls_fs_output_impedance_sc7280,
359 ARRAY_SIZE(ls_fs_output_impedance_sc7280),
360 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3,
361 LS_FS_OUTPUT_IMPEDANCE_MASK,
362 },
363 {},
364};
365
366static int qcom_snps_hsphy_init(struct phy *phy)
367{
368 struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
369 int ret, i;
370
371 dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__);
372
373 ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
374 if (ret)
375 return ret;
376
377 ret = clk_prepare_enable(hsphy->cfg_ahb_clk);
378 if (ret) {
379 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
380 goto poweroff_phy;
381 }
382
383 ret = reset_control_assert(hsphy->phy_reset);
384 if (ret) {
385 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
386 goto disable_ahb_clk;
387 }
388
389 usleep_range(100, 150);
390
391 ret = reset_control_deassert(hsphy->phy_reset);
392 if (ret) {
393 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
394 goto disable_ahb_clk;
395 }
396
397 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
398 UTMI_PHY_CMN_CTRL_OVERRIDE_EN,
399 UTMI_PHY_CMN_CTRL_OVERRIDE_EN);
400 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
401 POR, POR);
402 qcom_snps_hsphy_write_mask(hsphy->base,
403 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
404 FSEL_MASK, 0);
405 qcom_snps_hsphy_write_mask(hsphy->base,
406 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
407 PLLBTUNE, PLLBTUNE);
408 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL,
409 REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK);
410 qcom_snps_hsphy_write_mask(hsphy->base,
411 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
412 VBUSVLDEXTSEL0, VBUSVLDEXTSEL0);
413 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,
414 VBUSVLDEXT0, VBUSVLDEXT0);
415
416 for (i = 0; i < ARRAY_SIZE(hsphy->update_seq_cfg); i++) {
417 if (hsphy->update_seq_cfg[i].need_update)
418 qcom_snps_hsphy_write_mask(hsphy->base,
419 hsphy->update_seq_cfg[i].offset,
420 hsphy->update_seq_cfg[i].mask,
421 hsphy->update_seq_cfg[i].value);
422 }
423
424 qcom_snps_hsphy_write_mask(hsphy->base,
425 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2,
426 VREGBYPASS, VREGBYPASS);
427
428 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
429 USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
430 USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
431
432 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0,
433 SLEEPM, SLEEPM);
434
435 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
436 SIDDQ, 0);
437
438 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
439 POR, 0);
440
441 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
442 USB2_SUSPEND_N_SEL, 0);
443
444 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
445 UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0);
446
447 hsphy->phy_initialized = true;
448
449 return 0;
450
451disable_ahb_clk:
452 clk_disable_unprepare(hsphy->cfg_ahb_clk);
453poweroff_phy:
454 regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
455
456 return ret;
457}
458
459static int qcom_snps_hsphy_exit(struct phy *phy)
460{
461 struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
462
463 reset_control_assert(hsphy->phy_reset);
464 clk_disable_unprepare(hsphy->cfg_ahb_clk);
465 regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
466 hsphy->phy_initialized = false;
467
468 return 0;
469}
470
471static const struct phy_ops qcom_snps_hsphy_gen_ops = {
472 .init = qcom_snps_hsphy_init,
473 .exit = qcom_snps_hsphy_exit,
474 .set_mode = qcom_snps_hsphy_set_mode,
475 .owner = THIS_MODULE,
476};
477
478static const struct of_device_id qcom_snps_hsphy_of_match_table[] = {
479 { .compatible = "qcom,sm8150-usb-hs-phy", },
480 { .compatible = "qcom,usb-snps-hs-5nm-phy", },
481 {
482 .compatible = "qcom,usb-snps-hs-7nm-phy",
483 .data = &sc7280_snps_7nm_phy,
484 },
485 { .compatible = "qcom,usb-snps-femto-v2-phy", },
486 { }
487};
488MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table);
489
490static const struct dev_pm_ops qcom_snps_hsphy_pm_ops = {
491 SET_RUNTIME_PM_OPS(qcom_snps_hsphy_runtime_suspend,
492 qcom_snps_hsphy_runtime_resume, NULL)
493};
494
495static void qcom_snps_hsphy_override_param_update_val(
496 const struct override_param_map map,
497 s32 dt_val, struct phy_override_seq *seq_entry)
498{
499 int i;
500
501 /*
502 * Param table for each param is in increasing order
503 * of dt values. We need to iterate over the list to
504 * select the entry that matches the dt value and pick
505 * up the corresponding register value.
506 */
507 for (i = 0; i < map.table_size - 1; i++) {
508 if (map.param_table[i].value == dt_val)
509 break;
510 }
511
512 seq_entry->need_update = true;
513 seq_entry->offset = map.reg_offset;
514 seq_entry->mask = map.param_mask;
515 seq_entry->value = map.param_table[i].reg_val << __ffs(map.param_mask);
516}
517
518static void qcom_snps_hsphy_read_override_param_seq(struct device *dev)
519{
520 struct device_node *node = dev->of_node;
521 s32 val;
522 int ret, i;
523 struct qcom_snps_hsphy *hsphy;
524 const struct override_param_map *cfg = of_device_get_match_data(dev);
525
526 if (!cfg)
527 return;
528
529 hsphy = dev_get_drvdata(dev);
530
531 for (i = 0; cfg[i].prop_name != NULL; i++) {
532 ret = of_property_read_s32(node, cfg[i].prop_name, &val);
533 if (ret)
534 continue;
535
536 qcom_snps_hsphy_override_param_update_val(cfg[i], val,
537 &hsphy->update_seq_cfg[i]);
538 dev_dbg(&hsphy->phy->dev, "Read param: %s dt_val: %d reg_val: 0x%x\n",
539 cfg[i].prop_name, val, hsphy->update_seq_cfg[i].value);
540
541 }
542}
543
544static int qcom_snps_hsphy_probe(struct platform_device *pdev)
545{
546 struct device *dev = &pdev->dev;
547 struct qcom_snps_hsphy *hsphy;
548 struct phy_provider *phy_provider;
549 struct phy *generic_phy;
550 int ret, i;
551 int num;
552
553 hsphy = devm_kzalloc(dev, sizeof(*hsphy), GFP_KERNEL);
554 if (!hsphy)
555 return -ENOMEM;
556
557 hsphy->base = devm_platform_ioremap_resource(pdev, 0);
558 if (IS_ERR(hsphy->base))
559 return PTR_ERR(hsphy->base);
560
561 hsphy->ref_clk = devm_clk_get(dev, "ref");
562 if (IS_ERR(hsphy->ref_clk))
563 return dev_err_probe(dev, PTR_ERR(hsphy->ref_clk),
564 "failed to get ref clk\n");
565
566 hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
567 if (IS_ERR(hsphy->phy_reset)) {
568 dev_err(dev, "failed to get phy core reset\n");
569 return PTR_ERR(hsphy->phy_reset);
570 }
571
572 num = ARRAY_SIZE(hsphy->vregs);
573 for (i = 0; i < num; i++)
574 hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i];
575
576 ret = devm_regulator_bulk_get(dev, num, hsphy->vregs);
577 if (ret)
578 return dev_err_probe(dev, ret,
579 "failed to get regulator supplies\n");
580
581 pm_runtime_set_active(dev);
582 pm_runtime_enable(dev);
583 /*
584 * Prevent runtime pm from being ON by default. Users can enable
585 * it using power/control in sysfs.
586 */
587 pm_runtime_forbid(dev);
588
589 generic_phy = devm_phy_create(dev, NULL, &qcom_snps_hsphy_gen_ops);
590 if (IS_ERR(generic_phy)) {
591 ret = PTR_ERR(generic_phy);
592 dev_err(dev, "failed to create phy, %d\n", ret);
593 return ret;
594 }
595 hsphy->phy = generic_phy;
596
597 dev_set_drvdata(dev, hsphy);
598 phy_set_drvdata(generic_phy, hsphy);
599 qcom_snps_hsphy_read_override_param_seq(dev);
600
601 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
602 if (!IS_ERR(phy_provider))
603 dev_dbg(dev, "Registered Qcom-SNPS HS phy\n");
604 else
605 pm_runtime_disable(dev);
606
607 return PTR_ERR_OR_ZERO(phy_provider);
608}
609
610static struct platform_driver qcom_snps_hsphy_driver = {
611 .probe = qcom_snps_hsphy_probe,
612 .driver = {
613 .name = "qcom-snps-hs-femto-v2-phy",
614 .pm = &qcom_snps_hsphy_pm_ops,
615 .of_match_table = qcom_snps_hsphy_of_match_table,
616 },
617};
618
619module_platform_driver(qcom_snps_hsphy_driver);
620
621MODULE_DESCRIPTION("Qualcomm SNPS FEMTO USB HS PHY V2 driver");
622MODULE_LICENSE("GPL v2");