Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright 2014, Michael Ellerman, IBM Corp.
4 */
5
6#ifndef _SELFTESTS_POWERPC_REG_H
7#define _SELFTESTS_POWERPC_REG_H
8
9#define __stringify_1(x) #x
10#define __stringify(x) __stringify_1(x)
11
12#define mfspr(rn) ({unsigned long rval; \
13 asm volatile("mfspr %0," _str(rn) \
14 : "=r" (rval)); rval; })
15#define mtspr(rn, v) asm volatile("mtspr " _str(rn) ",%0" : \
16 : "r" ((unsigned long)(v)) \
17 : "memory")
18
19#define mb() asm volatile("sync" : : : "memory");
20#define barrier() asm volatile("" : : : "memory");
21
22#define SPRN_MMCR2 769
23#define SPRN_MMCRA 770
24#define SPRN_MMCR0 779
25#define MMCR0_PMAO 0x00000080
26#define MMCR0_PMAE 0x04000000
27#define MMCR0_FC 0x80000000
28#define SPRN_EBBHR 804
29#define SPRN_EBBRR 805
30#define SPRN_BESCR 806 /* Branch event status & control register */
31#define SPRN_BESCRS 800 /* Branch event status & control set (1 bits set to 1) */
32#define SPRN_BESCRSU 801 /* Branch event status & control set upper */
33#define SPRN_BESCRR 802 /* Branch event status & control REset (1 bits set to 0) */
34#define SPRN_BESCRRU 803 /* Branch event status & control REset upper */
35
36#define BESCR_PMEO 0x1 /* PMU Event-based exception Occurred */
37#define BESCR_PME (0x1ul << 32) /* PMU Event-based exception Enable */
38
39#define SPRN_PMC1 771
40#define SPRN_PMC2 772
41#define SPRN_PMC3 773
42#define SPRN_PMC4 774
43#define SPRN_PMC5 775
44#define SPRN_PMC6 776
45
46#define SPRN_SIAR 780
47#define SPRN_SDAR 781
48#define SPRN_SIER 768
49
50#define SPRN_TEXASR 0x82 /* Transaction Exception and Status Register */
51#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
52#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
53#define SPRN_TAR 0x32f /* Target Address Register */
54
55#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF)
56#define SPRN_PVR 0x11F
57
58#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
59#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
60#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
61
62#define SPRN_DSCR_PRIV 0x11 /* Privilege State DSCR */
63#define SPRN_DSCR 0x03 /* Data Stream Control Register */
64#define SPRN_PPR 896 /* Program Priority Register */
65#define SPRN_AMR 13 /* Authority Mask Register - problem state */
66
67#define set_amr(v) asm volatile("isync;" \
68 "mtspr " __stringify(SPRN_AMR) ",%0;" \
69 "isync" : \
70 : "r" ((unsigned long)(v)) \
71 : "memory")
72
73/* TEXASR register bits */
74#define TEXASR_FC 0xFE00000000000000
75#define TEXASR_FP 0x0100000000000000
76#define TEXASR_DA 0x0080000000000000
77#define TEXASR_NO 0x0040000000000000
78#define TEXASR_FO 0x0020000000000000
79#define TEXASR_SIC 0x0010000000000000
80#define TEXASR_NTC 0x0008000000000000
81#define TEXASR_TC 0x0004000000000000
82#define TEXASR_TIC 0x0002000000000000
83#define TEXASR_IC 0x0001000000000000
84#define TEXASR_IFC 0x0000800000000000
85#define TEXASR_ABT 0x0000000100000000
86#define TEXASR_SPD 0x0000000080000000
87#define TEXASR_HV 0x0000000020000000
88#define TEXASR_PR 0x0000000010000000
89#define TEXASR_FS 0x0000000008000000
90#define TEXASR_TE 0x0000000004000000
91#define TEXASR_ROT 0x0000000002000000
92
93/* MSR register bits */
94#define MSR_HV (1ul << 60) /* Hypervisor state */
95#define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */
96#define MSR_TS_T_LG 34 /* Trans Mem state: Active */
97
98#define __MASK(X) (1UL<<(X))
99
100/* macro to check TM MSR bits */
101#define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */
102#define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */
103
104/* Vector Instructions */
105#define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) | \
106 ((rb) << 11) | (((xs) >> 5)))
107#define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
108#define LXVD2X(xs, ra, rb) .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
109
110#define ASM_LOAD_GPR_IMMED(_asm_symbol_name_immed) \
111 "li 14, %[" #_asm_symbol_name_immed "];" \
112 "li 15, %[" #_asm_symbol_name_immed "];" \
113 "li 16, %[" #_asm_symbol_name_immed "];" \
114 "li 17, %[" #_asm_symbol_name_immed "];" \
115 "li 18, %[" #_asm_symbol_name_immed "];" \
116 "li 19, %[" #_asm_symbol_name_immed "];" \
117 "li 20, %[" #_asm_symbol_name_immed "];" \
118 "li 21, %[" #_asm_symbol_name_immed "];" \
119 "li 22, %[" #_asm_symbol_name_immed "];" \
120 "li 23, %[" #_asm_symbol_name_immed "];" \
121 "li 24, %[" #_asm_symbol_name_immed "];" \
122 "li 25, %[" #_asm_symbol_name_immed "];" \
123 "li 26, %[" #_asm_symbol_name_immed "];" \
124 "li 27, %[" #_asm_symbol_name_immed "];" \
125 "li 28, %[" #_asm_symbol_name_immed "];" \
126 "li 29, %[" #_asm_symbol_name_immed "];" \
127 "li 30, %[" #_asm_symbol_name_immed "];" \
128 "li 31, %[" #_asm_symbol_name_immed "];"
129
130#define ASM_LOAD_FPR(_asm_symbol_name_addr) \
131 "lfd 0, 0(%[" #_asm_symbol_name_addr "]);" \
132 "lfd 1, 0(%[" #_asm_symbol_name_addr "]);" \
133 "lfd 2, 0(%[" #_asm_symbol_name_addr "]);" \
134 "lfd 3, 0(%[" #_asm_symbol_name_addr "]);" \
135 "lfd 4, 0(%[" #_asm_symbol_name_addr "]);" \
136 "lfd 5, 0(%[" #_asm_symbol_name_addr "]);" \
137 "lfd 6, 0(%[" #_asm_symbol_name_addr "]);" \
138 "lfd 7, 0(%[" #_asm_symbol_name_addr "]);" \
139 "lfd 8, 0(%[" #_asm_symbol_name_addr "]);" \
140 "lfd 9, 0(%[" #_asm_symbol_name_addr "]);" \
141 "lfd 10, 0(%[" #_asm_symbol_name_addr "]);" \
142 "lfd 11, 0(%[" #_asm_symbol_name_addr "]);" \
143 "lfd 12, 0(%[" #_asm_symbol_name_addr "]);" \
144 "lfd 13, 0(%[" #_asm_symbol_name_addr "]);" \
145 "lfd 14, 0(%[" #_asm_symbol_name_addr "]);" \
146 "lfd 15, 0(%[" #_asm_symbol_name_addr "]);" \
147 "lfd 16, 0(%[" #_asm_symbol_name_addr "]);" \
148 "lfd 17, 0(%[" #_asm_symbol_name_addr "]);" \
149 "lfd 18, 0(%[" #_asm_symbol_name_addr "]);" \
150 "lfd 19, 0(%[" #_asm_symbol_name_addr "]);" \
151 "lfd 20, 0(%[" #_asm_symbol_name_addr "]);" \
152 "lfd 21, 0(%[" #_asm_symbol_name_addr "]);" \
153 "lfd 22, 0(%[" #_asm_symbol_name_addr "]);" \
154 "lfd 23, 0(%[" #_asm_symbol_name_addr "]);" \
155 "lfd 24, 0(%[" #_asm_symbol_name_addr "]);" \
156 "lfd 25, 0(%[" #_asm_symbol_name_addr "]);" \
157 "lfd 26, 0(%[" #_asm_symbol_name_addr "]);" \
158 "lfd 27, 0(%[" #_asm_symbol_name_addr "]);" \
159 "lfd 28, 0(%[" #_asm_symbol_name_addr "]);" \
160 "lfd 29, 0(%[" #_asm_symbol_name_addr "]);" \
161 "lfd 30, 0(%[" #_asm_symbol_name_addr "]);" \
162 "lfd 31, 0(%[" #_asm_symbol_name_addr "]);"
163
164#ifndef __ASSEMBLER__
165void store_gpr(unsigned long *addr);
166void load_gpr(unsigned long *addr);
167void store_fpr(double *addr);
168#endif /* end of __ASSEMBLER__ */
169
170#endif /* _SELFTESTS_POWERPC_REG_H */