Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// Copyright(c) 2020 Intel Corporation. All rights reserved.
4//
5// Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
6//
7
8/*
9 * Hardware interface for audio DSP on Tigerlake.
10 */
11
12#include <sound/sof/ext_manifest4.h>
13#include "../ipc4-priv.h"
14#include "../ops.h"
15#include "hda.h"
16#include "hda-ipc.h"
17#include "../sof-audio.h"
18
19static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
20 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
21 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
22 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
23};
24
25static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)
26{
27 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
28
29 /* power up primary core if not already powered up and return */
30 if (core == SOF_DSP_PRIMARY_CORE)
31 return hda_dsp_enable_core(sdev, BIT(core));
32
33 if (pm_ops->set_core_state)
34 return pm_ops->set_core_state(sdev, core, true);
35
36 return 0;
37}
38
39static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
40{
41 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
42
43 /* power down primary core and return */
44 if (core == SOF_DSP_PRIMARY_CORE)
45 return hda_dsp_core_reset_power_down(sdev, BIT(core));
46
47 if (pm_ops->set_core_state)
48 return pm_ops->set_core_state(sdev, core, false);
49
50 return 0;
51}
52
53/* Tigerlake ops */
54struct snd_sof_dsp_ops sof_tgl_ops;
55EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
56
57int sof_tgl_ops_init(struct snd_sof_dev *sdev)
58{
59 /* common defaults */
60 memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
61
62 /* probe/remove/shutdown */
63 sof_tgl_ops.shutdown = hda_dsp_shutdown;
64
65 if (sdev->pdata->ipc_type == SOF_IPC) {
66 /* doorbell */
67 sof_tgl_ops.irq_thread = cnl_ipc_irq_thread;
68
69 /* ipc */
70 sof_tgl_ops.send_msg = cnl_ipc_send_msg;
71 }
72
73 if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
74 struct sof_ipc4_fw_data *ipc4_data;
75
76 sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
77 if (!sdev->private)
78 return -ENOMEM;
79
80 ipc4_data = sdev->private;
81 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
82
83 /* doorbell */
84 sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread;
85
86 /* ipc */
87 sof_tgl_ops.send_msg = cnl_ipc4_send_msg;
88 }
89
90 /* set DAI driver ops */
91 hda_set_dai_drv_ops(sdev, &sof_tgl_ops);
92
93 /* debug */
94 sof_tgl_ops.debug_map = tgl_dsp_debugfs;
95 sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs);
96 sof_tgl_ops.ipc_dump = cnl_ipc_dump;
97
98 /* pre/post fw run */
99 sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run;
100
101 /* firmware run */
102 sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax;
103
104 /* dsp core get/put */
105 sof_tgl_ops.core_get = tgl_dsp_core_get;
106 sof_tgl_ops.core_put = tgl_dsp_core_put;
107
108 return 0;
109};
110EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
111
112const struct sof_intel_dsp_desc tgl_chip_info = {
113 /* Tigerlake , Alderlake */
114 .cores_num = 4,
115 .init_core_mask = 1,
116 .host_managed_cores_mask = BIT(0),
117 .ipc_req = CNL_DSP_REG_HIPCIDR,
118 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
119 .ipc_ack = CNL_DSP_REG_HIPCIDA,
120 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
121 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
122 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
123 .rom_init_timeout = 300,
124 .ssp_count = ICL_SSP_COUNT,
125 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
126 .sdw_shim_base = SDW_SHIM_BASE,
127 .sdw_alh_base = SDW_ALH_BASE,
128 .check_sdw_irq = hda_common_check_sdw_irq,
129 .check_ipc_irq = hda_dsp_check_ipc_irq,
130 .cl_init = cl_dsp_init,
131 .hw_ip_version = SOF_INTEL_CAVS_2_5,
132};
133EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
134
135const struct sof_intel_dsp_desc tglh_chip_info = {
136 /* Tigerlake-H */
137 .cores_num = 2,
138 .init_core_mask = 1,
139 .host_managed_cores_mask = BIT(0),
140 .ipc_req = CNL_DSP_REG_HIPCIDR,
141 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
142 .ipc_ack = CNL_DSP_REG_HIPCIDA,
143 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
144 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
145 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
146 .rom_init_timeout = 300,
147 .ssp_count = ICL_SSP_COUNT,
148 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
149 .sdw_shim_base = SDW_SHIM_BASE,
150 .sdw_alh_base = SDW_ALH_BASE,
151 .check_sdw_irq = hda_common_check_sdw_irq,
152 .check_ipc_irq = hda_dsp_check_ipc_irq,
153 .cl_init = cl_dsp_init,
154 .hw_ip_version = SOF_INTEL_CAVS_2_5,
155};
156EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
157
158const struct sof_intel_dsp_desc ehl_chip_info = {
159 /* Elkhartlake */
160 .cores_num = 4,
161 .init_core_mask = 1,
162 .host_managed_cores_mask = BIT(0),
163 .ipc_req = CNL_DSP_REG_HIPCIDR,
164 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
165 .ipc_ack = CNL_DSP_REG_HIPCIDA,
166 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
167 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
168 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
169 .rom_init_timeout = 300,
170 .ssp_count = ICL_SSP_COUNT,
171 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
172 .sdw_shim_base = SDW_SHIM_BASE,
173 .sdw_alh_base = SDW_ALH_BASE,
174 .check_sdw_irq = hda_common_check_sdw_irq,
175 .check_ipc_irq = hda_dsp_check_ipc_irq,
176 .cl_init = cl_dsp_init,
177 .hw_ip_version = SOF_INTEL_CAVS_2_5,
178};
179EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
180
181const struct sof_intel_dsp_desc adls_chip_info = {
182 /* Alderlake-S */
183 .cores_num = 2,
184 .init_core_mask = BIT(0),
185 .host_managed_cores_mask = BIT(0),
186 .ipc_req = CNL_DSP_REG_HIPCIDR,
187 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
188 .ipc_ack = CNL_DSP_REG_HIPCIDA,
189 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
190 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
191 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
192 .rom_init_timeout = 300,
193 .ssp_count = ICL_SSP_COUNT,
194 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
195 .sdw_shim_base = SDW_SHIM_BASE,
196 .sdw_alh_base = SDW_ALH_BASE,
197 .check_sdw_irq = hda_common_check_sdw_irq,
198 .check_ipc_irq = hda_dsp_check_ipc_irq,
199 .cl_init = cl_dsp_init,
200 .hw_ip_version = SOF_INTEL_CAVS_2_5,
201};
202EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);