tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2// Copyright 2018 NXP
3
4#include <linux/bitfield.h>
5#include <linux/clk.h>
6#include <linux/device.h>
7#include <linux/interrupt.h>
8#include <linux/kobject.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_address.h>
13#include <linux/of_irq.h>
14#include <linux/of_platform.h>
15#include <linux/pm_runtime.h>
16#include <linux/regmap.h>
17#include <linux/sysfs.h>
18#include <linux/types.h>
19#include <linux/dma/imx-dma.h>
20#include <sound/dmaengine_pcm.h>
21#include <sound/pcm.h>
22#include <sound/soc.h>
23#include <sound/tlv.h>
24#include <sound/core.h>
25
26#include "fsl_micfil.h"
27#include "fsl_utils.h"
28
29#define MICFIL_OSR_DEFAULT 16
30
31enum quality {
32 QUALITY_HIGH,
33 QUALITY_MEDIUM,
34 QUALITY_LOW,
35 QUALITY_VLOW0,
36 QUALITY_VLOW1,
37 QUALITY_VLOW2,
38};
39
40struct fsl_micfil {
41 struct platform_device *pdev;
42 struct regmap *regmap;
43 const struct fsl_micfil_soc_data *soc;
44 struct clk *busclk;
45 struct clk *mclk;
46 struct clk *pll8k_clk;
47 struct clk *pll11k_clk;
48 struct snd_dmaengine_dai_dma_data dma_params_rx;
49 struct sdma_peripheral_config sdmacfg;
50 unsigned int dataline;
51 char name[32];
52 int irq[MICFIL_IRQ_LINES];
53 enum quality quality;
54 int dc_remover;
55};
56
57struct fsl_micfil_soc_data {
58 unsigned int fifos;
59 unsigned int fifo_depth;
60 unsigned int dataline;
61 bool imx;
62 u64 formats;
63};
64
65static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
66 .imx = true,
67 .fifos = 8,
68 .fifo_depth = 8,
69 .dataline = 0xf,
70 .formats = SNDRV_PCM_FMTBIT_S16_LE,
71};
72
73static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {
74 .imx = true,
75 .fifos = 8,
76 .fifo_depth = 32,
77 .dataline = 0xf,
78 .formats = SNDRV_PCM_FMTBIT_S32_LE,
79};
80
81static const struct of_device_id fsl_micfil_dt_ids[] = {
82 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
83 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp },
84 {}
85};
86MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
87
88static const char * const micfil_quality_select_texts[] = {
89 [QUALITY_HIGH] = "High",
90 [QUALITY_MEDIUM] = "Medium",
91 [QUALITY_LOW] = "Low",
92 [QUALITY_VLOW0] = "VLow0",
93 [QUALITY_VLOW1] = "Vlow1",
94 [QUALITY_VLOW2] = "Vlow2",
95};
96
97static const struct soc_enum fsl_micfil_quality_enum =
98 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
99 micfil_quality_select_texts);
100
101static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
102
103static int micfil_set_quality(struct fsl_micfil *micfil)
104{
105 u32 qsel;
106
107 switch (micfil->quality) {
108 case QUALITY_HIGH:
109 qsel = MICFIL_QSEL_HIGH_QUALITY;
110 break;
111 case QUALITY_MEDIUM:
112 qsel = MICFIL_QSEL_MEDIUM_QUALITY;
113 break;
114 case QUALITY_LOW:
115 qsel = MICFIL_QSEL_LOW_QUALITY;
116 break;
117 case QUALITY_VLOW0:
118 qsel = MICFIL_QSEL_VLOW0_QUALITY;
119 break;
120 case QUALITY_VLOW1:
121 qsel = MICFIL_QSEL_VLOW1_QUALITY;
122 break;
123 case QUALITY_VLOW2:
124 qsel = MICFIL_QSEL_VLOW2_QUALITY;
125 break;
126 }
127
128 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
129 MICFIL_CTRL2_QSEL,
130 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
131}
132
133static int micfil_quality_get(struct snd_kcontrol *kcontrol,
134 struct snd_ctl_elem_value *ucontrol)
135{
136 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
137 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
138
139 ucontrol->value.integer.value[0] = micfil->quality;
140
141 return 0;
142}
143
144static int micfil_quality_set(struct snd_kcontrol *kcontrol,
145 struct snd_ctl_elem_value *ucontrol)
146{
147 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
148 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
149
150 micfil->quality = ucontrol->value.integer.value[0];
151
152 return micfil_set_quality(micfil);
153}
154
155static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
156 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
157 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv),
158 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
159 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0x7, gain_tlv),
160 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
161 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0x7, gain_tlv),
162 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
163 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0x7, gain_tlv),
164 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
165 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0x7, gain_tlv),
166 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
167 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0x7, gain_tlv),
168 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
169 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0x7, gain_tlv),
170 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
171 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv),
172 SOC_ENUM_EXT("MICFIL Quality Select",
173 fsl_micfil_quality_enum,
174 micfil_quality_get, micfil_quality_set),
175};
176
177/* The SRES is a self-negated bit which provides the CPU with the
178 * capability to initialize the PDM Interface module through the
179 * slave-bus interface. This bit always reads as zero, and this
180 * bit is only effective when MDIS is cleared
181 */
182static int fsl_micfil_reset(struct device *dev)
183{
184 struct fsl_micfil *micfil = dev_get_drvdata(dev);
185 int ret;
186
187 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
188 MICFIL_CTRL1_MDIS);
189 if (ret)
190 return ret;
191
192 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
193 MICFIL_CTRL1_SRES);
194 if (ret)
195 return ret;
196
197 return 0;
198}
199
200static int fsl_micfil_startup(struct snd_pcm_substream *substream,
201 struct snd_soc_dai *dai)
202{
203 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
204
205 if (!micfil) {
206 dev_err(dai->dev, "micfil dai priv_data not set\n");
207 return -EINVAL;
208 }
209
210 return 0;
211}
212
213static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
214 struct snd_soc_dai *dai)
215{
216 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
217 struct device *dev = &micfil->pdev->dev;
218 int ret;
219
220 switch (cmd) {
221 case SNDRV_PCM_TRIGGER_START:
222 case SNDRV_PCM_TRIGGER_RESUME:
223 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
224 ret = fsl_micfil_reset(dev);
225 if (ret) {
226 dev_err(dev, "failed to soft reset\n");
227 return ret;
228 }
229
230 /* DMA Interrupt Selection - DISEL bits
231 * 00 - DMA and IRQ disabled
232 * 01 - DMA req enabled
233 * 10 - IRQ enabled
234 * 11 - reserved
235 */
236 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
237 MICFIL_CTRL1_DISEL,
238 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
239 if (ret)
240 return ret;
241
242 /* Enable the module */
243 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
244 MICFIL_CTRL1_PDMIEN);
245 if (ret)
246 return ret;
247
248 break;
249 case SNDRV_PCM_TRIGGER_STOP:
250 case SNDRV_PCM_TRIGGER_SUSPEND:
251 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
252 /* Disable the module */
253 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
254 MICFIL_CTRL1_PDMIEN);
255 if (ret)
256 return ret;
257
258 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
259 MICFIL_CTRL1_DISEL,
260 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
261 if (ret)
262 return ret;
263 break;
264 default:
265 return -EINVAL;
266 }
267 return 0;
268}
269
270static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate)
271{
272 struct device *dev = &micfil->pdev->dev;
273 u64 ratio = sample_rate;
274 struct clk *clk;
275 int ret;
276
277 /* Get root clock */
278 clk = micfil->mclk;
279
280 /* Disable clock first, for it was enabled by pm_runtime */
281 clk_disable_unprepare(clk);
282 fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk,
283 micfil->pll11k_clk, ratio);
284 ret = clk_prepare_enable(clk);
285 if (ret)
286 return ret;
287
288 return 0;
289}
290
291static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
292 struct snd_pcm_hw_params *params,
293 struct snd_soc_dai *dai)
294{
295 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
296 unsigned int channels = params_channels(params);
297 unsigned int rate = params_rate(params);
298 int clk_div = 8;
299 int osr = MICFIL_OSR_DEFAULT;
300 int ret;
301
302 /* 1. Disable the module */
303 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
304 MICFIL_CTRL1_PDMIEN);
305 if (ret)
306 return ret;
307
308 /* enable channels */
309 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
310 0xFF, ((1 << channels) - 1));
311 if (ret)
312 return ret;
313
314 ret = fsl_micfil_reparent_rootclk(micfil, rate);
315 if (ret)
316 return ret;
317
318 ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
319 if (ret)
320 return ret;
321
322 ret = micfil_set_quality(micfil);
323 if (ret)
324 return ret;
325
326 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
327 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
328 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
329 FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
330
331 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
332 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
333 micfil->sdmacfg.n_fifos_src = channels;
334 micfil->sdmacfg.sw_done = true;
335 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
336
337 return 0;
338}
339
340static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
341 .startup = fsl_micfil_startup,
342 .trigger = fsl_micfil_trigger,
343 .hw_params = fsl_micfil_hw_params,
344};
345
346static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
347{
348 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
349 struct device *dev = cpu_dai->dev;
350 unsigned int val = 0;
351 int ret, i;
352
353 micfil->quality = QUALITY_VLOW0;
354
355 /* set default gain to 2 */
356 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222);
357
358 /* set DC Remover in bypass mode*/
359 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
360 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
361 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL,
362 MICFIL_DC_CTRL_CONFIG, val);
363 if (ret) {
364 dev_err(dev, "failed to set DC Remover mode bits\n");
365 return ret;
366 }
367 micfil->dc_remover = MICFIL_DC_BYPASS;
368
369 snd_soc_dai_init_dma_data(cpu_dai, NULL,
370 &micfil->dma_params_rx);
371
372 /* FIFO Watermark Control - FIFOWMK*/
373 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
374 MICFIL_FIFO_CTRL_FIFOWMK,
375 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
376 if (ret)
377 return ret;
378
379 return 0;
380}
381
382static struct snd_soc_dai_driver fsl_micfil_dai = {
383 .probe = fsl_micfil_dai_probe,
384 .capture = {
385 .stream_name = "CPU-Capture",
386 .channels_min = 1,
387 .channels_max = 8,
388 .rates = SNDRV_PCM_RATE_8000_48000,
389 .formats = SNDRV_PCM_FMTBIT_S16_LE,
390 },
391 .ops = &fsl_micfil_dai_ops,
392};
393
394static const struct snd_soc_component_driver fsl_micfil_component = {
395 .name = "fsl-micfil-dai",
396 .controls = fsl_micfil_snd_controls,
397 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
398 .legacy_dai_naming = 1,
399};
400
401/* REGMAP */
402static const struct reg_default fsl_micfil_reg_defaults[] = {
403 {REG_MICFIL_CTRL1, 0x00000000},
404 {REG_MICFIL_CTRL2, 0x00000000},
405 {REG_MICFIL_STAT, 0x00000000},
406 {REG_MICFIL_FIFO_CTRL, 0x00000007},
407 {REG_MICFIL_FIFO_STAT, 0x00000000},
408 {REG_MICFIL_DATACH0, 0x00000000},
409 {REG_MICFIL_DATACH1, 0x00000000},
410 {REG_MICFIL_DATACH2, 0x00000000},
411 {REG_MICFIL_DATACH3, 0x00000000},
412 {REG_MICFIL_DATACH4, 0x00000000},
413 {REG_MICFIL_DATACH5, 0x00000000},
414 {REG_MICFIL_DATACH6, 0x00000000},
415 {REG_MICFIL_DATACH7, 0x00000000},
416 {REG_MICFIL_DC_CTRL, 0x00000000},
417 {REG_MICFIL_OUT_CTRL, 0x00000000},
418 {REG_MICFIL_OUT_STAT, 0x00000000},
419 {REG_MICFIL_VAD0_CTRL1, 0x00000000},
420 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},
421 {REG_MICFIL_VAD0_STAT, 0x00000000},
422 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},
423 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},
424 {REG_MICFIL_VAD0_NDATA, 0x00000000},
425 {REG_MICFIL_VAD0_ZCD, 0x00000004},
426};
427
428static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
429{
430 switch (reg) {
431 case REG_MICFIL_CTRL1:
432 case REG_MICFIL_CTRL2:
433 case REG_MICFIL_STAT:
434 case REG_MICFIL_FIFO_CTRL:
435 case REG_MICFIL_FIFO_STAT:
436 case REG_MICFIL_DATACH0:
437 case REG_MICFIL_DATACH1:
438 case REG_MICFIL_DATACH2:
439 case REG_MICFIL_DATACH3:
440 case REG_MICFIL_DATACH4:
441 case REG_MICFIL_DATACH5:
442 case REG_MICFIL_DATACH6:
443 case REG_MICFIL_DATACH7:
444 case REG_MICFIL_DC_CTRL:
445 case REG_MICFIL_OUT_CTRL:
446 case REG_MICFIL_OUT_STAT:
447 case REG_MICFIL_VAD0_CTRL1:
448 case REG_MICFIL_VAD0_CTRL2:
449 case REG_MICFIL_VAD0_STAT:
450 case REG_MICFIL_VAD0_SCONFIG:
451 case REG_MICFIL_VAD0_NCONFIG:
452 case REG_MICFIL_VAD0_NDATA:
453 case REG_MICFIL_VAD0_ZCD:
454 return true;
455 default:
456 return false;
457 }
458}
459
460static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
461{
462 switch (reg) {
463 case REG_MICFIL_CTRL1:
464 case REG_MICFIL_CTRL2:
465 case REG_MICFIL_STAT: /* Write 1 to Clear */
466 case REG_MICFIL_FIFO_CTRL:
467 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
468 case REG_MICFIL_DC_CTRL:
469 case REG_MICFIL_OUT_CTRL:
470 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
471 case REG_MICFIL_VAD0_CTRL1:
472 case REG_MICFIL_VAD0_CTRL2:
473 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
474 case REG_MICFIL_VAD0_SCONFIG:
475 case REG_MICFIL_VAD0_NCONFIG:
476 case REG_MICFIL_VAD0_ZCD:
477 return true;
478 default:
479 return false;
480 }
481}
482
483static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
484{
485 switch (reg) {
486 case REG_MICFIL_STAT:
487 case REG_MICFIL_DATACH0:
488 case REG_MICFIL_DATACH1:
489 case REG_MICFIL_DATACH2:
490 case REG_MICFIL_DATACH3:
491 case REG_MICFIL_DATACH4:
492 case REG_MICFIL_DATACH5:
493 case REG_MICFIL_DATACH6:
494 case REG_MICFIL_DATACH7:
495 case REG_MICFIL_VAD0_STAT:
496 case REG_MICFIL_VAD0_NDATA:
497 return true;
498 default:
499 return false;
500 }
501}
502
503static const struct regmap_config fsl_micfil_regmap_config = {
504 .reg_bits = 32,
505 .reg_stride = 4,
506 .val_bits = 32,
507
508 .max_register = REG_MICFIL_VAD0_ZCD,
509 .reg_defaults = fsl_micfil_reg_defaults,
510 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
511 .readable_reg = fsl_micfil_readable_reg,
512 .volatile_reg = fsl_micfil_volatile_reg,
513 .writeable_reg = fsl_micfil_writeable_reg,
514 .cache_type = REGCACHE_RBTREE,
515};
516
517/* END OF REGMAP */
518
519static irqreturn_t micfil_isr(int irq, void *devid)
520{
521 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
522 struct platform_device *pdev = micfil->pdev;
523 u32 stat_reg;
524 u32 fifo_stat_reg;
525 u32 ctrl1_reg;
526 bool dma_enabled;
527 int i;
528
529 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
530 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
531 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
532
533 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
534
535 /* Channel 0-7 Output Data Flags */
536 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
537 if (stat_reg & MICFIL_STAT_CHXF(i))
538 dev_dbg(&pdev->dev,
539 "Data available in Data Channel %d\n", i);
540 /* if DMA is not enabled, field must be written with 1
541 * to clear
542 */
543 if (!dma_enabled)
544 regmap_write_bits(micfil->regmap,
545 REG_MICFIL_STAT,
546 MICFIL_STAT_CHXF(i),
547 1);
548 }
549
550 for (i = 0; i < MICFIL_FIFO_NUM; i++) {
551 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
552 dev_dbg(&pdev->dev,
553 "FIFO Overflow Exception flag for channel %d\n",
554 i);
555
556 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
557 dev_dbg(&pdev->dev,
558 "FIFO Underflow Exception flag for channel %d\n",
559 i);
560 }
561
562 return IRQ_HANDLED;
563}
564
565static irqreturn_t micfil_err_isr(int irq, void *devid)
566{
567 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
568 struct platform_device *pdev = micfil->pdev;
569 u32 stat_reg;
570
571 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
572
573 if (stat_reg & MICFIL_STAT_BSY_FIL)
574 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
575
576 if (stat_reg & MICFIL_STAT_FIR_RDY)
577 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
578
579 if (stat_reg & MICFIL_STAT_LOWFREQF) {
580 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
581 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
582 MICFIL_STAT_LOWFREQF, 1);
583 }
584
585 return IRQ_HANDLED;
586}
587
588static int fsl_micfil_probe(struct platform_device *pdev)
589{
590 struct device_node *np = pdev->dev.of_node;
591 struct fsl_micfil *micfil;
592 struct resource *res;
593 void __iomem *regs;
594 int ret, i;
595
596 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
597 if (!micfil)
598 return -ENOMEM;
599
600 micfil->pdev = pdev;
601 strncpy(micfil->name, np->name, sizeof(micfil->name) - 1);
602
603 micfil->soc = of_device_get_match_data(&pdev->dev);
604
605 /* ipg_clk is used to control the registers
606 * ipg_clk_app is used to operate the filter
607 */
608 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
609 if (IS_ERR(micfil->mclk)) {
610 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
611 PTR_ERR(micfil->mclk));
612 return PTR_ERR(micfil->mclk);
613 }
614
615 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");
616 if (IS_ERR(micfil->busclk)) {
617 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",
618 PTR_ERR(micfil->busclk));
619 return PTR_ERR(micfil->busclk);
620 }
621
622 fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk,
623 &micfil->pll11k_clk);
624
625 /* init regmap */
626 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
627 if (IS_ERR(regs))
628 return PTR_ERR(regs);
629
630 micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
631 regs,
632 &fsl_micfil_regmap_config);
633 if (IS_ERR(micfil->regmap)) {
634 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
635 PTR_ERR(micfil->regmap));
636 return PTR_ERR(micfil->regmap);
637 }
638
639 /* dataline mask for RX */
640 ret = of_property_read_u32_index(np,
641 "fsl,dataline",
642 0,
643 &micfil->dataline);
644 if (ret)
645 micfil->dataline = 1;
646
647 if (micfil->dataline & ~micfil->soc->dataline) {
648 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
649 micfil->soc->dataline);
650 return -EINVAL;
651 }
652
653 /* get IRQs */
654 for (i = 0; i < MICFIL_IRQ_LINES; i++) {
655 micfil->irq[i] = platform_get_irq(pdev, i);
656 if (micfil->irq[i] < 0)
657 return micfil->irq[i];
658 }
659
660 /* Digital Microphone interface interrupt */
661 ret = devm_request_irq(&pdev->dev, micfil->irq[0],
662 micfil_isr, IRQF_SHARED,
663 micfil->name, micfil);
664 if (ret) {
665 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
666 micfil->irq[0]);
667 return ret;
668 }
669
670 /* Digital Microphone interface error interrupt */
671 ret = devm_request_irq(&pdev->dev, micfil->irq[1],
672 micfil_err_isr, IRQF_SHARED,
673 micfil->name, micfil);
674 if (ret) {
675 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
676 micfil->irq[1]);
677 return ret;
678 }
679
680 micfil->dma_params_rx.chan_name = "rx";
681 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
682 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
683
684 platform_set_drvdata(pdev, micfil);
685
686 pm_runtime_enable(&pdev->dev);
687 regcache_cache_only(micfil->regmap, true);
688
689 /*
690 * Register platform component before registering cpu dai for there
691 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
692 */
693 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
694 if (ret) {
695 dev_err(&pdev->dev, "failed to pcm register\n");
696 return ret;
697 }
698
699 fsl_micfil_dai.capture.formats = micfil->soc->formats;
700
701 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
702 &fsl_micfil_dai, 1);
703 if (ret) {
704 dev_err(&pdev->dev, "failed to register component %s\n",
705 fsl_micfil_component.name);
706 }
707
708 return ret;
709}
710
711static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev)
712{
713 struct fsl_micfil *micfil = dev_get_drvdata(dev);
714
715 regcache_cache_only(micfil->regmap, true);
716
717 clk_disable_unprepare(micfil->mclk);
718 clk_disable_unprepare(micfil->busclk);
719
720 return 0;
721}
722
723static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev)
724{
725 struct fsl_micfil *micfil = dev_get_drvdata(dev);
726 int ret;
727
728 ret = clk_prepare_enable(micfil->busclk);
729 if (ret < 0)
730 return ret;
731
732 ret = clk_prepare_enable(micfil->mclk);
733 if (ret < 0) {
734 clk_disable_unprepare(micfil->busclk);
735 return ret;
736 }
737
738 regcache_cache_only(micfil->regmap, false);
739 regcache_mark_dirty(micfil->regmap);
740 regcache_sync(micfil->regmap);
741
742 return 0;
743}
744
745static int __maybe_unused fsl_micfil_suspend(struct device *dev)
746{
747 pm_runtime_force_suspend(dev);
748
749 return 0;
750}
751
752static int __maybe_unused fsl_micfil_resume(struct device *dev)
753{
754 pm_runtime_force_resume(dev);
755
756 return 0;
757}
758
759static const struct dev_pm_ops fsl_micfil_pm_ops = {
760 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
761 fsl_micfil_runtime_resume,
762 NULL)
763 SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend,
764 fsl_micfil_resume)
765};
766
767static struct platform_driver fsl_micfil_driver = {
768 .probe = fsl_micfil_probe,
769 .driver = {
770 .name = "fsl-micfil-dai",
771 .pm = &fsl_micfil_pm_ops,
772 .of_match_table = fsl_micfil_dt_ids,
773 },
774};
775module_platform_driver(fsl_micfil_driver);
776
777MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");
778MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
779MODULE_LICENSE("GPL v2");