tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#ifndef __RTW89_PHY_H__
6#define __RTW89_PHY_H__
7
8#include "core.h"
9
10#define RTW89_PHY_ADDR_OFFSET 0x10000
11#define RTW89_RF_ADDR_ADSEL_MASK BIT(16)
12
13#define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr)
14#define PHY_HEADLINE_VALID 0xf
15#define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr)
16#define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \
17 FIELD_PREP(GENMASK(7, 0), cv))
18
19#define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr)
20#define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr)
21#define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr)
22#define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr)
23#define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; })
24#define PHY_COND_BRANCH_IF 0x8
25#define PHY_COND_BRANCH_ELIF 0x9
26#define PHY_COND_BRANCH_ELSE 0xa
27#define PHY_COND_BRANCH_END 0xb
28#define PHY_COND_CHECK 0x4
29#define PHY_COND_DONT_CARE 0xff
30
31#define RA_MASK_CCK_RATES GENMASK_ULL(3, 0)
32#define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4)
33#define RA_MASK_SUBCCK_RATES 0x5ULL
34#define RA_MASK_SUBOFDM_RATES 0x10ULL
35#define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12)
36#define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24)
37#define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36)
38#define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48)
39#define RA_MASK_HT_RATES GENMASK_ULL(55, 12)
40#define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12)
41#define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24)
42#define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36)
43#define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48)
44#define RA_MASK_VHT_RATES GENMASK_ULL(57, 12)
45#define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12)
46#define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24)
47#define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36)
48#define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48)
49#define RA_MASK_HE_RATES GENMASK_ULL(59, 12)
50
51#define CFO_TRK_ENABLE_TH (2 << 2)
52#define CFO_TRK_STOP_TH_4 (30 << 2)
53#define CFO_TRK_STOP_TH_3 (20 << 2)
54#define CFO_TRK_STOP_TH_2 (10 << 2)
55#define CFO_TRK_STOP_TH_1 (00 << 2)
56#define CFO_TRK_STOP_TH (2 << 2)
57#define CFO_SW_COMP_FINE_TUNE (2 << 2)
58#define CFO_PERIOD_CNT 15
59#define CFO_BOUND 32
60#define CFO_TP_UPPER 100
61#define CFO_TP_LOWER 50
62#define CFO_COMP_PERIOD 250
63#define CFO_COMP_WEIGHT 8
64#define MAX_CFO_TOLERANCE 30
65#define CFO_TF_CNT_TH 300
66
67#define CCX_MAX_PERIOD 2097
68#define CCX_MAX_PERIOD_UNIT 32
69#define MS_TO_4US_RATIO 250
70#define ENV_MNTR_FAIL_DWORD 0xffffffff
71#define ENV_MNTR_IFSCLM_HIS_MAX 127
72#define PERMIL 1000
73#define PERCENT 100
74#define IFS_CLM_TH0_UPPER 64
75#define IFS_CLM_TH_MUL 4
76#define IFS_CLM_TH_START_IDX 0
77
78#define TIA0_GAIN_A 12
79#define TIA0_GAIN_G 16
80#define LNA0_GAIN (-24)
81#define U4_MAX_BIT 3
82#define U8_MAX_BIT 7
83#define DIG_GAIN_SHIFT 2
84#define DIG_GAIN 8
85
86#define LNA_IDX_MAX 6
87#define LNA_IDX_MIN 0
88#define TIA_IDX_MAX 1
89#define TIA_IDX_MIN 0
90#define RXB_IDX_MAX 31
91#define RXB_IDX_MIN 0
92
93#define IGI_RSSI_MAX 110
94#define PD_TH_MAX_RSSI 70
95#define PD_TH_MIN_RSSI 8
96#define CCKPD_TH_MIN_RSSI (-18)
97#define PD_TH_BW160_CMP_VAL 9
98#define PD_TH_BW80_CMP_VAL 6
99#define PD_TH_BW40_CMP_VAL 3
100#define PD_TH_BW20_CMP_VAL 0
101#define PD_TH_CMP_VAL 3
102#define PD_TH_SB_FLTR_CMP_VAL 7
103
104#define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT)
105#define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL)
106#define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA)
107#define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD)
108#define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA)
109
110enum rtw89_phy_c2h_ra_func {
111 RTW89_PHY_C2H_FUNC_STS_RPT,
112 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT,
113 RTW89_PHY_C2H_FUNC_TXSTS,
114 RTW89_PHY_C2H_FUNC_RA_MAX,
115};
116
117enum rtw89_phy_c2h_class {
118 RTW89_PHY_C2H_CLASS_RUA,
119 RTW89_PHY_C2H_CLASS_RA,
120 RTW89_PHY_C2H_CLASS_DM,
121 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10,
122 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17,
123 RTW89_PHY_C2H_CLASS_MAX,
124};
125
126enum rtw89_env_monitor_result_level {
127 RTW89_PHY_ENV_MON_CCX_FAIL = 0,
128 RTW89_PHY_ENV_MON_NHM = BIT(0),
129 RTW89_PHY_ENV_MON_CLM = BIT(1),
130 RTW89_PHY_ENV_MON_FAHM = BIT(2),
131 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3),
132 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4),
133};
134
135#define CCX_US_BASE_RATIO 4
136enum rtw89_ccx_unit {
137 RTW89_CCX_4_US = 0,
138 RTW89_CCX_8_US = 1,
139 RTW89_CCX_16_US = 2,
140 RTW89_CCX_32_US = 3
141};
142
143enum rtw89_phy_status_ie_type {
144 RTW89_PHYSTS_IE00_CMN_CCK = 0,
145 RTW89_PHYSTS_IE01_CMN_OFDM = 1,
146 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2,
147 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3,
148 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4,
149 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5,
150 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6,
151 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7,
152 RTW89_PHYSTS_IE08_FTR_CH = 8,
153 RTW89_PHYSTS_IE09_FTR_0 = 9,
154 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10,
155 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11,
156 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12,
157 RTW89_PHYSTS_IE13_DL_MU_DEF = 13,
158 RTW89_PHYSTS_IE14_TB_UL_CQI = 14,
159 RTW89_PHYSTS_IE15_TB_UL_DEF = 15,
160 RTW89_PHYSTS_IE16_RSVD16 = 16,
161 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17,
162 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18,
163 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19,
164 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20,
165 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21,
166 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22,
167 RTW89_PHYSTS_IE23_RSVD23 = 23,
168 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24,
169 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25,
170 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26,
171 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27,
172 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28,
173 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29,
174 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30,
175 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31,
176
177 /* keep last */
178 RTW89_PHYSTS_IE_NUM,
179 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1
180};
181
182enum rtw89_phy_status_bitmap {
183 RTW89_TD_SEARCH_FAIL = 0,
184 RTW89_BRK_BY_TX_PKT = 1,
185 RTW89_CCA_SPOOF = 2,
186 RTW89_OFDM_BRK = 3,
187 RTW89_CCK_BRK = 4,
188 RTW89_DL_MU_SPOOFING = 5,
189 RTW89_HE_MU = 6,
190 RTW89_VHT_MU = 7,
191 RTW89_UL_TB_SPOOFING = 8,
192 RTW89_RSVD_9 = 9,
193 RTW89_TRIG_BASE_PPDU = 10,
194 RTW89_CCK_PKT = 11,
195 RTW89_LEGACY_OFDM_PKT = 12,
196 RTW89_HT_PKT = 13,
197 RTW89_VHT_PKT = 14,
198 RTW89_HE_PKT = 15,
199
200 RTW89_PHYSTS_BITMAP_NUM
201};
202
203enum rtw89_dig_gain_type {
204 RTW89_DIG_GAIN_LNA_G = 0,
205 RTW89_DIG_GAIN_TIA_G = 1,
206 RTW89_DIG_GAIN_LNA_A = 2,
207 RTW89_DIG_GAIN_TIA_A = 3,
208 RTW89_DIG_GAIN_MAX = 4
209};
210
211enum rtw89_dig_gain_lna_idx {
212 RTW89_DIG_GAIN_LNA_IDX1 = 1,
213 RTW89_DIG_GAIN_LNA_IDX2 = 2,
214 RTW89_DIG_GAIN_LNA_IDX3 = 3,
215 RTW89_DIG_GAIN_LNA_IDX4 = 4,
216 RTW89_DIG_GAIN_LNA_IDX5 = 5,
217 RTW89_DIG_GAIN_LNA_IDX6 = 6
218};
219
220enum rtw89_dig_gain_tia_idx {
221 RTW89_DIG_GAIN_TIA_IDX0 = 0,
222 RTW89_DIG_GAIN_TIA_IDX1 = 1
223};
224
225enum rtw89_tssi_bandedge_cfg {
226 RTW89_TSSI_BANDEDGE_FLAT,
227 RTW89_TSSI_BANDEDGE_LOW,
228 RTW89_TSSI_BANDEDGE_MID,
229 RTW89_TSSI_BANDEDGE_HIGH,
230
231 RTW89_TSSI_CFG_NUM,
232};
233
234enum rtw89_tssi_sbw_idx {
235 RTW89_TSSI_SBW20,
236 RTW89_TSSI_SBW40_0,
237 RTW89_TSSI_SBW40_1,
238 RTW89_TSSI_SBW80_0,
239 RTW89_TSSI_SBW80_1,
240 RTW89_TSSI_SBW80_2,
241 RTW89_TSSI_SBW80_3,
242 RTW89_TSSI_SBW160_0,
243 RTW89_TSSI_SBW160_1,
244 RTW89_TSSI_SBW160_2,
245 RTW89_TSSI_SBW160_3,
246 RTW89_TSSI_SBW160_4,
247 RTW89_TSSI_SBW160_5,
248 RTW89_TSSI_SBW160_6,
249 RTW89_TSSI_SBW160_7,
250
251 RTW89_TSSI_SBW_NUM,
252};
253
254struct rtw89_txpwr_byrate_cfg {
255 enum rtw89_band band;
256 enum rtw89_nss nss;
257 enum rtw89_rate_section rs;
258 u8 shf;
259 u8 len;
260 u32 data;
261};
262
263#define DELTA_SWINGIDX_SIZE 30
264
265struct rtw89_txpwr_track_cfg {
266 const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE];
267 const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE];
268 const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE];
269 const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE];
270 const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE];
271 const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE];
272 const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE];
273 const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE];
274 const s8 *delta_swingidx_2gb_n;
275 const s8 *delta_swingidx_2gb_p;
276 const s8 *delta_swingidx_2ga_n;
277 const s8 *delta_swingidx_2ga_p;
278 const s8 *delta_swingidx_2g_cck_b_n;
279 const s8 *delta_swingidx_2g_cck_b_p;
280 const s8 *delta_swingidx_2g_cck_a_n;
281 const s8 *delta_swingidx_2g_cck_a_p;
282};
283
284struct rtw89_phy_dig_gain_cfg {
285 const struct rtw89_reg_def *table;
286 u8 size;
287};
288
289struct rtw89_phy_dig_gain_table {
290 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g;
291 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g;
292 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a;
293 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a;
294};
295
296struct rtw89_phy_tssi_dbw_table {
297 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM];
298};
299
300struct rtw89_phy_reg3_tbl {
301 const struct rtw89_reg3_def *reg3;
302 int size;
303};
304
305#define DECLARE_PHY_REG3_TBL(_name) \
306const struct rtw89_phy_reg3_tbl _name ## _tbl = { \
307 .reg3 = _name, \
308 .size = ARRAY_SIZE(_name), \
309}
310
311struct rtw89_nbi_reg_def {
312 struct rtw89_reg_def notch1_idx;
313 struct rtw89_reg_def notch1_frac_idx;
314 struct rtw89_reg_def notch1_en;
315 struct rtw89_reg_def notch2_idx;
316 struct rtw89_reg_def notch2_frac_idx;
317 struct rtw89_reg_def notch2_en;
318};
319
320extern const u8 rtw89_rs_idx_max[RTW89_RS_MAX];
321extern const u8 rtw89_rs_nss_max[RTW89_RS_MAX];
322
323static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,
324 u32 addr, u8 data)
325{
326 rtw89_write8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
327}
328
329static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev,
330 u32 addr, u16 data)
331{
332 rtw89_write16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
333}
334
335static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev,
336 u32 addr, u32 data)
337{
338 rtw89_write32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
339}
340
341static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev,
342 u32 addr, u32 bits)
343{
344 rtw89_write32_set(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits);
345}
346
347static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev,
348 u32 addr, u32 bits)
349{
350 rtw89_write32_clr(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits);
351}
352
353static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev,
354 u32 addr, u32 mask, u32 data)
355{
356 rtw89_write32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask, data);
357}
358
359static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr)
360{
361 return rtw89_read8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
362}
363
364static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr)
365{
366 return rtw89_read16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
367}
368
369static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr)
370{
371 return rtw89_read32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
372}
373
374static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev,
375 u32 addr, u32 mask)
376{
377 return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask);
378}
379
380enum rtw89_rfk_flag {
381 RTW89_RFK_F_WRF = 0,
382 RTW89_RFK_F_WM = 1,
383 RTW89_RFK_F_WS = 2,
384 RTW89_RFK_F_WC = 3,
385 RTW89_RFK_F_DELAY = 4,
386 RTW89_RFK_F_NUM,
387};
388
389struct rtw89_rfk_tbl {
390 const struct rtw89_reg5_def *defs;
391 u32 size;
392};
393
394#define RTW89_DECLARE_RFK_TBL(_name) \
395const struct rtw89_rfk_tbl _name ## _tbl = { \
396 .defs = _name, \
397 .size = ARRAY_SIZE(_name), \
398}
399
400#define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \
401 {.flag = RTW89_RFK_F_WRF, \
402 .path = _path, \
403 .addr = _addr, \
404 .mask = _mask, \
405 .data = _data,}
406
407#define RTW89_DECL_RFK_WM(_addr, _mask, _data) \
408 {.flag = RTW89_RFK_F_WM, \
409 .addr = _addr, \
410 .mask = _mask, \
411 .data = _data,}
412
413#define RTW89_DECL_RFK_WS(_addr, _mask) \
414 {.flag = RTW89_RFK_F_WS, \
415 .addr = _addr, \
416 .mask = _mask,}
417
418#define RTW89_DECL_RFK_WC(_addr, _mask) \
419 {.flag = RTW89_RFK_F_WC, \
420 .addr = _addr, \
421 .mask = _mask,}
422
423#define RTW89_DECL_RFK_DELAY(_data) \
424 {.flag = RTW89_RFK_F_DELAY, \
425 .data = _data,}
426
427void
428rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl);
429
430#define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \
431 do { \
432 typeof(dev) __dev = (dev); \
433 if (cond) \
434 rtw89_rfk_parser(__dev, (tbl_t)); \
435 else \
436 rtw89_rfk_parser(__dev, (tbl_f)); \
437 } while (0)
438
439void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
440 const struct rtw89_phy_reg3_tbl *tbl);
441u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
442 struct rtw89_channel_params *param,
443 enum rtw89_bandwidth dbw);
444u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
445 u32 addr, u32 mask);
446u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
447 u32 addr, u32 mask);
448bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
449 u32 addr, u32 mask, u32 data);
450bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
451 u32 addr, u32 mask, u32 data);
452void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev);
453void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev);
454void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
455 const struct rtw89_reg2_def *reg,
456 enum rtw89_rf_path rf_path,
457 void *extra_data);
458void rtw89_phy_dm_init(struct rtw89_dev *rtwdev);
459void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
460 u32 data, enum rtw89_phy_idx phy_idx);
461void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
462 const struct rtw89_txpwr_table *tbl);
463s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev,
464 const struct rtw89_rate_desc *rate_desc);
465void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,
466 struct rtw89_txpwr_limit *lmt,
467 u8 ntx);
468void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
469 struct rtw89_txpwr_limit_ru *lmt_ru,
470 u8 ntx);
471s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev,
472 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch);
473void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta);
474void rtw89_phy_ra_update(struct rtw89_dev *rtwdev);
475void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
476 u32 changed);
477void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
478 struct ieee80211_vif *vif,
479 const struct cfg80211_bitrate_mask *mask);
480void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
481 u32 len, u8 class, u8 func);
482void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev);
483void rtw89_phy_cfo_track_work(struct work_struct *work);
484void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
485 struct rtw89_rx_phy_ppdu *phy_ppdu);
486void rtw89_phy_stat_track(struct rtw89_dev *rtwdev);
487void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev);
488void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
489 u32 val);
490void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev);
491void rtw89_phy_dig(struct rtw89_dev *rtwdev);
492void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
493void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
494 enum rtw89_mac_idx mac_idx,
495 enum rtw89_tssi_bandedge_cfg bandedge_cfg);
496
497#endif