tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/module.h>
26#include "amdgpu.h"
27#include "soc15_common.h"
28#include "soc21.h"
29#include "gc/gc_11_0_0_offset.h"
30#include "gc/gc_11_0_0_sh_mask.h"
31#include "gc/gc_11_0_0_default.h"
32#include "v11_structs.h"
33#include "mes_v11_api_def.h"
34
35MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin");
36MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin");
37MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin");
38MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin");
39MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin");
40MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");
41
42static int mes_v11_0_hw_fini(void *handle);
43static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
44static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);
45
46#define MES_EOP_SIZE 2048
47
48static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)
49{
50 struct amdgpu_device *adev = ring->adev;
51
52 if (ring->use_doorbell) {
53 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
54 ring->wptr);
55 WDOORBELL64(ring->doorbell_index, ring->wptr);
56 } else {
57 BUG();
58 }
59}
60
61static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring)
62{
63 return *ring->rptr_cpu_addr;
64}
65
66static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring)
67{
68 u64 wptr;
69
70 if (ring->use_doorbell)
71 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
72 else
73 BUG();
74 return wptr;
75}
76
77static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = {
78 .type = AMDGPU_RING_TYPE_MES,
79 .align_mask = 1,
80 .nop = 0,
81 .support_64bit_ptrs = true,
82 .get_rptr = mes_v11_0_ring_get_rptr,
83 .get_wptr = mes_v11_0_ring_get_wptr,
84 .set_wptr = mes_v11_0_ring_set_wptr,
85 .insert_nop = amdgpu_ring_insert_nop,
86};
87
88static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
89 void *pkt, int size,
90 int api_status_off)
91{
92 int ndw = size / 4;
93 signed long r;
94 union MESAPI__ADD_QUEUE *x_pkt = pkt;
95 struct MES_API_STATUS *api_status;
96 struct amdgpu_device *adev = mes->adev;
97 struct amdgpu_ring *ring = &mes->ring;
98 unsigned long flags;
99
100 BUG_ON(size % 4 != 0);
101
102 spin_lock_irqsave(&mes->ring_lock, flags);
103 if (amdgpu_ring_alloc(ring, ndw)) {
104 spin_unlock_irqrestore(&mes->ring_lock, flags);
105 return -ENOMEM;
106 }
107
108 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
109 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr;
110 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq;
111
112 amdgpu_ring_write_multiple(ring, pkt, ndw);
113 amdgpu_ring_commit(ring);
114 spin_unlock_irqrestore(&mes->ring_lock, flags);
115
116 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode);
117
118 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq,
119 adev->usec_timeout * (amdgpu_emu_mode ? 100 : 1));
120 if (r < 1) {
121 DRM_ERROR("MES failed to response msg=%d\n",
122 x_pkt->header.opcode);
123 return -ETIMEDOUT;
124 }
125
126 return 0;
127}
128
129static int convert_to_mes_queue_type(int queue_type)
130{
131 if (queue_type == AMDGPU_RING_TYPE_GFX)
132 return MES_QUEUE_TYPE_GFX;
133 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
134 return MES_QUEUE_TYPE_COMPUTE;
135 else if (queue_type == AMDGPU_RING_TYPE_SDMA)
136 return MES_QUEUE_TYPE_SDMA;
137 else
138 BUG();
139 return -1;
140}
141
142static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
143 struct mes_add_queue_input *input)
144{
145 struct amdgpu_device *adev = mes->adev;
146 union MESAPI__ADD_QUEUE mes_add_queue_pkt;
147 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
148 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
149
150 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
151
152 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
153 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
154 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
155
156 mes_add_queue_pkt.process_id = input->process_id;
157 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
158 mes_add_queue_pkt.process_va_start = input->process_va_start;
159 mes_add_queue_pkt.process_va_end = input->process_va_end;
160 mes_add_queue_pkt.process_quantum = input->process_quantum;
161 mes_add_queue_pkt.process_context_addr = input->process_context_addr;
162 mes_add_queue_pkt.gang_quantum = input->gang_quantum;
163 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
164 mes_add_queue_pkt.inprocess_gang_priority =
165 input->inprocess_gang_priority;
166 mes_add_queue_pkt.gang_global_priority_level =
167 input->gang_global_priority_level;
168 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
169 mes_add_queue_pkt.mqd_addr = input->mqd_addr;
170
171 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
172 AMDGPU_MES_API_VERSION_SHIFT) >= 2)
173 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
174 else
175 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
176
177 mes_add_queue_pkt.queue_type =
178 convert_to_mes_queue_type(input->queue_type);
179 mes_add_queue_pkt.paging = input->paging;
180 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
181 mes_add_queue_pkt.gws_base = input->gws_base;
182 mes_add_queue_pkt.gws_size = input->gws_size;
183 mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
184 mes_add_queue_pkt.tma_addr = input->tma_addr;
185 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
186 mes_add_queue_pkt.trap_en = 1;
187
188 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
189 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
190 mes_add_queue_pkt.gds_size = input->queue_size;
191
192 return mes_v11_0_submit_pkt_and_poll_completion(mes,
193 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
194 offsetof(union MESAPI__ADD_QUEUE, api_status));
195}
196
197static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes,
198 struct mes_remove_queue_input *input)
199{
200 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
201
202 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
203
204 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
205 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
206 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
207
208 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
209 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
210
211 return mes_v11_0_submit_pkt_and_poll_completion(mes,
212 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
213 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
214}
215
216static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes,
217 struct mes_unmap_legacy_queue_input *input)
218{
219 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
220
221 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
222
223 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
224 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
225 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
226
227 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
228 mes_remove_queue_pkt.gang_context_addr = 0;
229
230 mes_remove_queue_pkt.pipe_id = input->pipe_id;
231 mes_remove_queue_pkt.queue_id = input->queue_id;
232
233 if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
234 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
235 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
236 mes_remove_queue_pkt.tf_data =
237 lower_32_bits(input->trail_fence_data);
238 } else {
239 mes_remove_queue_pkt.unmap_legacy_queue = 1;
240 mes_remove_queue_pkt.queue_type =
241 convert_to_mes_queue_type(input->queue_type);
242 }
243
244 return mes_v11_0_submit_pkt_and_poll_completion(mes,
245 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
246 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
247}
248
249static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes,
250 struct mes_suspend_gang_input *input)
251{
252 return 0;
253}
254
255static int mes_v11_0_resume_gang(struct amdgpu_mes *mes,
256 struct mes_resume_gang_input *input)
257{
258 return 0;
259}
260
261static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes)
262{
263 union MESAPI__QUERY_MES_STATUS mes_status_pkt;
264
265 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
266
267 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
268 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
269 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
270
271 return mes_v11_0_submit_pkt_and_poll_completion(mes,
272 &mes_status_pkt, sizeof(mes_status_pkt),
273 offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
274}
275
276static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
277 struct mes_misc_op_input *input)
278{
279 union MESAPI__MISC misc_pkt;
280
281 memset(&misc_pkt, 0, sizeof(misc_pkt));
282
283 misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
284 misc_pkt.header.opcode = MES_SCH_API_MISC;
285 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
286
287 switch (input->op) {
288 case MES_MISC_OP_READ_REG:
289 misc_pkt.opcode = MESAPI_MISC__READ_REG;
290 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
291 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
292 break;
293 case MES_MISC_OP_WRITE_REG:
294 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
295 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
296 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
297 break;
298 case MES_MISC_OP_WRM_REG_WAIT:
299 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
300 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
301 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
302 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
303 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
304 misc_pkt.wait_reg_mem.reg_offset2 = 0;
305 break;
306 case MES_MISC_OP_WRM_REG_WR_WAIT:
307 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
308 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
309 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
310 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
311 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
312 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
313 break;
314 default:
315 DRM_ERROR("unsupported misc op (%d) \n", input->op);
316 return -EINVAL;
317 }
318
319 return mes_v11_0_submit_pkt_and_poll_completion(mes,
320 &misc_pkt, sizeof(misc_pkt),
321 offsetof(union MESAPI__MISC, api_status));
322}
323
324static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
325{
326 int i;
327 struct amdgpu_device *adev = mes->adev;
328 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
329
330 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
331
332 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
333 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
334 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
335
336 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
337 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
338 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
339 mes_set_hw_res_pkt.paging_vmid = 0;
340 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
341 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
342 mes->query_status_fence_gpu_addr;
343
344 for (i = 0; i < MAX_COMPUTE_PIPES; i++)
345 mes_set_hw_res_pkt.compute_hqd_mask[i] =
346 mes->compute_hqd_mask[i];
347
348 for (i = 0; i < MAX_GFX_PIPES; i++)
349 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
350
351 for (i = 0; i < MAX_SDMA_PIPES; i++)
352 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
353
354 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
355 mes_set_hw_res_pkt.aggregated_doorbells[i] =
356 mes->aggregated_doorbells[i];
357
358 for (i = 0; i < 5; i++) {
359 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
360 mes_set_hw_res_pkt.mmhub_base[i] =
361 adev->reg_offset[MMHUB_HWIP][0][i];
362 mes_set_hw_res_pkt.osssys_base[i] =
363 adev->reg_offset[OSSSYS_HWIP][0][i];
364 }
365
366 mes_set_hw_res_pkt.disable_reset = 1;
367 mes_set_hw_res_pkt.disable_mes_log = 1;
368 mes_set_hw_res_pkt.use_different_vmid_compute = 1;
369 mes_set_hw_res_pkt.oversubscription_timer = 50;
370
371 return mes_v11_0_submit_pkt_and_poll_completion(mes,
372 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
373 offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
374}
375
376static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes)
377{
378 struct amdgpu_device *adev = mes->adev;
379 uint32_t data;
380
381 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1);
382 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |
383 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |
384 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);
385 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<
386 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;
387 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;
388 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data);
389
390 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2);
391 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |
392 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |
393 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);
394 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<
395 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;
396 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;
397 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data);
398
399 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3);
400 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |
401 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |
402 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);
403 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<
404 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;
405 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;
406 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data);
407
408 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4);
409 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |
410 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |
411 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);
412 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<
413 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;
414 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;
415 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data);
416
417 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5);
418 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |
419 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |
420 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);
421 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<
422 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;
423 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;
424 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data);
425
426 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;
427 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data);
428}
429
430static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
431 .add_hw_queue = mes_v11_0_add_hw_queue,
432 .remove_hw_queue = mes_v11_0_remove_hw_queue,
433 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue,
434 .suspend_gang = mes_v11_0_suspend_gang,
435 .resume_gang = mes_v11_0_resume_gang,
436 .misc_op = mes_v11_0_misc_op,
437};
438
439static int mes_v11_0_init_microcode(struct amdgpu_device *adev,
440 enum admgpu_mes_pipe pipe)
441{
442 char fw_name[30];
443 char ucode_prefix[30];
444 int err;
445 const struct mes_firmware_header_v1_0 *mes_hdr;
446 struct amdgpu_firmware_info *info;
447
448 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
449
450 if (pipe == AMDGPU_MES_SCHED_PIPE)
451 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin",
452 ucode_prefix);
453 else
454 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin",
455 ucode_prefix);
456
457 err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev);
458 if (err)
459 return err;
460
461 err = amdgpu_ucode_validate(adev->mes.fw[pipe]);
462 if (err) {
463 release_firmware(adev->mes.fw[pipe]);
464 adev->mes.fw[pipe] = NULL;
465 return err;
466 }
467
468 mes_hdr = (const struct mes_firmware_header_v1_0 *)
469 adev->mes.fw[pipe]->data;
470 adev->mes.ucode_fw_version[pipe] =
471 le32_to_cpu(mes_hdr->mes_ucode_version);
472 adev->mes.ucode_fw_version[pipe] =
473 le32_to_cpu(mes_hdr->mes_ucode_data_version);
474 adev->mes.uc_start_addr[pipe] =
475 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) |
476 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32);
477 adev->mes.data_start_addr[pipe] =
478 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) |
479 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32);
480
481 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
482 int ucode, ucode_data;
483
484 if (pipe == AMDGPU_MES_SCHED_PIPE) {
485 ucode = AMDGPU_UCODE_ID_CP_MES;
486 ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA;
487 } else {
488 ucode = AMDGPU_UCODE_ID_CP_MES1;
489 ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA;
490 }
491
492 info = &adev->firmware.ucode[ucode];
493 info->ucode_id = ucode;
494 info->fw = adev->mes.fw[pipe];
495 adev->firmware.fw_size +=
496 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes),
497 PAGE_SIZE);
498
499 info = &adev->firmware.ucode[ucode_data];
500 info->ucode_id = ucode_data;
501 info->fw = adev->mes.fw[pipe];
502 adev->firmware.fw_size +=
503 ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes),
504 PAGE_SIZE);
505 }
506
507 return 0;
508}
509
510static void mes_v11_0_free_microcode(struct amdgpu_device *adev,
511 enum admgpu_mes_pipe pipe)
512{
513 release_firmware(adev->mes.fw[pipe]);
514 adev->mes.fw[pipe] = NULL;
515}
516
517static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,
518 enum admgpu_mes_pipe pipe)
519{
520 int r;
521 const struct mes_firmware_header_v1_0 *mes_hdr;
522 const __le32 *fw_data;
523 unsigned fw_size;
524
525 mes_hdr = (const struct mes_firmware_header_v1_0 *)
526 adev->mes.fw[pipe]->data;
527
528 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
529 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
530 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
531
532 r = amdgpu_bo_create_reserved(adev, fw_size,
533 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
534 &adev->mes.ucode_fw_obj[pipe],
535 &adev->mes.ucode_fw_gpu_addr[pipe],
536 (void **)&adev->mes.ucode_fw_ptr[pipe]);
537 if (r) {
538 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
539 return r;
540 }
541
542 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
543
544 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
545 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
546
547 return 0;
548}
549
550static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
551 enum admgpu_mes_pipe pipe)
552{
553 int r;
554 const struct mes_firmware_header_v1_0 *mes_hdr;
555 const __le32 *fw_data;
556 unsigned fw_size;
557
558 mes_hdr = (const struct mes_firmware_header_v1_0 *)
559 adev->mes.fw[pipe]->data;
560
561 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
562 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
563 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
564
565 r = amdgpu_bo_create_reserved(adev, fw_size,
566 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
567 &adev->mes.data_fw_obj[pipe],
568 &adev->mes.data_fw_gpu_addr[pipe],
569 (void **)&adev->mes.data_fw_ptr[pipe]);
570 if (r) {
571 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
572 return r;
573 }
574
575 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
576
577 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
578 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
579
580 return 0;
581}
582
583static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,
584 enum admgpu_mes_pipe pipe)
585{
586 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
587 &adev->mes.data_fw_gpu_addr[pipe],
588 (void **)&adev->mes.data_fw_ptr[pipe]);
589
590 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
591 &adev->mes.ucode_fw_gpu_addr[pipe],
592 (void **)&adev->mes.ucode_fw_ptr[pipe]);
593}
594
595static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
596{
597 uint64_t ucode_addr;
598 uint32_t pipe, data = 0;
599
600 if (enable) {
601 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
602 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
603 data = REG_SET_FIELD(data, CP_MES_CNTL,
604 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0);
605 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
606
607 mutex_lock(&adev->srbm_mutex);
608 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
609 if (!adev->enable_mes_kiq &&
610 pipe == AMDGPU_MES_KIQ_PIPE)
611 continue;
612
613 soc21_grbm_select(adev, 3, pipe, 0, 0);
614
615 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
616 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
617 lower_32_bits(ucode_addr));
618 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
619 upper_32_bits(ucode_addr));
620 }
621 soc21_grbm_select(adev, 0, 0, 0, 0);
622 mutex_unlock(&adev->srbm_mutex);
623
624 /* unhalt MES and activate pipe0 */
625 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
626 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,
627 adev->enable_mes_kiq ? 1 : 0);
628 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
629
630 if (amdgpu_emu_mode)
631 msleep(100);
632 else
633 udelay(50);
634 } else {
635 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
636 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
637 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
638 data = REG_SET_FIELD(data, CP_MES_CNTL,
639 MES_INVALIDATE_ICACHE, 1);
640 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
641 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
642 adev->enable_mes_kiq ? 1 : 0);
643 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
644 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
645 }
646}
647
648/* This function is for backdoor MES firmware */
649static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
650 enum admgpu_mes_pipe pipe, bool prime_icache)
651{
652 int r;
653 uint32_t data;
654 uint64_t ucode_addr;
655
656 mes_v11_0_enable(adev, false);
657
658 if (!adev->mes.fw[pipe])
659 return -EINVAL;
660
661 r = mes_v11_0_allocate_ucode_buffer(adev, pipe);
662 if (r)
663 return r;
664
665 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe);
666 if (r) {
667 mes_v11_0_free_ucode_buffers(adev, pipe);
668 return r;
669 }
670
671 mutex_lock(&adev->srbm_mutex);
672 /* me=3, pipe=0, queue=0 */
673 soc21_grbm_select(adev, 3, pipe, 0, 0);
674
675 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
676
677 /* set ucode start address */
678 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
679 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
680 lower_32_bits(ucode_addr));
681 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
682 upper_32_bits(ucode_addr));
683
684 /* set ucode fimrware address */
685 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
686 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
687 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
688 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
689
690 /* set ucode instruction cache boundary to 2M-1 */
691 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
692
693 /* set ucode data firmware address */
694 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
695 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
696 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
697 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
698
699 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */
700 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF);
701
702 if (prime_icache) {
703 /* invalidate ICACHE */
704 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
705 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
706 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
707 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
708
709 /* prime the ICACHE. */
710 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
711 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
712 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
713 }
714
715 soc21_grbm_select(adev, 0, 0, 0, 0);
716 mutex_unlock(&adev->srbm_mutex);
717
718 return 0;
719}
720
721static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev,
722 enum admgpu_mes_pipe pipe)
723{
724 int r;
725 u32 *eop;
726
727 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
728 AMDGPU_GEM_DOMAIN_GTT,
729 &adev->mes.eop_gpu_obj[pipe],
730 &adev->mes.eop_gpu_addr[pipe],
731 (void **)&eop);
732 if (r) {
733 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
734 return r;
735 }
736
737 memset(eop, 0,
738 adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
739
740 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
741 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
742
743 return 0;
744}
745
746static int mes_v11_0_mqd_init(struct amdgpu_ring *ring)
747{
748 struct v11_compute_mqd *mqd = ring->mqd_ptr;
749 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
750 uint32_t tmp;
751
752 mqd->header = 0xC0310800;
753 mqd->compute_pipelinestat_enable = 0x00000001;
754 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
755 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
756 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
757 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
758 mqd->compute_misc_reserved = 0x00000007;
759
760 eop_base_addr = ring->eop_gpu_addr >> 8;
761
762 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
763 tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
764 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
765 (order_base_2(MES_EOP_SIZE / 4) - 1));
766
767 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
768 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
769 mqd->cp_hqd_eop_control = tmp;
770
771 /* disable the queue if it's active */
772 ring->wptr = 0;
773 mqd->cp_hqd_pq_rptr = 0;
774 mqd->cp_hqd_pq_wptr_lo = 0;
775 mqd->cp_hqd_pq_wptr_hi = 0;
776
777 /* set the pointer to the MQD */
778 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
779 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
780
781 /* set MQD vmid to 0 */
782 tmp = regCP_MQD_CONTROL_DEFAULT;
783 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
784 mqd->cp_mqd_control = tmp;
785
786 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
787 hqd_gpu_addr = ring->gpu_addr >> 8;
788 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
789 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
790
791 /* set the wb address whether it's enabled or not */
792 wb_gpu_addr = ring->rptr_gpu_addr;
793 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
794 mqd->cp_hqd_pq_rptr_report_addr_hi =
795 upper_32_bits(wb_gpu_addr) & 0xffff;
796
797 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
798 wb_gpu_addr = ring->wptr_gpu_addr;
799 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
800 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
801
802 /* set up the HQD, this is similar to CP_RB0_CNTL */
803 tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
804 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
805 (order_base_2(ring->ring_size / 4) - 1));
806 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
807 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
808 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
809 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
810 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
811 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
812 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
813 mqd->cp_hqd_pq_control = tmp;
814
815 /* enable doorbell */
816 tmp = 0;
817 if (ring->use_doorbell) {
818 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
819 DOORBELL_OFFSET, ring->doorbell_index);
820 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
821 DOORBELL_EN, 1);
822 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
823 DOORBELL_SOURCE, 0);
824 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
825 DOORBELL_HIT, 0);
826 }
827 else
828 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
829 DOORBELL_EN, 0);
830 mqd->cp_hqd_pq_doorbell_control = tmp;
831
832 mqd->cp_hqd_vmid = 0;
833 /* activate the queue */
834 mqd->cp_hqd_active = 1;
835
836 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
837 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
838 PRELOAD_SIZE, 0x55);
839 mqd->cp_hqd_persistent_state = tmp;
840
841 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
842 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
843 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
844
845 return 0;
846}
847
848static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring)
849{
850 struct v11_compute_mqd *mqd = ring->mqd_ptr;
851 struct amdgpu_device *adev = ring->adev;
852 uint32_t data = 0;
853
854 mutex_lock(&adev->srbm_mutex);
855 soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
856
857 /* set CP_HQD_VMID.VMID = 0. */
858 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
859 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
860 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
861
862 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
863 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
864 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
865 DOORBELL_EN, 0);
866 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
867
868 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
869 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
870 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
871
872 /* set CP_MQD_CONTROL.VMID=0 */
873 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
874 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
875 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
876
877 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
878 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
879 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
880
881 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
882 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
883 mqd->cp_hqd_pq_rptr_report_addr_lo);
884 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
885 mqd->cp_hqd_pq_rptr_report_addr_hi);
886
887 /* set CP_HQD_PQ_CONTROL */
888 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
889
890 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
891 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
892 mqd->cp_hqd_pq_wptr_poll_addr_lo);
893 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
894 mqd->cp_hqd_pq_wptr_poll_addr_hi);
895
896 /* set CP_HQD_PQ_DOORBELL_CONTROL */
897 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
898 mqd->cp_hqd_pq_doorbell_control);
899
900 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
901 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
902
903 /* set CP_HQD_ACTIVE.ACTIVE=1 */
904 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
905
906 soc21_grbm_select(adev, 0, 0, 0, 0);
907 mutex_unlock(&adev->srbm_mutex);
908}
909
910static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev)
911{
912 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
913 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
914 int r;
915
916 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
917 return -EINVAL;
918
919 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
920 if (r) {
921 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
922 return r;
923 }
924
925 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
926
927 r = amdgpu_ring_test_ring(kiq_ring);
928 if (r) {
929 DRM_ERROR("kfq enable failed\n");
930 kiq_ring->sched.ready = false;
931 }
932 return r;
933}
934
935static int mes_v11_0_queue_init(struct amdgpu_device *adev,
936 enum admgpu_mes_pipe pipe)
937{
938 struct amdgpu_ring *ring;
939 int r;
940
941 if (pipe == AMDGPU_MES_KIQ_PIPE)
942 ring = &adev->gfx.kiq.ring;
943 else if (pipe == AMDGPU_MES_SCHED_PIPE)
944 ring = &adev->mes.ring;
945 else
946 BUG();
947
948 if ((pipe == AMDGPU_MES_SCHED_PIPE) &&
949 (amdgpu_in_reset(adev) || adev->in_suspend)) {
950 *(ring->wptr_cpu_addr) = 0;
951 *(ring->rptr_cpu_addr) = 0;
952 amdgpu_ring_clear_ring(ring);
953 }
954
955 r = mes_v11_0_mqd_init(ring);
956 if (r)
957 return r;
958
959 if (pipe == AMDGPU_MES_SCHED_PIPE) {
960 r = mes_v11_0_kiq_enable_queue(adev);
961 if (r)
962 return r;
963 } else {
964 mes_v11_0_queue_init_register(ring);
965 }
966
967 /* get MES scheduler/KIQ versions */
968 mutex_lock(&adev->srbm_mutex);
969 soc21_grbm_select(adev, 3, pipe, 0, 0);
970
971 if (pipe == AMDGPU_MES_SCHED_PIPE)
972 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
973 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
974 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
975
976 soc21_grbm_select(adev, 0, 0, 0, 0);
977 mutex_unlock(&adev->srbm_mutex);
978
979 return 0;
980}
981
982static int mes_v11_0_ring_init(struct amdgpu_device *adev)
983{
984 struct amdgpu_ring *ring;
985
986 ring = &adev->mes.ring;
987
988 ring->funcs = &mes_v11_0_ring_funcs;
989
990 ring->me = 3;
991 ring->pipe = 0;
992 ring->queue = 0;
993
994 ring->ring_obj = NULL;
995 ring->use_doorbell = true;
996 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
997 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];
998 ring->no_scheduler = true;
999 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1000
1001 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1002 AMDGPU_RING_PRIO_DEFAULT, NULL);
1003}
1004
1005static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev)
1006{
1007 struct amdgpu_ring *ring;
1008
1009 spin_lock_init(&adev->gfx.kiq.ring_lock);
1010
1011 ring = &adev->gfx.kiq.ring;
1012
1013 ring->me = 3;
1014 ring->pipe = 1;
1015 ring->queue = 0;
1016
1017 ring->adev = NULL;
1018 ring->ring_obj = NULL;
1019 ring->use_doorbell = true;
1020 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1021 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
1022 ring->no_scheduler = true;
1023 sprintf(ring->name, "mes_kiq_%d.%d.%d",
1024 ring->me, ring->pipe, ring->queue);
1025
1026 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1027 AMDGPU_RING_PRIO_DEFAULT, NULL);
1028}
1029
1030static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,
1031 enum admgpu_mes_pipe pipe)
1032{
1033 int r, mqd_size = sizeof(struct v11_compute_mqd);
1034 struct amdgpu_ring *ring;
1035
1036 if (pipe == AMDGPU_MES_KIQ_PIPE)
1037 ring = &adev->gfx.kiq.ring;
1038 else if (pipe == AMDGPU_MES_SCHED_PIPE)
1039 ring = &adev->mes.ring;
1040 else
1041 BUG();
1042
1043 if (ring->mqd_obj)
1044 return 0;
1045
1046 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1047 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1048 &ring->mqd_gpu_addr, &ring->mqd_ptr);
1049 if (r) {
1050 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1051 return r;
1052 }
1053
1054 memset(ring->mqd_ptr, 0, mqd_size);
1055
1056 /* prepare MQD backup */
1057 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
1058 if (!adev->mes.mqd_backup[pipe])
1059 dev_warn(adev->dev,
1060 "no memory to create MQD backup for ring %s\n",
1061 ring->name);
1062
1063 return 0;
1064}
1065
1066static int mes_v11_0_sw_init(void *handle)
1067{
1068 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1069 int pipe, r;
1070
1071 adev->mes.adev = adev;
1072 adev->mes.funcs = &mes_v11_0_funcs;
1073 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
1074 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;
1075
1076 r = amdgpu_mes_init(adev);
1077 if (r)
1078 return r;
1079
1080 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1081 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1082 continue;
1083
1084 r = mes_v11_0_init_microcode(adev, pipe);
1085 if (r)
1086 return r;
1087
1088 r = mes_v11_0_allocate_eop_buf(adev, pipe);
1089 if (r)
1090 return r;
1091
1092 r = mes_v11_0_mqd_sw_init(adev, pipe);
1093 if (r)
1094 return r;
1095 }
1096
1097 if (adev->enable_mes_kiq) {
1098 r = mes_v11_0_kiq_ring_init(adev);
1099 if (r)
1100 return r;
1101 }
1102
1103 r = mes_v11_0_ring_init(adev);
1104 if (r)
1105 return r;
1106
1107 return 0;
1108}
1109
1110static int mes_v11_0_sw_fini(void *handle)
1111{
1112 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1113 int pipe;
1114
1115 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
1116 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
1117
1118 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1119 kfree(adev->mes.mqd_backup[pipe]);
1120
1121 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1122 &adev->mes.eop_gpu_addr[pipe],
1123 NULL);
1124
1125 mes_v11_0_free_microcode(adev, pipe);
1126 }
1127
1128 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj,
1129 &adev->gfx.kiq.ring.mqd_gpu_addr,
1130 &adev->gfx.kiq.ring.mqd_ptr);
1131
1132 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj,
1133 &adev->mes.ring.mqd_gpu_addr,
1134 &adev->mes.ring.mqd_ptr);
1135
1136 amdgpu_ring_fini(&adev->gfx.kiq.ring);
1137 amdgpu_ring_fini(&adev->mes.ring);
1138
1139 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1140 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1141 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1142 }
1143
1144 amdgpu_mes_fini(adev);
1145 return 0;
1146}
1147
1148static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
1149{
1150 uint32_t tmp;
1151 struct amdgpu_device *adev = ring->adev;
1152
1153 /* tell RLC which is KIQ queue */
1154 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1155 tmp &= 0xffffff00;
1156 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1157 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1158 tmp |= 0x80;
1159 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1160}
1161
1162static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
1163{
1164 int r = 0;
1165
1166 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1167
1168 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1169 if (r) {
1170 DRM_ERROR("failed to load MES fw, r=%d\n", r);
1171 return r;
1172 }
1173
1174 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1175 if (r) {
1176 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1177 return r;
1178 }
1179
1180 }
1181
1182 mes_v11_0_enable(adev, true);
1183
1184 mes_v11_0_kiq_setting(&adev->gfx.kiq.ring);
1185
1186 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1187 if (r)
1188 goto failure;
1189
1190 return r;
1191
1192failure:
1193 mes_v11_0_hw_fini(adev);
1194 return r;
1195}
1196
1197static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
1198{
1199 mes_v11_0_enable(adev, false);
1200 return 0;
1201}
1202
1203static int mes_v11_0_hw_init(void *handle)
1204{
1205 int r;
1206 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1207
1208 if (!adev->enable_mes_kiq) {
1209 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1210 r = mes_v11_0_load_microcode(adev,
1211 AMDGPU_MES_SCHED_PIPE, true);
1212 if (r) {
1213 DRM_ERROR("failed to MES fw, r=%d\n", r);
1214 return r;
1215 }
1216 }
1217
1218 mes_v11_0_enable(adev, true);
1219 }
1220
1221 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1222 if (r)
1223 goto failure;
1224
1225 r = mes_v11_0_set_hw_resources(&adev->mes);
1226 if (r)
1227 goto failure;
1228
1229 mes_v11_0_init_aggregated_doorbell(&adev->mes);
1230
1231 r = mes_v11_0_query_sched_status(&adev->mes);
1232 if (r) {
1233 DRM_ERROR("MES is busy\n");
1234 goto failure;
1235 }
1236
1237 /*
1238 * Disable KIQ ring usage from the driver once MES is enabled.
1239 * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1240 * with MES enabled.
1241 */
1242 adev->gfx.kiq.ring.sched.ready = false;
1243 adev->mes.ring.sched.ready = true;
1244
1245 return 0;
1246
1247failure:
1248 mes_v11_0_hw_fini(adev);
1249 return r;
1250}
1251
1252static int mes_v11_0_hw_fini(void *handle)
1253{
1254 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1255
1256 adev->mes.ring.sched.ready = false;
1257 return 0;
1258}
1259
1260static int mes_v11_0_suspend(void *handle)
1261{
1262 int r;
1263 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1264
1265 r = amdgpu_mes_suspend(adev);
1266 if (r)
1267 return r;
1268
1269 return mes_v11_0_hw_fini(adev);
1270}
1271
1272static int mes_v11_0_resume(void *handle)
1273{
1274 int r;
1275 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1276
1277 r = mes_v11_0_hw_init(adev);
1278 if (r)
1279 return r;
1280
1281 return amdgpu_mes_resume(adev);
1282}
1283
1284static int mes_v11_0_late_init(void *handle)
1285{
1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1287
1288 if (!amdgpu_in_reset(adev))
1289 amdgpu_mes_self_test(adev);
1290
1291 return 0;
1292}
1293
1294static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
1295 .name = "mes_v11_0",
1296 .late_init = mes_v11_0_late_init,
1297 .sw_init = mes_v11_0_sw_init,
1298 .sw_fini = mes_v11_0_sw_fini,
1299 .hw_init = mes_v11_0_hw_init,
1300 .hw_fini = mes_v11_0_hw_fini,
1301 .suspend = mes_v11_0_suspend,
1302 .resume = mes_v11_0_resume,
1303};
1304
1305const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
1306 .type = AMD_IP_BLOCK_TYPE_MES,
1307 .major = 11,
1308 .minor = 0,
1309 .rev = 0,
1310 .funcs = &mes_v11_0_ip_funcs,
1311};