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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Copyright (C) 2019 Western Digital Corporation or its affiliates.
4 *
5 * Authors:
6 * Anup Patel <anup.patel@wdc.com>
7 */
8
9#ifndef __LINUX_KVM_RISCV_H
10#define __LINUX_KVM_RISCV_H
11
12#ifndef __ASSEMBLY__
13
14#include <linux/types.h>
15#include <asm/ptrace.h>
16
17#define __KVM_HAVE_READONLY_MEM
18
19#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
20
21#define KVM_INTERRUPT_SET -1U
22#define KVM_INTERRUPT_UNSET -2U
23
24/* for KVM_GET_REGS and KVM_SET_REGS */
25struct kvm_regs {
26};
27
28/* for KVM_GET_FPU and KVM_SET_FPU */
29struct kvm_fpu {
30};
31
32/* KVM Debug exit structure */
33struct kvm_debug_exit_arch {
34};
35
36/* for KVM_SET_GUEST_DEBUG */
37struct kvm_guest_debug_arch {
38};
39
40/* definition of registers in kvm_run */
41struct kvm_sync_regs {
42};
43
44/* for KVM_GET_SREGS and KVM_SET_SREGS */
45struct kvm_sregs {
46};
47
48/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
49struct kvm_riscv_config {
50 unsigned long isa;
51};
52
53/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
54struct kvm_riscv_core {
55 struct user_regs_struct regs;
56 unsigned long mode;
57};
58
59/* Possible privilege modes for kvm_riscv_core */
60#define KVM_RISCV_MODE_S 1
61#define KVM_RISCV_MODE_U 0
62
63/* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
64struct kvm_riscv_csr {
65 unsigned long sstatus;
66 unsigned long sie;
67 unsigned long stvec;
68 unsigned long sscratch;
69 unsigned long sepc;
70 unsigned long scause;
71 unsigned long stval;
72 unsigned long sip;
73 unsigned long satp;
74 unsigned long scounteren;
75};
76
77/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
78struct kvm_riscv_timer {
79 __u64 frequency;
80 __u64 time;
81 __u64 compare;
82 __u64 state;
83};
84
85/*
86 * ISA extension IDs specific to KVM. This is not the same as the host ISA
87 * extension IDs as that is internal to the host and should not be exposed
88 * to the guest. This should always be contiguous to keep the mapping simple
89 * in KVM implementation.
90 */
91enum KVM_RISCV_ISA_EXT_ID {
92 KVM_RISCV_ISA_EXT_A = 0,
93 KVM_RISCV_ISA_EXT_C,
94 KVM_RISCV_ISA_EXT_D,
95 KVM_RISCV_ISA_EXT_F,
96 KVM_RISCV_ISA_EXT_H,
97 KVM_RISCV_ISA_EXT_I,
98 KVM_RISCV_ISA_EXT_M,
99 KVM_RISCV_ISA_EXT_SVPBMT,
100 KVM_RISCV_ISA_EXT_SSTC,
101 KVM_RISCV_ISA_EXT_MAX,
102};
103
104/* Possible states for kvm_riscv_timer */
105#define KVM_RISCV_TIMER_STATE_OFF 0
106#define KVM_RISCV_TIMER_STATE_ON 1
107
108#define KVM_REG_SIZE(id) \
109 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
110
111/* If you need to interpret the index values, here is the key: */
112#define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000
113#define KVM_REG_RISCV_TYPE_SHIFT 24
114
115/* Config registers are mapped as type 1 */
116#define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
117#define KVM_REG_RISCV_CONFIG_REG(name) \
118 (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
119
120/* Core registers are mapped as type 2 */
121#define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
122#define KVM_REG_RISCV_CORE_REG(name) \
123 (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
124
125/* Control and status registers are mapped as type 3 */
126#define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
127#define KVM_REG_RISCV_CSR_REG(name) \
128 (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
129
130/* Timer registers are mapped as type 4 */
131#define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
132#define KVM_REG_RISCV_TIMER_REG(name) \
133 (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
134
135/* F extension registers are mapped as type 5 */
136#define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
137#define KVM_REG_RISCV_FP_F_REG(name) \
138 (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
139
140/* D extension registers are mapped as type 6 */
141#define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
142#define KVM_REG_RISCV_FP_D_REG(name) \
143 (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
144
145/* ISA Extension registers are mapped as type 7 */
146#define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
147
148#endif
149
150#endif /* __LINUX_KVM_RISCV_H */