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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2015 Regents of the University of California
4 */
5
6#ifndef _ASM_RISCV_CACHEFLUSH_H
7#define _ASM_RISCV_CACHEFLUSH_H
8
9#include <linux/mm.h>
10
11static inline void local_flush_icache_all(void)
12{
13 asm volatile ("fence.i" ::: "memory");
14}
15
16#define PG_dcache_clean PG_arch_1
17
18static inline void flush_dcache_page(struct page *page)
19{
20 if (test_bit(PG_dcache_clean, &page->flags))
21 clear_bit(PG_dcache_clean, &page->flags);
22}
23#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
24
25/*
26 * RISC-V doesn't have an instruction to flush parts of the instruction cache,
27 * so instead we just flush the whole thing.
28 */
29#define flush_icache_range(start, end) flush_icache_all()
30#define flush_icache_user_page(vma, pg, addr, len) \
31 flush_icache_mm(vma->vm_mm, 0)
32
33#ifndef CONFIG_SMP
34
35#define flush_icache_all() local_flush_icache_all()
36#define flush_icache_mm(mm, local) flush_icache_all()
37
38#else /* CONFIG_SMP */
39
40void flush_icache_all(void);
41void flush_icache_mm(struct mm_struct *mm, bool local);
42
43#endif /* CONFIG_SMP */
44
45/*
46 * The T-Head CMO errata internally probe the CBOM block size, but otherwise
47 * don't depend on Zicbom.
48 */
49extern unsigned int riscv_cbom_block_size;
50#ifdef CONFIG_RISCV_ISA_ZICBOM
51void riscv_init_cbom_blocksize(void);
52#else
53static inline void riscv_init_cbom_blocksize(void) { }
54#endif
55
56#ifdef CONFIG_RISCV_DMA_NONCOHERENT
57void riscv_noncoherent_supported(void);
58#endif
59
60/*
61 * Bits in sys_riscv_flush_icache()'s flags argument.
62 */
63#define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL
64#define SYS_RISCV_FLUSH_ICACHE_ALL (SYS_RISCV_FLUSH_ICACHE_LOCAL)
65
66#include <asm-generic/cacheflush.h>
67
68#endif /* _ASM_RISCV_CACHEFLUSH_H */