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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2#ifndef _ASM_POWERPC_PROCESSOR_H
3#define _ASM_POWERPC_PROCESSOR_H
4
5/*
6 * Copyright (C) 2001 PPC 64 Team, IBM Corp
7 */
8
9#include <vdso/processor.h>
10
11#include <asm/reg.h>
12
13#ifdef CONFIG_VSX
14#define TS_FPRWIDTH 2
15
16#ifdef __BIG_ENDIAN__
17#define TS_FPROFFSET 0
18#define TS_VSRLOWOFFSET 1
19#else
20#define TS_FPROFFSET 1
21#define TS_VSRLOWOFFSET 0
22#endif
23
24#else
25#define TS_FPRWIDTH 1
26#define TS_FPROFFSET 0
27#endif
28
29#ifdef CONFIG_PPC64
30/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
31#define PPR_PRIORITY 3
32#ifdef __ASSEMBLY__
33#define DEFAULT_PPR (PPR_PRIORITY << 50)
34#else
35#define DEFAULT_PPR ((u64)PPR_PRIORITY << 50)
36#endif /* __ASSEMBLY__ */
37#endif /* CONFIG_PPC64 */
38
39#ifndef __ASSEMBLY__
40#include <linux/types.h>
41#include <linux/thread_info.h>
42#include <asm/ptrace.h>
43#include <asm/hw_breakpoint.h>
44
45/* We do _not_ want to define new machine types at all, those must die
46 * in favor of using the device-tree
47 * -- BenH.
48 */
49
50/* PREP sub-platform types. Unused */
51#define _PREP_Motorola 0x01 /* motorola prep */
52#define _PREP_Firm 0x02 /* firmworks prep */
53#define _PREP_IBM 0x00 /* ibm prep */
54#define _PREP_Bull 0x03 /* bull prep */
55
56/* CHRP sub-platform types. These are arbitrary */
57#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
58#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
59#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
60#define _CHRP_briq 0x07 /* TotalImpact's briQ */
61
62#if defined(__KERNEL__) && defined(CONFIG_PPC32)
63
64extern int _chrp_type;
65
66#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
67
68#ifdef __KERNEL__
69
70#ifdef CONFIG_PPC64
71#include <asm/task_size_64.h>
72#else
73#include <asm/task_size_32.h>
74#endif
75
76struct task_struct;
77void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
78void release_thread(struct task_struct *);
79
80#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
81#define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
82
83/* FP and VSX 0-31 register set */
84struct thread_fp_state {
85 u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
86 u64 fpscr; /* Floating point status */
87};
88
89/* Complete AltiVec register set including VSCR */
90struct thread_vr_state {
91 vector128 vr[32] __attribute__((aligned(16)));
92 vector128 vscr __attribute__((aligned(16)));
93};
94
95struct debug_reg {
96#ifdef CONFIG_PPC_ADV_DEBUG_REGS
97 /*
98 * The following help to manage the use of Debug Control Registers
99 * om the BookE platforms.
100 */
101 uint32_t dbcr0;
102 uint32_t dbcr1;
103#ifdef CONFIG_BOOKE
104 uint32_t dbcr2;
105#endif
106 /*
107 * The stored value of the DBSR register will be the value at the
108 * last debug interrupt. This register can only be read from the
109 * user (will never be written to) and has value while helping to
110 * describe the reason for the last debug trap. Torez
111 */
112 uint32_t dbsr;
113 /*
114 * The following will contain addresses used by debug applications
115 * to help trace and trap on particular address locations.
116 * The bits in the Debug Control Registers above help define which
117 * of the following registers will contain valid data and/or addresses.
118 */
119 unsigned long iac1;
120 unsigned long iac2;
121#if CONFIG_PPC_ADV_DEBUG_IACS > 2
122 unsigned long iac3;
123 unsigned long iac4;
124#endif
125 unsigned long dac1;
126 unsigned long dac2;
127#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
128 unsigned long dvc1;
129 unsigned long dvc2;
130#endif
131#endif
132};
133
134struct thread_struct {
135 unsigned long ksp; /* Kernel stack pointer */
136
137#ifdef CONFIG_PPC64
138 unsigned long ksp_vsid;
139#endif
140 struct pt_regs *regs; /* Pointer to saved register state */
141#ifdef CONFIG_BOOKE
142 /* BookE base exception scratch space; align on cacheline */
143 unsigned long normsave[8] ____cacheline_aligned;
144#endif
145#ifdef CONFIG_PPC32
146 void *pgdir; /* root of page-table tree */
147#ifdef CONFIG_PPC_RTAS
148 unsigned long rtas_sp; /* stack pointer for when in RTAS */
149#endif
150#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
151 unsigned long kuap; /* opened segments for user access */
152#endif
153 unsigned long srr0;
154 unsigned long srr1;
155 unsigned long dar;
156 unsigned long dsisr;
157#ifdef CONFIG_PPC_BOOK3S_32
158 unsigned long r0, r3, r4, r5, r6, r8, r9, r11;
159 unsigned long lr, ctr;
160 unsigned long sr0;
161#endif
162#endif /* CONFIG_PPC32 */
163#if defined(CONFIG_BOOKE_OR_40x) && defined(CONFIG_PPC_KUAP)
164 unsigned long pid; /* value written in PID reg. at interrupt exit */
165#endif
166 /* Debug Registers */
167 struct debug_reg debug;
168#ifdef CONFIG_PPC_FPU_REGS
169 struct thread_fp_state fp_state;
170 struct thread_fp_state *fp_save_area;
171#endif
172 int fpexc_mode; /* floating-point exception mode */
173 unsigned int align_ctl; /* alignment handling control */
174#ifdef CONFIG_HAVE_HW_BREAKPOINT
175 struct perf_event *ptrace_bps[HBP_NUM_MAX];
176 /*
177 * Helps identify source of single-step exception and subsequent
178 * hw-breakpoint enablement
179 */
180 struct perf_event *last_hit_ubp[HBP_NUM_MAX];
181#endif /* CONFIG_HAVE_HW_BREAKPOINT */
182 struct arch_hw_breakpoint hw_brk[HBP_NUM_MAX]; /* hardware breakpoint info */
183 unsigned long trap_nr; /* last trap # on this thread */
184 u8 load_slb; /* Ages out SLB preload cache entries */
185 u8 load_fp;
186#ifdef CONFIG_ALTIVEC
187 u8 load_vec;
188 struct thread_vr_state vr_state;
189 struct thread_vr_state *vr_save_area;
190 unsigned long vrsave;
191 int used_vr; /* set if process has used altivec */
192#endif /* CONFIG_ALTIVEC */
193#ifdef CONFIG_VSX
194 /* VSR status */
195 int used_vsr; /* set if process has used VSX */
196#endif /* CONFIG_VSX */
197#ifdef CONFIG_SPE
198 struct_group(spe,
199 unsigned long evr[32]; /* upper 32-bits of SPE regs */
200 u64 acc; /* Accumulator */
201 );
202 unsigned long spefscr; /* SPE & eFP status */
203 unsigned long spefscr_last; /* SPEFSCR value on last prctl
204 call or trap return */
205 int used_spe; /* set if process has used spe */
206#endif /* CONFIG_SPE */
207#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
208 u8 load_tm;
209 u64 tm_tfhar; /* Transaction fail handler addr */
210 u64 tm_texasr; /* Transaction exception & summary */
211 u64 tm_tfiar; /* Transaction fail instr address reg */
212 struct pt_regs ckpt_regs; /* Checkpointed registers */
213
214 unsigned long tm_tar;
215 unsigned long tm_ppr;
216 unsigned long tm_dscr;
217 unsigned long tm_amr;
218
219 /*
220 * Checkpointed FP and VSX 0-31 register set.
221 *
222 * When a transaction is active/signalled/scheduled etc., *regs is the
223 * most recent set of/speculated GPRs with ckpt_regs being the older
224 * checkpointed regs to which we roll back if transaction aborts.
225 *
226 * These are analogous to how ckpt_regs and pt_regs work
227 */
228 struct thread_fp_state ckfp_state; /* Checkpointed FP state */
229 struct thread_vr_state ckvr_state; /* Checkpointed VR state */
230 unsigned long ckvrsave; /* Checkpointed VRSAVE */
231#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
232#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
233 void* kvm_shadow_vcpu; /* KVM internal data */
234#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
235#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
236 struct kvm_vcpu *kvm_vcpu;
237#endif
238#ifdef CONFIG_PPC64
239 unsigned long dscr;
240 unsigned long fscr;
241 /*
242 * This member element dscr_inherit indicates that the process
243 * has explicitly attempted and changed the DSCR register value
244 * for itself. Hence kernel wont use the default CPU DSCR value
245 * contained in the PACA structure anymore during process context
246 * switch. Once this variable is set, this behaviour will also be
247 * inherited to all the children of this process from that point
248 * onwards.
249 */
250 int dscr_inherit;
251 unsigned long tidr;
252#endif
253#ifdef CONFIG_PPC_BOOK3S_64
254 unsigned long tar;
255 unsigned long ebbrr;
256 unsigned long ebbhr;
257 unsigned long bescr;
258 unsigned long siar;
259 unsigned long sdar;
260 unsigned long sier;
261 unsigned long mmcr2;
262 unsigned mmcr0;
263
264 unsigned used_ebb;
265 unsigned long mmcr3;
266 unsigned long sier2;
267 unsigned long sier3;
268
269#endif
270};
271
272#define ARCH_MIN_TASKALIGN 16
273
274#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
275#define INIT_SP_LIMIT ((unsigned long)&init_stack)
276
277#ifdef CONFIG_SPE
278#define SPEFSCR_INIT \
279 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
280 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
281#else
282#define SPEFSCR_INIT
283#endif
284
285#ifdef CONFIG_PPC_BOOK3S_32
286#define SR0_INIT .sr0 = IS_ENABLED(CONFIG_PPC_KUEP) ? SR_NX : 0,
287#else
288#define SR0_INIT
289#endif
290
291#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
292#define INIT_THREAD { \
293 .ksp = INIT_SP, \
294 .pgdir = swapper_pg_dir, \
295 .kuap = ~0UL, /* KUAP_NONE */ \
296 .fpexc_mode = MSR_FE0 | MSR_FE1, \
297 SPEFSCR_INIT \
298 SR0_INIT \
299}
300#elif defined(CONFIG_PPC32)
301#define INIT_THREAD { \
302 .ksp = INIT_SP, \
303 .pgdir = swapper_pg_dir, \
304 .fpexc_mode = MSR_FE0 | MSR_FE1, \
305 SPEFSCR_INIT \
306 SR0_INIT \
307}
308#else
309#define INIT_THREAD { \
310 .ksp = INIT_SP, \
311 .fpexc_mode = 0, \
312}
313#endif
314
315#define task_pt_regs(tsk) ((tsk)->thread.regs)
316
317unsigned long __get_wchan(struct task_struct *p);
318
319#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
320#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
321
322/* Get/set floating-point exception mode */
323#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
324#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
325
326extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
327extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
328
329#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
330#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
331
332extern int get_endian(struct task_struct *tsk, unsigned long adr);
333extern int set_endian(struct task_struct *tsk, unsigned int val);
334
335#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
336#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
337
338extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
339extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
340
341extern void load_fp_state(struct thread_fp_state *fp);
342extern void store_fp_state(struct thread_fp_state *fp);
343extern void load_vr_state(struct thread_vr_state *vr);
344extern void store_vr_state(struct thread_vr_state *vr);
345
346static inline unsigned int __unpack_fe01(unsigned long msr_bits)
347{
348 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
349}
350
351static inline unsigned long __pack_fe01(unsigned int fpmode)
352{
353 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
354}
355
356#ifdef CONFIG_PPC64
357
358#define spin_begin() HMT_low()
359
360#define spin_cpu_relax() barrier()
361
362#define spin_end() HMT_medium()
363
364#endif
365
366/* Check that a certain kernel stack pointer is valid in task_struct p */
367int validate_sp(unsigned long sp, struct task_struct *p,
368 unsigned long nbytes);
369
370/*
371 * Prefetch macros.
372 */
373#define ARCH_HAS_PREFETCH
374#define ARCH_HAS_PREFETCHW
375#define ARCH_HAS_SPINLOCK_PREFETCH
376
377static inline void prefetch(const void *x)
378{
379 if (unlikely(!x))
380 return;
381
382 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
383}
384
385static inline void prefetchw(const void *x)
386{
387 if (unlikely(!x))
388 return;
389
390 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
391}
392
393#define spin_lock_prefetch(x) prefetchw(x)
394
395/* asm stubs */
396extern unsigned long isa300_idle_stop_noloss(unsigned long psscr_val);
397extern unsigned long isa300_idle_stop_mayloss(unsigned long psscr_val);
398extern unsigned long isa206_idle_insn_mayloss(unsigned long type);
399#ifdef CONFIG_PPC_970_NAP
400extern void power4_idle_nap(void);
401void power4_idle_nap_return(void);
402#endif
403
404extern unsigned long cpuidle_disable;
405enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
406
407extern int powersave_nap; /* set if nap mode can be used in idle loop */
408
409extern void power7_idle_type(unsigned long type);
410extern void arch300_idle_type(unsigned long stop_psscr_val,
411 unsigned long stop_psscr_mask);
412void pnv_power9_force_smt4_catch(void);
413void pnv_power9_force_smt4_release(void);
414
415extern int fix_alignment(struct pt_regs *);
416
417#ifdef CONFIG_PPC64
418/*
419 * We handle most unaligned accesses in hardware. On the other hand
420 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
421 * powers of 2 writes until it reaches sufficient alignment).
422 *
423 * Based on this we disable the IP header alignment in network drivers.
424 */
425#define NET_IP_ALIGN 0
426#endif
427
428int do_mathemu(struct pt_regs *regs);
429
430/* VMX copying */
431int enter_vmx_usercopy(void);
432int exit_vmx_usercopy(void);
433int enter_vmx_ops(void);
434void *exit_vmx_ops(void *dest);
435
436#endif /* __KERNEL__ */
437#endif /* __ASSEMBLY__ */
438#endif /* _ASM_POWERPC_PROCESSOR_H */