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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7#ifndef __ARM64_KVM_ARM_H__
8#define __ARM64_KVM_ARM_H__
9
10#include <asm/esr.h>
11#include <asm/memory.h>
12#include <asm/types.h>
13
14/* Hyp Configuration Register (HCR) bits */
15
16#define HCR_TID5 (UL(1) << 58)
17#define HCR_DCT (UL(1) << 57)
18#define HCR_ATA_SHIFT 56
19#define HCR_ATA (UL(1) << HCR_ATA_SHIFT)
20#define HCR_AMVOFFEN (UL(1) << 51)
21#define HCR_FIEN (UL(1) << 47)
22#define HCR_FWB (UL(1) << 46)
23#define HCR_API (UL(1) << 41)
24#define HCR_APK (UL(1) << 40)
25#define HCR_TEA (UL(1) << 37)
26#define HCR_TERR (UL(1) << 36)
27#define HCR_TLOR (UL(1) << 35)
28#define HCR_E2H (UL(1) << 34)
29#define HCR_ID (UL(1) << 33)
30#define HCR_CD (UL(1) << 32)
31#define HCR_RW_SHIFT 31
32#define HCR_RW (UL(1) << HCR_RW_SHIFT)
33#define HCR_TRVM (UL(1) << 30)
34#define HCR_HCD (UL(1) << 29)
35#define HCR_TDZ (UL(1) << 28)
36#define HCR_TGE (UL(1) << 27)
37#define HCR_TVM (UL(1) << 26)
38#define HCR_TTLB (UL(1) << 25)
39#define HCR_TPU (UL(1) << 24)
40#define HCR_TPC (UL(1) << 23) /* HCR_TPCP if FEAT_DPB */
41#define HCR_TSW (UL(1) << 22)
42#define HCR_TACR (UL(1) << 21)
43#define HCR_TIDCP (UL(1) << 20)
44#define HCR_TSC (UL(1) << 19)
45#define HCR_TID3 (UL(1) << 18)
46#define HCR_TID2 (UL(1) << 17)
47#define HCR_TID1 (UL(1) << 16)
48#define HCR_TID0 (UL(1) << 15)
49#define HCR_TWE (UL(1) << 14)
50#define HCR_TWI (UL(1) << 13)
51#define HCR_DC (UL(1) << 12)
52#define HCR_BSU (3 << 10)
53#define HCR_BSU_IS (UL(1) << 10)
54#define HCR_FB (UL(1) << 9)
55#define HCR_VSE (UL(1) << 8)
56#define HCR_VI (UL(1) << 7)
57#define HCR_VF (UL(1) << 6)
58#define HCR_AMO (UL(1) << 5)
59#define HCR_IMO (UL(1) << 4)
60#define HCR_FMO (UL(1) << 3)
61#define HCR_PTW (UL(1) << 2)
62#define HCR_SWIO (UL(1) << 1)
63#define HCR_VM (UL(1) << 0)
64#define HCR_RES0 ((UL(1) << 48) | (UL(1) << 39))
65
66/*
67 * The bits we set in HCR:
68 * TLOR: Trap LORegion register accesses
69 * RW: 64bit by default, can be overridden for 32bit VMs
70 * TACR: Trap ACTLR
71 * TSC: Trap SMC
72 * TSW: Trap cache operations by set/way
73 * TWE: Trap WFE
74 * TWI: Trap WFI
75 * TIDCP: Trap L2CTLR/L2ECTLR
76 * BSU_IS: Upgrade barriers to the inner shareable domain
77 * FB: Force broadcast of all maintenance operations
78 * AMO: Override CPSR.A and enable signaling with VA
79 * IMO: Override CPSR.I and enable signaling with VI
80 * FMO: Override CPSR.F and enable signaling with VF
81 * SWIO: Turn set/way invalidates into set/way clean+invalidate
82 * PTW: Take a stage2 fault if a stage1 walk steps in device memory
83 * TID3: Trap EL1 reads of group 3 ID registers
84 */
85#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
86 HCR_BSU_IS | HCR_FB | HCR_TACR | \
87 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
88 HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 )
89#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
90#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA)
91#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)
92#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
93
94/* TCR_EL2 Registers bits */
95#define TCR_EL2_RES1 ((1U << 31) | (1 << 23))
96#define TCR_EL2_TBI (1 << 20)
97#define TCR_EL2_PS_SHIFT 16
98#define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT)
99#define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT)
100#define TCR_EL2_TG0_MASK TCR_TG0_MASK
101#define TCR_EL2_SH0_MASK TCR_SH0_MASK
102#define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
103#define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
104#define TCR_EL2_T0SZ_MASK 0x3f
105#define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
106 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)
107
108/* VTCR_EL2 Registers bits */
109#define VTCR_EL2_RES1 (1U << 31)
110#define VTCR_EL2_HD (1 << 22)
111#define VTCR_EL2_HA (1 << 21)
112#define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT
113#define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK
114#define VTCR_EL2_TG0_MASK TCR_TG0_MASK
115#define VTCR_EL2_TG0_4K TCR_TG0_4K
116#define VTCR_EL2_TG0_16K TCR_TG0_16K
117#define VTCR_EL2_TG0_64K TCR_TG0_64K
118#define VTCR_EL2_SH0_MASK TCR_SH0_MASK
119#define VTCR_EL2_SH0_INNER TCR_SH0_INNER
120#define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
121#define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA
122#define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
123#define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA
124#define VTCR_EL2_SL0_SHIFT 6
125#define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT)
126#define VTCR_EL2_T0SZ_MASK 0x3f
127#define VTCR_EL2_VS_SHIFT 19
128#define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT)
129#define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT)
130
131#define VTCR_EL2_T0SZ(x) TCR_T0SZ(x)
132
133/*
134 * We configure the Stage-2 page tables to always restrict the IPA space to be
135 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
136 * not known to exist and will break with this configuration.
137 *
138 * The VTCR_EL2 is configured per VM and is initialised in kvm_arm_setup_stage2().
139 *
140 * Note that when using 4K pages, we concatenate two first level page tables
141 * together. With 16K pages, we concatenate 16 first level page tables.
142 *
143 */
144
145#define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
146 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)
147
148/*
149 * VTCR_EL2:SL0 indicates the entry level for Stage2 translation.
150 * Interestingly, it depends on the page size.
151 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
152 *
153 * -----------------------------------------
154 * | Entry level | 4K | 16K/64K |
155 * ------------------------------------------
156 * | Level: 0 | 2 | - |
157 * ------------------------------------------
158 * | Level: 1 | 1 | 2 |
159 * ------------------------------------------
160 * | Level: 2 | 0 | 1 |
161 * ------------------------------------------
162 * | Level: 3 | - | 0 |
163 * ------------------------------------------
164 *
165 * The table roughly translates to :
166 *
167 * SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
168 *
169 * Where TGRAN_SL0_BASE is a magic number depending on the page size:
170 * TGRAN_SL0_BASE(4K) = 2
171 * TGRAN_SL0_BASE(16K) = 3
172 * TGRAN_SL0_BASE(64K) = 3
173 * provided we take care of ruling out the unsupported cases and
174 * Entry_Level = 4 - Number_of_levels.
175 *
176 */
177#ifdef CONFIG_ARM64_64K_PAGES
178
179#define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K
180#define VTCR_EL2_TGRAN_SL0_BASE 3UL
181
182#elif defined(CONFIG_ARM64_16K_PAGES)
183
184#define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K
185#define VTCR_EL2_TGRAN_SL0_BASE 3UL
186
187#else /* 4K */
188
189#define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K
190#define VTCR_EL2_TGRAN_SL0_BASE 2UL
191
192#endif
193
194#define VTCR_EL2_LVLS_TO_SL0(levels) \
195 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
196#define VTCR_EL2_SL0_TO_LVLS(sl0) \
197 ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
198#define VTCR_EL2_LVLS(vtcr) \
199 VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT)
200
201#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN)
202#define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
203
204/*
205 * ARM VMSAv8-64 defines an algorithm for finding the translation table
206 * descriptors in section D4.2.8 in ARM DDI 0487C.a.
207 *
208 * The algorithm defines the expectations on the translation table
209 * addresses for each level, based on PAGE_SIZE, entry level
210 * and the translation table size (T0SZ). The variable "x" in the
211 * algorithm determines the alignment of a table base address at a given
212 * level and thus determines the alignment of VTTBR:BADDR for stage2
213 * page table entry level.
214 * Since the number of bits resolved at the entry level could vary
215 * depending on the T0SZ, the value of "x" is defined based on a
216 * Magic constant for a given PAGE_SIZE and Entry Level. The
217 * intermediate levels must be always aligned to the PAGE_SIZE (i.e,
218 * x = PAGE_SHIFT).
219 *
220 * The value of "x" for entry level is calculated as :
221 * x = Magic_N - T0SZ
222 *
223 * where Magic_N is an integer depending on the page size and the entry
224 * level of the page table as below:
225 *
226 * --------------------------------------------
227 * | Entry level | 4K 16K 64K |
228 * --------------------------------------------
229 * | Level: 0 (4 levels) | 28 | - | - |
230 * --------------------------------------------
231 * | Level: 1 (3 levels) | 37 | 31 | 25 |
232 * --------------------------------------------
233 * | Level: 2 (2 levels) | 46 | 42 | 38 |
234 * --------------------------------------------
235 * | Level: 3 (1 level) | - | 53 | 51 |
236 * --------------------------------------------
237 *
238 * We have a magic formula for the Magic_N below:
239 *
240 * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
241 *
242 * where Number_of_levels = (4 - Level). We are only interested in the
243 * value for Entry_Level for the stage2 page table.
244 *
245 * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
246 *
247 * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
248 * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
249 *
250 * Here is one way to explain the Magic Formula:
251 *
252 * x = log2(Size_of_Entry_Level_Table)
253 *
254 * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
255 * PAGE_SHIFT bits in the PTE, we have :
256 *
257 * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
258 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
259 * where n = number of levels, and since each pointer is 8bytes, we have:
260 *
261 * x = Bits_Entry_Level + 3
262 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n
263 *
264 * The only constraint here is that, we have to find the number of page table
265 * levels for a given IPA size (which we do, see stage2_pt_levels())
266 */
267#define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3)))
268
269#define VTTBR_CNP_BIT (UL(1))
270#define VTTBR_VMID_SHIFT (UL(48))
271#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
272
273/* Hyp System Trap Register */
274#define HSTR_EL2_T(x) (1 << x)
275
276/* Hyp Coprocessor Trap Register Shifts */
277#define CPTR_EL2_TFP_SHIFT 10
278
279/* Hyp Coprocessor Trap Register */
280#define CPTR_EL2_TCPAC (1U << 31)
281#define CPTR_EL2_TAM (1 << 30)
282#define CPTR_EL2_TTA (1 << 20)
283#define CPTR_EL2_TSM (1 << 12)
284#define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT)
285#define CPTR_EL2_TZ (1 << 8)
286#define CPTR_NVHE_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */
287#define CPTR_EL2_DEFAULT CPTR_NVHE_EL2_RES1
288#define CPTR_NVHE_EL2_RES0 (GENMASK(63, 32) | \
289 GENMASK(29, 21) | \
290 GENMASK(19, 14) | \
291 BIT(11))
292
293/* Hyp Debug Configuration Register bits */
294#define MDCR_EL2_E2TB_MASK (UL(0x3))
295#define MDCR_EL2_E2TB_SHIFT (UL(24))
296#define MDCR_EL2_HPMFZS (UL(1) << 36)
297#define MDCR_EL2_HPMFZO (UL(1) << 29)
298#define MDCR_EL2_MTPME (UL(1) << 28)
299#define MDCR_EL2_TDCC (UL(1) << 27)
300#define MDCR_EL2_HLP (UL(1) << 26)
301#define MDCR_EL2_HCCD (UL(1) << 23)
302#define MDCR_EL2_TTRF (UL(1) << 19)
303#define MDCR_EL2_HPMD (UL(1) << 17)
304#define MDCR_EL2_TPMS (UL(1) << 14)
305#define MDCR_EL2_E2PB_MASK (UL(0x3))
306#define MDCR_EL2_E2PB_SHIFT (UL(12))
307#define MDCR_EL2_TDRA (UL(1) << 11)
308#define MDCR_EL2_TDOSA (UL(1) << 10)
309#define MDCR_EL2_TDA (UL(1) << 9)
310#define MDCR_EL2_TDE (UL(1) << 8)
311#define MDCR_EL2_HPME (UL(1) << 7)
312#define MDCR_EL2_TPM (UL(1) << 6)
313#define MDCR_EL2_TPMCR (UL(1) << 5)
314#define MDCR_EL2_HPMN_MASK (UL(0x1F))
315#define MDCR_EL2_RES0 (GENMASK(63, 37) | \
316 GENMASK(35, 30) | \
317 GENMASK(25, 24) | \
318 GENMASK(22, 20) | \
319 BIT(18) | \
320 GENMASK(16, 15))
321
322/* For compatibility with fault code shared with 32-bit */
323#define FSC_FAULT ESR_ELx_FSC_FAULT
324#define FSC_ACCESS ESR_ELx_FSC_ACCESS
325#define FSC_PERM ESR_ELx_FSC_PERM
326#define FSC_SEA ESR_ELx_FSC_EXTABT
327#define FSC_SEA_TTW0 (0x14)
328#define FSC_SEA_TTW1 (0x15)
329#define FSC_SEA_TTW2 (0x16)
330#define FSC_SEA_TTW3 (0x17)
331#define FSC_SECC (0x18)
332#define FSC_SECC_TTW0 (0x1c)
333#define FSC_SECC_TTW1 (0x1d)
334#define FSC_SECC_TTW2 (0x1e)
335#define FSC_SECC_TTW3 (0x1f)
336
337/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
338#define HPFAR_MASK (~UL(0xf))
339/*
340 * We have
341 * PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12]
342 * HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12]
343 */
344#define PAR_TO_HPFAR(par) \
345 (((par) & GENMASK_ULL(PHYS_MASK_SHIFT - 1, 12)) >> 8)
346
347#define ECN(x) { ESR_ELx_EC_##x, #x }
348
349#define kvm_arm_exception_class \
350 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
351 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \
352 ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \
353 ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \
354 ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
355 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
356 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
357 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
358 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)
359
360#define CPACR_EL1_TTA (1 << 28)
361#define CPACR_EL1_DEFAULT (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN |\
362 CPACR_EL1_ZEN_EL1EN)
363
364#endif /* __ARM64_KVM_ARM_H__ */