Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5#ifndef __ASM_CACHE_H
6#define __ASM_CACHE_H
7
8#define L1_CACHE_SHIFT (6)
9#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
10
11#define CLIDR_LOUU_SHIFT 27
12#define CLIDR_LOC_SHIFT 24
13#define CLIDR_LOUIS_SHIFT 21
14
15#define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
16#define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
17#define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
18
19/*
20 * Memory returned by kmalloc() may be used for DMA, so we must make
21 * sure that all such allocations are cache aligned. Otherwise,
22 * unrelated code may cause parts of the buffer to be read into the
23 * cache before the transfer is done, causing old data to be seen by
24 * the CPU.
25 */
26#define ARCH_DMA_MINALIGN (128)
27
28#ifndef __ASSEMBLY__
29
30#include <linux/bitops.h>
31#include <linux/kasan-enabled.h>
32
33#include <asm/cputype.h>
34#include <asm/mte-def.h>
35#include <asm/sysreg.h>
36
37#ifdef CONFIG_KASAN_SW_TAGS
38#define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT)
39#elif defined(CONFIG_KASAN_HW_TAGS)
40static inline unsigned int arch_slab_minalign(void)
41{
42 return kasan_hw_tags_enabled() ? MTE_GRANULE_SIZE :
43 __alignof__(unsigned long long);
44}
45#define arch_slab_minalign() arch_slab_minalign()
46#endif
47
48#define CTR_CACHE_MINLINE_MASK \
49 (0xf << CTR_EL0_DMINLINE_SHIFT | \
50 CTR_EL0_IMINLINE_MASK << CTR_EL0_IMINLINE_SHIFT)
51
52#define CTR_L1IP(ctr) SYS_FIELD_GET(CTR_EL0, L1Ip, ctr)
53
54#define ICACHEF_ALIASING 0
55#define ICACHEF_VPIPT 1
56extern unsigned long __icache_flags;
57
58/*
59 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
60 * permitted in the I-cache.
61 */
62static inline int icache_is_aliasing(void)
63{
64 return test_bit(ICACHEF_ALIASING, &__icache_flags);
65}
66
67static __always_inline int icache_is_vpipt(void)
68{
69 return test_bit(ICACHEF_VPIPT, &__icache_flags);
70}
71
72static inline u32 cache_type_cwg(void)
73{
74 return SYS_FIELD_GET(CTR_EL0, CWG, read_cpuid_cachetype());
75}
76
77#define __read_mostly __section(".data..read_mostly")
78
79static inline int cache_line_size_of_cpu(void)
80{
81 u32 cwg = cache_type_cwg();
82
83 return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
84}
85
86int cache_line_size(void);
87
88/*
89 * Read the effective value of CTR_EL0.
90 *
91 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
92 * section D10.2.33 "CTR_EL0, Cache Type Register" :
93 *
94 * CTR_EL0.IDC reports the data cache clean requirements for
95 * instruction to data coherence.
96 *
97 * 0 - dcache clean to PoU is required unless :
98 * (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
99 * 1 - dcache clean to PoU is not required for i-to-d coherence.
100 *
101 * This routine provides the CTR_EL0 with the IDC field updated to the
102 * effective state.
103 */
104static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
105{
106 u32 ctr = read_cpuid_cachetype();
107
108 if (!(ctr & BIT(CTR_EL0_IDC_SHIFT))) {
109 u64 clidr = read_sysreg(clidr_el1);
110
111 if (CLIDR_LOC(clidr) == 0 ||
112 (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
113 ctr |= BIT(CTR_EL0_IDC_SHIFT);
114 }
115
116 return ctr;
117}
118
119#endif /* __ASSEMBLY__ */
120
121#endif