tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZN1D-DB Board
4 *
5 * Copyright (C) 2018 Renesas Electronics Europe Limited
6 *
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
12#include <dt-bindings/net/pcs-rzn1-miic.h>
13
14#include "r9a06g032.dtsi"
15
16/ {
17 model = "RZN1D-DB Board";
18 compatible = "renesas,rzn1d400-db", "renesas,r9a06g032";
19
20 chosen {
21 stdout-path = "serial0:115200n8";
22 };
23
24 aliases {
25 serial0 = &uart0;
26 };
27};
28
29ð_miic {
30 status = "okay";
31 renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
32};
33
34&gmac2 {
35 status = "okay";
36 phy-mode = "gmii";
37
38 fixed-link {
39 speed = <1000>;
40 full-duplex;
41 };
42};
43
44&mii_conv4 {
45 renesas,miic-input = <MIIC_SWITCH_PORTB>;
46 status = "okay";
47};
48
49&mii_conv5 {
50 renesas,miic-input = <MIIC_SWITCH_PORTA>;
51 status = "okay";
52};
53
54&pinctrl{
55 pins_eth3: pins_eth3 {
56 pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
57 <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
58 <RZN1_PINMUX(38, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
59 <RZN1_PINMUX(39, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
60 <RZN1_PINMUX(40, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
61 <RZN1_PINMUX(41, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
62 <RZN1_PINMUX(42, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
63 <RZN1_PINMUX(43, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
64 <RZN1_PINMUX(44, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
65 <RZN1_PINMUX(45, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
66 <RZN1_PINMUX(46, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
67 <RZN1_PINMUX(47, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
68 drive-strength = <6>;
69 bias-disable;
70 };
71
72 pins_eth4: pins_eth4 {
73 pinmux = <RZN1_PINMUX(48, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
74 <RZN1_PINMUX(49, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
75 <RZN1_PINMUX(50, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
76 <RZN1_PINMUX(51, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
77 <RZN1_PINMUX(52, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
78 <RZN1_PINMUX(53, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
79 <RZN1_PINMUX(54, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
80 <RZN1_PINMUX(55, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
81 <RZN1_PINMUX(56, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
82 <RZN1_PINMUX(57, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
83 <RZN1_PINMUX(58, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
84 <RZN1_PINMUX(59, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
85 drive-strength = <6>;
86 bias-disable;
87 };
88
89 pins_mdio1: pins_mdio1 {
90 pinmux = <RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)>,
91 <RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)>;
92 };
93};
94
95&rtc0 {
96 status = "okay";
97};
98
99&switch {
100 status = "okay";
101 #address-cells = <1>;
102 #size-cells = <0>;
103
104 pinctrl-names = "default";
105 pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>;
106
107 dsa,member = <0 0>;
108
109 mdio {
110 clock-frequency = <2500000>;
111
112 #address-cells = <1>;
113 #size-cells = <0>;
114
115 switch0phy4: ethernet-phy@4 {
116 reg = <4>;
117 micrel,led-mode = <1>;
118 };
119
120 switch0phy5: ethernet-phy@5 {
121 reg = <5>;
122 micrel,led-mode = <1>;
123 };
124 };
125};
126
127&switch_port0 {
128 label = "lan0";
129 phy-mode = "mii";
130 phy-handle = <&switch0phy5>;
131 status = "okay";
132};
133
134&switch_port1 {
135 label = "lan1";
136 phy-mode = "mii";
137 phy-handle = <&switch0phy4>;
138 status = "okay";
139};
140
141&switch_port4 {
142 status = "okay";
143};
144
145&uart0 {
146 status = "okay";
147};
148
149&wdt0 {
150 timeout-sec = <60>;
151 status = "okay";
152};