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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
3
4#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
5#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
6
7/**
8 * @file
9 * @defgroup bpmp_clock_ids Clock ID's
10 * @{
11 */
12/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
13#define TEGRA234_CLK_AHUB 4U
14/** @brief output of gate CLK_ENB_APB2APE */
15#define TEGRA234_CLK_APB2APE 5U
16/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
17#define TEGRA234_CLK_APE 6U
18/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
19#define TEGRA234_CLK_AUD_MCLK 7U
20/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
21#define TEGRA234_CLK_DMIC1 15U
22/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
23#define TEGRA234_CLK_DMIC2 16U
24/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
25#define TEGRA234_CLK_DMIC3 17U
26/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
27#define TEGRA234_CLK_DMIC4 18U
28/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
29#define TEGRA234_CLK_DSPK1 29U
30/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
31#define TEGRA234_CLK_DSPK2 30U
32/**
33 * @brief controls the EMC clock frequency.
34 * @details Doing a clk_set_rate on this clock will select the
35 * appropriate clock source, program the source rate and execute a
36 * specific sequence to switch to the new clock source for both memory
37 * controllers. This can be used to control the balance between memory
38 * throughput and memory controller power.
39 */
40#define TEGRA234_CLK_EMC 31U
41/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
42#define TEGRA234_CLK_HOST1X 46U
43/** @brief output of gate CLK_ENB_FUSE */
44#define TEGRA234_CLK_FUSE 40U
45/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
46#define TEGRA234_CLK_I2C1 48U
47/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
48#define TEGRA234_CLK_I2C2 49U
49/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
50#define TEGRA234_CLK_I2C3 50U
51/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
52#define TEGRA234_CLK_I2C4 51U
53/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
54#define TEGRA234_CLK_I2C6 52U
55/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
56#define TEGRA234_CLK_I2C7 53U
57/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
58#define TEGRA234_CLK_I2C8 54U
59/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
60#define TEGRA234_CLK_I2C9 55U
61/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
62#define TEGRA234_CLK_I2S1 56U
63/** @brief clock recovered from I2S1 input */
64#define TEGRA234_CLK_I2S1_SYNC_INPUT 57U
65/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
66#define TEGRA234_CLK_I2S2 58U
67/** @brief clock recovered from I2S2 input */
68#define TEGRA234_CLK_I2S2_SYNC_INPUT 59U
69/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
70#define TEGRA234_CLK_I2S3 60U
71/** @brief clock recovered from I2S3 input */
72#define TEGRA234_CLK_I2S3_SYNC_INPUT 61U
73/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
74#define TEGRA234_CLK_I2S4 62U
75/** @brief clock recovered from I2S4 input */
76#define TEGRA234_CLK_I2S4_SYNC_INPUT 63U
77/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
78#define TEGRA234_CLK_I2S5 64U
79/** @brief clock recovered from I2S5 input */
80#define TEGRA234_CLK_I2S5_SYNC_INPUT 65U
81/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */
82#define TEGRA234_CLK_I2S6 66U
83/** @brief clock recovered from I2S6 input */
84#define TEGRA234_CLK_I2S6_SYNC_INPUT 67U
85/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
86#define TEGRA234_CLK_PLLA 93U
87/** @brief PLLP clk output */
88#define TEGRA234_CLK_PLLP_OUT0 102U
89/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
90#define TEGRA234_CLK_PLLA_OUT0 104U
91/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
92#define TEGRA234_CLK_PWM1 105U
93/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
94#define TEGRA234_CLK_PWM2 106U
95/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
96#define TEGRA234_CLK_PWM3 107U
97/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
98#define TEGRA234_CLK_PWM4 108U
99/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
100#define TEGRA234_CLK_PWM5 109U
101/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
102#define TEGRA234_CLK_PWM6 110U
103/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
104#define TEGRA234_CLK_PWM7 111U
105/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
106#define TEGRA234_CLK_PWM8 112U
107/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
108#define TEGRA234_CLK_SDMMC4 123U
109/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
110#define TEGRA234_CLK_SYNC_DMIC1 139U
111/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
112#define TEGRA234_CLK_SYNC_DMIC2 140U
113/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
114#define TEGRA234_CLK_SYNC_DMIC3 141U
115/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
116#define TEGRA234_CLK_SYNC_DMIC4 142U
117/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
118#define TEGRA234_CLK_SYNC_DSPK1 143U
119/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
120#define TEGRA234_CLK_SYNC_DSPK2 144U
121/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
122#define TEGRA234_CLK_SYNC_I2S1 145U
123/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
124#define TEGRA234_CLK_SYNC_I2S2 146U
125/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
126#define TEGRA234_CLK_SYNC_I2S3 147U
127/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
128#define TEGRA234_CLK_SYNC_I2S4 148U
129/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
130#define TEGRA234_CLK_SYNC_I2S5 149U
131/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
132#define TEGRA234_CLK_SYNC_I2S6 150U
133/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
134#define TEGRA234_CLK_UARTA 155U
135/** @brief output of gate CLK_ENB_PEX1_CORE_6 */
136#define TEGRA234_CLK_PEX1_C6_CORE 161U
137/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
138#define TEGRA234_CLK_VIC 167U
139/** @brief output of gate CLK_ENB_PEX2_CORE_7 */
140#define TEGRA234_CLK_PEX2_C7_CORE 171U
141/** @brief output of gate CLK_ENB_PEX2_CORE_8 */
142#define TEGRA234_CLK_PEX2_C8_CORE 172U
143/** @brief output of gate CLK_ENB_PEX2_CORE_9 */
144#define TEGRA234_CLK_PEX2_C9_CORE 173U
145/** @brief output of gate CLK_ENB_PEX2_CORE_10 */
146#define TEGRA234_CLK_PEX2_C10_CORE 187U
147/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */
148#define TEGRA234_CLK_QSPI0_2X_PM 192U
149/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */
150#define TEGRA234_CLK_QSPI1_2X_PM 193U
151/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */
152#define TEGRA234_CLK_QSPI0_PM 194U
153/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */
154#define TEGRA234_CLK_QSPI1_PM 195U
155/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
156#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U
157/** @brief output of gate CLK_ENB_PEX0_CORE_0 */
158#define TEGRA234_CLK_PEX0_C0_CORE 220U
159/** @brief output of gate CLK_ENB_PEX0_CORE_1 */
160#define TEGRA234_CLK_PEX0_C1_CORE 221U
161/** @brief output of gate CLK_ENB_PEX0_CORE_2 */
162#define TEGRA234_CLK_PEX0_C2_CORE 222U
163/** @brief output of gate CLK_ENB_PEX0_CORE_3 */
164#define TEGRA234_CLK_PEX0_C3_CORE 223U
165/** @brief output of gate CLK_ENB_PEX0_CORE_4 */
166#define TEGRA234_CLK_PEX0_C4_CORE 224U
167/** @brief output of gate CLK_ENB_PEX1_CORE_5 */
168#define TEGRA234_CLK_PEX1_C5_CORE 225U
169/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
170#define TEGRA234_CLK_PLLC4 237U
171/** @brief RX clock recovered from MGBE0 lane input */
172#define TEGRA234_CLK_MGBE0_RX_INPUT 248U
173/** @brief RX clock recovered from MGBE1 lane input */
174#define TEGRA234_CLK_MGBE1_RX_INPUT 249U
175/** @brief RX clock recovered from MGBE2 lane input */
176#define TEGRA234_CLK_MGBE2_RX_INPUT 250U
177/** @brief RX clock recovered from MGBE3 lane input */
178#define TEGRA234_CLK_MGBE3_RX_INPUT 251U
179/** @brief 32K input clock provided by PMIC */
180#define TEGRA234_CLK_CLK_32K 289U
181/** @brief Monitored branch of MBGE0 RX input clock */
182#define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U
183/** @brief Monitored branch of MBGE1 RX input clock */
184#define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U
185/** @brief Monitored branch of MBGE2 RX input clock */
186#define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U
187/** @brief Monitored branch of MBGE3 RX input clock */
188#define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U
189/** @brief Monitored branch of MGBE0 RX PCS mux output */
190#define TEGRA234_CLK_MGBE0_RX_PCS_M 361U
191/** @brief Monitored branch of MGBE1 RX PCS mux output */
192#define TEGRA234_CLK_MGBE1_RX_PCS_M 362U
193/** @brief Monitored branch of MGBE2 RX PCS mux output */
194#define TEGRA234_CLK_MGBE2_RX_PCS_M 363U
195/** @brief Monitored branch of MGBE3 RX PCS mux output */
196#define TEGRA234_CLK_MGBE3_RX_PCS_M 364U
197/** @brief RX PCS clock recovered from MGBE0 lane input */
198#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U
199/** @brief RX PCS clock recovered from MGBE1 lane input */
200#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U
201/** @brief RX PCS clock recovered from MGBE2 lane input */
202#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U
203/** @brief RX PCS clock recovered from MGBE3 lane input */
204#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U
205/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */
206#define TEGRA234_CLK_MGBE0_RX_PCS 373U
207/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
208#define TEGRA234_CLK_MGBE0_TX 374U
209/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
210#define TEGRA234_CLK_MGBE0_TX_PCS 375U
211/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */
212#define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U
213/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */
214#define TEGRA234_CLK_MGBE0_MAC 377U
215/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */
216#define TEGRA234_CLK_MGBE0_MACSEC 378U
217/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */
218#define TEGRA234_CLK_MGBE0_EEE_PCS 379U
219/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */
220#define TEGRA234_CLK_MGBE0_APP 380U
221/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
222#define TEGRA234_CLK_MGBE0_PTP_REF 381U
223/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */
224#define TEGRA234_CLK_MGBE1_RX_PCS 382U
225/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
226#define TEGRA234_CLK_MGBE1_TX 383U
227/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */
228#define TEGRA234_CLK_MGBE1_TX_PCS 384U
229/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */
230#define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U
231/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */
232#define TEGRA234_CLK_MGBE1_MAC 386U
233/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */
234#define TEGRA234_CLK_MGBE1_EEE_PCS 388U
235/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */
236#define TEGRA234_CLK_MGBE1_APP 389U
237/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */
238#define TEGRA234_CLK_MGBE1_PTP_REF 390U
239/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */
240#define TEGRA234_CLK_MGBE2_RX_PCS 391U
241/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */
242#define TEGRA234_CLK_MGBE2_TX 392U
243/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */
244#define TEGRA234_CLK_MGBE2_TX_PCS 393U
245/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */
246#define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U
247/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */
248#define TEGRA234_CLK_MGBE2_MAC 395U
249/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */
250#define TEGRA234_CLK_MGBE2_EEE_PCS 397U
251/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */
252#define TEGRA234_CLK_MGBE2_APP 398U
253/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */
254#define TEGRA234_CLK_MGBE2_PTP_REF 399U
255/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */
256#define TEGRA234_CLK_MGBE3_RX_PCS 400U
257/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */
258#define TEGRA234_CLK_MGBE3_TX 401U
259/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */
260#define TEGRA234_CLK_MGBE3_TX_PCS 402U
261/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */
262#define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U
263/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */
264#define TEGRA234_CLK_MGBE3_MAC 404U
265/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */
266#define TEGRA234_CLK_MGBE3_MACSEC 405U
267/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */
268#define TEGRA234_CLK_MGBE3_EEE_PCS 406U
269/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */
270#define TEGRA234_CLK_MGBE3_APP 407U
271/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */
272#define TEGRA234_CLK_MGBE3_PTP_REF 408U
273/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
274#define TEGRA234_CLK_AZA_2XBIT 457U
275/** @brief aza_2xbitclk / 2 (aza_bitclk) */
276#define TEGRA234_CLK_AZA_BIT 458U
277
278#endif