tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3 */
4
5#ifndef UFS_QCOM_H_
6#define UFS_QCOM_H_
7
8#include <linux/reset-controller.h>
9#include <linux/reset.h>
10#include <ufs/ufshcd.h>
11
12#define MAX_UFS_QCOM_HOSTS 1
13#define MAX_U32 (~(u32)0)
14#define MPHY_TX_FSM_STATE 0x41
15#define TX_FSM_HIBERN8 0x1
16#define HBRN8_POLL_TOUT_MS 100
17#define DEFAULT_CLK_RATE_HZ 1000000
18#define BUS_VECTOR_NAME_LEN 32
19
20#define UFS_HW_VER_MAJOR_SHFT (28)
21#define UFS_HW_VER_MAJOR_MASK (0x000F << UFS_HW_VER_MAJOR_SHFT)
22#define UFS_HW_VER_MINOR_SHFT (16)
23#define UFS_HW_VER_MINOR_MASK (0x0FFF << UFS_HW_VER_MINOR_SHFT)
24#define UFS_HW_VER_STEP_SHFT (0)
25#define UFS_HW_VER_STEP_MASK (0xFFFF << UFS_HW_VER_STEP_SHFT)
26
27/* vendor specific pre-defined parameters */
28#define SLOW 1
29#define FAST 2
30
31#define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B
32
33/* QCOM UFS host controller vendor specific registers */
34enum {
35 REG_UFS_SYS1CLK_1US = 0xC0,
36 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
37 REG_UFS_LOCAL_PORT_ID_REG = 0xC8,
38 REG_UFS_PA_ERR_CODE = 0xCC,
39 REG_UFS_RETRY_TIMER_REG = 0xD0,
40 REG_UFS_PA_LINK_STARTUP_TIMER = 0xD8,
41 REG_UFS_CFG1 = 0xDC,
42 REG_UFS_CFG2 = 0xE0,
43 REG_UFS_HW_VERSION = 0xE4,
44
45 UFS_TEST_BUS = 0xE8,
46 UFS_TEST_BUS_CTRL_0 = 0xEC,
47 UFS_TEST_BUS_CTRL_1 = 0xF0,
48 UFS_TEST_BUS_CTRL_2 = 0xF4,
49 UFS_UNIPRO_CFG = 0xF8,
50
51 /*
52 * QCOM UFS host controller vendor specific registers
53 * added in HW Version 3.0.0
54 */
55 UFS_AH8_CFG = 0xFC,
56};
57
58/* QCOM UFS host controller vendor specific debug registers */
59enum {
60 UFS_DBG_RD_REG_UAWM = 0x100,
61 UFS_DBG_RD_REG_UARM = 0x200,
62 UFS_DBG_RD_REG_TXUC = 0x300,
63 UFS_DBG_RD_REG_RXUC = 0x400,
64 UFS_DBG_RD_REG_DFC = 0x500,
65 UFS_DBG_RD_REG_TRLUT = 0x600,
66 UFS_DBG_RD_REG_TMRLUT = 0x700,
67 UFS_UFS_DBG_RD_REG_OCSC = 0x800,
68
69 UFS_UFS_DBG_RD_DESC_RAM = 0x1500,
70 UFS_UFS_DBG_RD_PRDT_RAM = 0x1700,
71 UFS_UFS_DBG_RD_RESP_RAM = 0x1800,
72 UFS_UFS_DBG_RD_EDTL_RAM = 0x1900,
73};
74
75#define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x)
76#define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x)
77
78/* bit definitions for REG_UFS_CFG1 register */
79#define QUNIPRO_SEL 0x1
80#define UTP_DBG_RAMS_EN 0x20000
81#define TEST_BUS_EN BIT(18)
82#define TEST_BUS_SEL GENMASK(22, 19)
83#define UFS_REG_TEST_BUS_EN BIT(30)
84
85/* bit definitions for REG_UFS_CFG2 register */
86#define UAWM_HW_CGC_EN (1 << 0)
87#define UARM_HW_CGC_EN (1 << 1)
88#define TXUC_HW_CGC_EN (1 << 2)
89#define RXUC_HW_CGC_EN (1 << 3)
90#define DFC_HW_CGC_EN (1 << 4)
91#define TRLUT_HW_CGC_EN (1 << 5)
92#define TMRLUT_HW_CGC_EN (1 << 6)
93#define OCSC_HW_CGC_EN (1 << 7)
94
95/* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
96#define TEST_BUS_SUB_SEL_MASK 0x1F /* All XXX_SEL fields are 5 bits wide */
97
98#define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
99 TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
100 DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\
101 TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
102
103/* bit offset */
104enum {
105 OFFSET_UFS_PHY_SOFT_RESET = 1,
106 OFFSET_CLK_NS_REG = 10,
107};
108
109/* bit masks */
110enum {
111 MASK_UFS_PHY_SOFT_RESET = 0x2,
112 MASK_TX_SYMBOL_CLK_1US_REG = 0x3FF,
113 MASK_CLK_NS_REG = 0xFFFC00,
114};
115
116/* QCOM UFS debug print bit mask */
117#define UFS_QCOM_DBG_PRINT_REGS_EN BIT(0)
118#define UFS_QCOM_DBG_PRINT_ICE_REGS_EN BIT(1)
119#define UFS_QCOM_DBG_PRINT_TEST_BUS_EN BIT(2)
120
121#define UFS_QCOM_DBG_PRINT_ALL \
122 (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_ICE_REGS_EN | \
123 UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
124
125/* QUniPro Vendor specific attributes */
126#define PA_VS_CONFIG_REG1 0x9000
127#define DME_VS_CORE_CLK_CTRL 0xD002
128/* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
129#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8)
130#define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK 0xFF
131
132static inline void
133ufs_qcom_get_controller_revision(struct ufs_hba *hba,
134 u8 *major, u16 *minor, u16 *step)
135{
136 u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
137
138 *major = (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT;
139 *minor = (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT;
140 *step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT;
141};
142
143static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
144{
145 ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
146 1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
147
148 /*
149 * Make sure assertion of ufs phy reset is written to
150 * register before returning
151 */
152 mb();
153}
154
155static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
156{
157 ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
158 0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
159
160 /*
161 * Make sure de-assertion of ufs phy reset is written to
162 * register before returning
163 */
164 mb();
165}
166
167/* Host controller hardware version: major.minor.step */
168struct ufs_hw_version {
169 u16 step;
170 u16 minor;
171 u8 major;
172};
173
174struct ufs_qcom_testbus {
175 u8 select_major;
176 u8 select_minor;
177};
178
179struct gpio_desc;
180
181struct ufs_qcom_host {
182 /*
183 * Set this capability if host controller supports the QUniPro mode
184 * and if driver wants the Host controller to operate in QUniPro mode.
185 * Note: By default this capability will be kept enabled if host
186 * controller supports the QUniPro mode.
187 */
188 #define UFS_QCOM_CAP_QUNIPRO 0x1
189
190 /*
191 * Set this capability if host controller can retain the secure
192 * configuration even after UFS controller core power collapse.
193 */
194 #define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE 0x2
195 u32 caps;
196
197 struct phy *generic_phy;
198 struct ufs_hba *hba;
199 struct ufs_pa_layer_attr dev_req_params;
200 struct clk *rx_l0_sync_clk;
201 struct clk *tx_l0_sync_clk;
202 struct clk *rx_l1_sync_clk;
203 struct clk *tx_l1_sync_clk;
204 bool is_lane_clks_enabled;
205
206 void __iomem *dev_ref_clk_ctrl_mmio;
207 bool is_dev_ref_clk_enabled;
208 struct ufs_hw_version hw_ver;
209#ifdef CONFIG_SCSI_UFS_CRYPTO
210 void __iomem *ice_mmio;
211#endif
212
213 u32 dev_ref_clk_en_mask;
214
215 /* Bitmask for enabling debug prints */
216 u32 dbg_print_en;
217 struct ufs_qcom_testbus testbus;
218
219 /* Reset control of HCI */
220 struct reset_control *core_reset;
221 struct reset_controller_dev rcdev;
222
223 struct gpio_desc *device_reset;
224};
225
226static inline u32
227ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg)
228{
229 if (host->hw_ver.major <= 0x02)
230 return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg);
231
232 return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg);
233};
234
235#define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba)
236#define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba)
237#define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
238
239int ufs_qcom_testbus_config(struct ufs_qcom_host *host);
240
241static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host)
242{
243 return host->caps & UFS_QCOM_CAP_QUNIPRO;
244}
245
246/* ufs-qcom-ice.c */
247
248#ifdef CONFIG_SCSI_UFS_CRYPTO
249int ufs_qcom_ice_init(struct ufs_qcom_host *host);
250int ufs_qcom_ice_enable(struct ufs_qcom_host *host);
251int ufs_qcom_ice_resume(struct ufs_qcom_host *host);
252int ufs_qcom_ice_program_key(struct ufs_hba *hba,
253 const union ufs_crypto_cfg_entry *cfg, int slot);
254#else
255static inline int ufs_qcom_ice_init(struct ufs_qcom_host *host)
256{
257 return 0;
258}
259static inline int ufs_qcom_ice_enable(struct ufs_qcom_host *host)
260{
261 return 0;
262}
263static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
264{
265 return 0;
266}
267#define ufs_qcom_ice_program_key NULL
268#endif /* !CONFIG_SCSI_UFS_CRYPTO */
269
270#endif /* UFS_QCOM_H_ */