tjh.dev
Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
6 *
7 */
8#include <linux/clk.h>
9#include <linux/iopoll.h>
10#include <linux/of.h>
11#include <linux/module.h>
12#include <linux/pm_runtime.h>
13#include <linux/property.h>
14#include <linux/regmap.h>
15#include <linux/sys_soc.h>
16
17#include "cqhci.h"
18#include "sdhci-pltfm.h"
19
20/* CTL_CFG Registers */
21#define CTL_CFG_2 0x14
22#define CTL_CFG_3 0x18
23
24#define SLOTTYPE_MASK GENMASK(31, 30)
25#define SLOTTYPE_EMBEDDED BIT(30)
26#define TUNINGFORSDR50_MASK BIT(13)
27
28/* PHY Registers */
29#define PHY_CTRL1 0x100
30#define PHY_CTRL2 0x104
31#define PHY_CTRL3 0x108
32#define PHY_CTRL4 0x10C
33#define PHY_CTRL5 0x110
34#define PHY_CTRL6 0x114
35#define PHY_STAT1 0x130
36#define PHY_STAT2 0x134
37
38#define IOMUX_ENABLE_SHIFT 31
39#define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
40#define OTAPDLYENA_SHIFT 20
41#define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
42#define OTAPDLYSEL_SHIFT 12
43#define OTAPDLYSEL_MASK GENMASK(15, 12)
44#define STRBSEL_SHIFT 24
45#define STRBSEL_4BIT_MASK GENMASK(27, 24)
46#define STRBSEL_8BIT_MASK GENMASK(31, 24)
47#define SEL50_SHIFT 8
48#define SEL50_MASK BIT(SEL50_SHIFT)
49#define SEL100_SHIFT 9
50#define SEL100_MASK BIT(SEL100_SHIFT)
51#define FREQSEL_SHIFT 8
52#define FREQSEL_MASK GENMASK(10, 8)
53#define CLKBUFSEL_SHIFT 0
54#define CLKBUFSEL_MASK GENMASK(2, 0)
55#define DLL_TRIM_ICP_SHIFT 4
56#define DLL_TRIM_ICP_MASK GENMASK(7, 4)
57#define DR_TY_SHIFT 20
58#define DR_TY_MASK GENMASK(22, 20)
59#define ENDLL_SHIFT 1
60#define ENDLL_MASK BIT(ENDLL_SHIFT)
61#define DLLRDY_SHIFT 0
62#define DLLRDY_MASK BIT(DLLRDY_SHIFT)
63#define PDB_SHIFT 0
64#define PDB_MASK BIT(PDB_SHIFT)
65#define CALDONE_SHIFT 1
66#define CALDONE_MASK BIT(CALDONE_SHIFT)
67#define RETRIM_SHIFT 17
68#define RETRIM_MASK BIT(RETRIM_SHIFT)
69#define SELDLYTXCLK_SHIFT 17
70#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
71#define SELDLYRXCLK_SHIFT 16
72#define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
73#define ITAPDLYSEL_SHIFT 0
74#define ITAPDLYSEL_MASK GENMASK(4, 0)
75#define ITAPDLYENA_SHIFT 8
76#define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
77#define ITAPCHGWIN_SHIFT 9
78#define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
79
80#define DRIVER_STRENGTH_50_OHM 0x0
81#define DRIVER_STRENGTH_33_OHM 0x1
82#define DRIVER_STRENGTH_66_OHM 0x2
83#define DRIVER_STRENGTH_100_OHM 0x3
84#define DRIVER_STRENGTH_40_OHM 0x4
85
86#define CLOCK_TOO_SLOW_HZ 50000000
87
88/* Command Queue Host Controller Interface Base address */
89#define SDHCI_AM654_CQE_BASE_ADDR 0x200
90
91static struct regmap_config sdhci_am654_regmap_config = {
92 .reg_bits = 32,
93 .val_bits = 32,
94 .reg_stride = 4,
95 .fast_io = true,
96};
97
98struct timing_data {
99 const char *otap_binding;
100 const char *itap_binding;
101 u32 capability;
102};
103
104static const struct timing_data td[] = {
105 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
106 "ti,itap-del-sel-legacy",
107 0},
108 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
109 "ti,itap-del-sel-mmc-hs",
110 MMC_CAP_MMC_HIGHSPEED},
111 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
112 "ti,itap-del-sel-sd-hs",
113 MMC_CAP_SD_HIGHSPEED},
114 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
115 "ti,itap-del-sel-sdr12",
116 MMC_CAP_UHS_SDR12},
117 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
118 "ti,itap-del-sel-sdr25",
119 MMC_CAP_UHS_SDR25},
120 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
121 NULL,
122 MMC_CAP_UHS_SDR50},
123 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
124 NULL,
125 MMC_CAP_UHS_SDR104},
126 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
127 NULL,
128 MMC_CAP_UHS_DDR50},
129 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
130 "ti,itap-del-sel-ddr52",
131 MMC_CAP_DDR},
132 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
133 NULL,
134 MMC_CAP2_HS200},
135 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
136 NULL,
137 MMC_CAP2_HS400},
138};
139
140struct sdhci_am654_data {
141 struct regmap *base;
142 bool legacy_otapdly;
143 int otap_del_sel[ARRAY_SIZE(td)];
144 int itap_del_sel[ARRAY_SIZE(td)];
145 int clkbuf_sel;
146 int trm_icp;
147 int drv_strength;
148 int strb_sel;
149 u32 flags;
150 u32 quirks;
151
152#define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
153};
154
155struct sdhci_am654_driver_data {
156 const struct sdhci_pltfm_data *pdata;
157 u32 flags;
158#define IOMUX_PRESENT (1 << 0)
159#define FREQSEL_2_BIT (1 << 1)
160#define STRBSEL_4_BIT (1 << 2)
161#define DLL_PRESENT (1 << 3)
162#define DLL_CALIB (1 << 4)
163};
164
165static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
166{
167 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
168 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
169 int sel50, sel100, freqsel;
170 u32 mask, val;
171 int ret;
172
173 /* Disable delay chain mode */
174 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
175 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
176
177 if (sdhci_am654->flags & FREQSEL_2_BIT) {
178 switch (clock) {
179 case 200000000:
180 sel50 = 0;
181 sel100 = 0;
182 break;
183 case 100000000:
184 sel50 = 0;
185 sel100 = 1;
186 break;
187 default:
188 sel50 = 1;
189 sel100 = 0;
190 }
191
192 /* Configure PHY DLL frequency */
193 mask = SEL50_MASK | SEL100_MASK;
194 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
195 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
196
197 } else {
198 switch (clock) {
199 case 200000000:
200 freqsel = 0x0;
201 break;
202 default:
203 freqsel = 0x4;
204 }
205
206 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
207 freqsel << FREQSEL_SHIFT);
208 }
209 /* Configure DLL TRIM */
210 mask = DLL_TRIM_ICP_MASK;
211 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
212
213 /* Configure DLL driver strength */
214 mask |= DR_TY_MASK;
215 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
216 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
217
218 /* Enable DLL */
219 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
220 0x1 << ENDLL_SHIFT);
221 /*
222 * Poll for DLL ready. Use a one second timeout.
223 * Works in all experiments done so far
224 */
225 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
226 val & DLLRDY_MASK, 1000, 1000000);
227 if (ret) {
228 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
229 return;
230 }
231}
232
233static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
234 u32 itapdly)
235{
236 /* Set ITAPCHGWIN before writing to ITAPDLY */
237 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
238 1 << ITAPCHGWIN_SHIFT);
239 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
240 itapdly << ITAPDLYSEL_SHIFT);
241 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
242}
243
244static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
245 unsigned char timing)
246{
247 u32 mask, val;
248
249 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
250
251 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
252 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
253 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
254
255 sdhci_am654_write_itapdly(sdhci_am654,
256 sdhci_am654->itap_del_sel[timing]);
257}
258
259static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
260{
261 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
262 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
263 unsigned char timing = host->mmc->ios.timing;
264 u32 otap_del_sel;
265 u32 otap_del_ena;
266 u32 mask, val;
267
268 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
269
270 sdhci_set_clock(host, clock);
271
272 /* Setup DLL Output TAP delay */
273 if (sdhci_am654->legacy_otapdly)
274 otap_del_sel = sdhci_am654->otap_del_sel[0];
275 else
276 otap_del_sel = sdhci_am654->otap_del_sel[timing];
277
278 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0;
279
280 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
281 val = (otap_del_ena << OTAPDLYENA_SHIFT) |
282 (otap_del_sel << OTAPDLYSEL_SHIFT);
283
284 /* Write to STRBSEL for HS400 speed mode */
285 if (timing == MMC_TIMING_MMC_HS400) {
286 if (sdhci_am654->flags & STRBSEL_4_BIT)
287 mask |= STRBSEL_4BIT_MASK;
288 else
289 mask |= STRBSEL_8BIT_MASK;
290
291 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
292 }
293
294 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
295
296 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ)
297 sdhci_am654_setup_dll(host, clock);
298 else
299 sdhci_am654_setup_delay_chain(sdhci_am654, timing);
300
301 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
302 sdhci_am654->clkbuf_sel);
303}
304
305static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
306 unsigned int clock)
307{
308 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
309 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
310 unsigned char timing = host->mmc->ios.timing;
311 u32 otap_del_sel;
312 u32 mask, val;
313
314 /* Setup DLL Output TAP delay */
315 if (sdhci_am654->legacy_otapdly)
316 otap_del_sel = sdhci_am654->otap_del_sel[0];
317 else
318 otap_del_sel = sdhci_am654->otap_del_sel[timing];
319
320 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
321 val = (0x1 << OTAPDLYENA_SHIFT) |
322 (otap_del_sel << OTAPDLYSEL_SHIFT);
323 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
324
325 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
326 sdhci_am654->clkbuf_sel);
327
328 sdhci_set_clock(host, clock);
329}
330
331static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
332{
333 writeb(val, host->ioaddr + reg);
334 usleep_range(1000, 10000);
335 return readb(host->ioaddr + reg);
336}
337
338#define MAX_POWER_ON_TIMEOUT 1500000 /* us */
339static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
340{
341 unsigned char timing = host->mmc->ios.timing;
342 u8 pwr;
343 int ret;
344
345 if (reg == SDHCI_HOST_CONTROL) {
346 switch (timing) {
347 /*
348 * According to the data manual, HISPD bit
349 * should not be set in these speed modes.
350 */
351 case MMC_TIMING_SD_HS:
352 case MMC_TIMING_MMC_HS:
353 case MMC_TIMING_UHS_SDR12:
354 case MMC_TIMING_UHS_SDR25:
355 val &= ~SDHCI_CTRL_HISPD;
356 }
357 }
358
359 writeb(val, host->ioaddr + reg);
360 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
361 /*
362 * Power on will not happen until the card detect debounce
363 * timer expires. Wait at least 1.5 seconds for the power on
364 * bit to be set
365 */
366 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
367 pwr & SDHCI_POWER_ON, 0,
368 MAX_POWER_ON_TIMEOUT, false, host, val,
369 reg);
370 if (ret)
371 dev_warn(mmc_dev(host->mmc), "Power on failed\n");
372 }
373}
374
375static void sdhci_am654_reset(struct sdhci_host *host, u8 mask)
376{
377 u8 ctrl;
378 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
379 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
380
381 sdhci_reset(host, mask);
382
383 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
384 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
385 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
386 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
387 }
388}
389
390static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
391{
392 struct sdhci_host *host = mmc_priv(mmc);
393 int err = sdhci_execute_tuning(mmc, opcode);
394
395 if (err)
396 return err;
397 /*
398 * Tuning data remains in the buffer after tuning.
399 * Do a command and data reset to get rid of it
400 */
401 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
402
403 return 0;
404}
405
406static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
407{
408 int cmd_error = 0;
409 int data_error = 0;
410
411 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
412 return intmask;
413
414 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
415
416 return 0;
417}
418
419#define ITAP_MAX 32
420static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
421 u32 opcode)
422{
423 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
424 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
425 int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
426 u32 itap;
427
428 /* Enable ITAPDLY */
429 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
430 1 << ITAPDLYENA_SHIFT);
431
432 for (itap = 0; itap < ITAP_MAX; itap++) {
433 sdhci_am654_write_itapdly(sdhci_am654, itap);
434
435 cur_val = !mmc_send_tuning(host->mmc, opcode, NULL);
436 if (cur_val && !prev_val)
437 pass_window = itap;
438
439 if (!cur_val)
440 fail_len++;
441
442 prev_val = cur_val;
443 }
444 /*
445 * Having determined the length of the failing window and start of
446 * the passing window calculate the length of the passing window and
447 * set the final value halfway through it considering the range as a
448 * circular buffer
449 */
450 pass_len = ITAP_MAX - fail_len;
451 itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
452 sdhci_am654_write_itapdly(sdhci_am654, itap);
453
454 return 0;
455}
456
457static struct sdhci_ops sdhci_am654_ops = {
458 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
459 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
460 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
461 .set_uhs_signaling = sdhci_set_uhs_signaling,
462 .set_bus_width = sdhci_set_bus_width,
463 .set_power = sdhci_set_power_and_bus_voltage,
464 .set_clock = sdhci_am654_set_clock,
465 .write_b = sdhci_am654_write_b,
466 .irq = sdhci_am654_cqhci_irq,
467 .reset = sdhci_reset,
468};
469
470static const struct sdhci_pltfm_data sdhci_am654_pdata = {
471 .ops = &sdhci_am654_ops,
472 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
473 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
474};
475
476static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
477 .pdata = &sdhci_am654_pdata,
478 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
479 DLL_CALIB,
480};
481
482static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
483 .pdata = &sdhci_am654_pdata,
484 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
485};
486
487static struct sdhci_ops sdhci_j721e_8bit_ops = {
488 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
489 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
490 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
491 .set_uhs_signaling = sdhci_set_uhs_signaling,
492 .set_bus_width = sdhci_set_bus_width,
493 .set_power = sdhci_set_power_and_bus_voltage,
494 .set_clock = sdhci_am654_set_clock,
495 .write_b = sdhci_am654_write_b,
496 .irq = sdhci_am654_cqhci_irq,
497 .reset = sdhci_reset,
498};
499
500static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
501 .ops = &sdhci_j721e_8bit_ops,
502 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
503 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
504};
505
506static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
507 .pdata = &sdhci_j721e_8bit_pdata,
508 .flags = DLL_PRESENT | DLL_CALIB,
509};
510
511static struct sdhci_ops sdhci_j721e_4bit_ops = {
512 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
513 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
514 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
515 .set_uhs_signaling = sdhci_set_uhs_signaling,
516 .set_bus_width = sdhci_set_bus_width,
517 .set_power = sdhci_set_power_and_bus_voltage,
518 .set_clock = sdhci_j721e_4bit_set_clock,
519 .write_b = sdhci_am654_write_b,
520 .irq = sdhci_am654_cqhci_irq,
521 .reset = sdhci_am654_reset,
522};
523
524static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
525 .ops = &sdhci_j721e_4bit_ops,
526 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
527 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
528};
529
530static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
531 .pdata = &sdhci_j721e_4bit_pdata,
532 .flags = IOMUX_PRESENT,
533};
534
535static const struct soc_device_attribute sdhci_am654_devices[] = {
536 { .family = "AM65X",
537 .revision = "SR1.0",
538 .data = &sdhci_am654_sr1_drvdata
539 },
540 {/* sentinel */}
541};
542
543static void sdhci_am654_dumpregs(struct mmc_host *mmc)
544{
545 sdhci_dumpregs(mmc_priv(mmc));
546}
547
548static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
549 .enable = sdhci_cqe_enable,
550 .disable = sdhci_cqe_disable,
551 .dumpregs = sdhci_am654_dumpregs,
552};
553
554static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
555{
556 struct cqhci_host *cq_host;
557 int ret;
558
559 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host),
560 GFP_KERNEL);
561 if (!cq_host)
562 return -ENOMEM;
563
564 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
565 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
566 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
567 cq_host->ops = &sdhci_am654_cqhci_ops;
568
569 host->mmc->caps2 |= MMC_CAP2_CQE;
570
571 ret = cqhci_init(cq_host, host->mmc, 1);
572
573 return ret;
574}
575
576static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
577 struct sdhci_am654_data *sdhci_am654)
578{
579 struct device *dev = mmc_dev(host->mmc);
580 int i;
581 int ret;
582
583 ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding,
584 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]);
585 if (ret) {
586 /*
587 * ti,otap-del-sel-legacy is mandatory, look for old binding
588 * if not found.
589 */
590 ret = device_property_read_u32(dev, "ti,otap-del-sel",
591 &sdhci_am654->otap_del_sel[0]);
592 if (ret) {
593 dev_err(dev, "Couldn't find otap-del-sel\n");
594
595 return ret;
596 }
597
598 dev_info(dev, "Using legacy binding ti,otap-del-sel\n");
599 sdhci_am654->legacy_otapdly = true;
600
601 return 0;
602 }
603
604 for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) {
605
606 ret = device_property_read_u32(dev, td[i].otap_binding,
607 &sdhci_am654->otap_del_sel[i]);
608 if (ret) {
609 dev_dbg(dev, "Couldn't find %s\n",
610 td[i].otap_binding);
611 /*
612 * Remove the corresponding capability
613 * if an otap-del-sel value is not found
614 */
615 if (i <= MMC_TIMING_MMC_DDR52)
616 host->mmc->caps &= ~td[i].capability;
617 else
618 host->mmc->caps2 &= ~td[i].capability;
619 }
620
621 if (td[i].itap_binding)
622 device_property_read_u32(dev, td[i].itap_binding,
623 &sdhci_am654->itap_del_sel[i]);
624 }
625
626 return 0;
627}
628
629static int sdhci_am654_init(struct sdhci_host *host)
630{
631 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
632 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
633 u32 ctl_cfg_2 = 0;
634 u32 mask;
635 u32 val;
636 int ret;
637
638 /* Reset OTAP to default value */
639 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
640 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
641
642 if (sdhci_am654->flags & DLL_CALIB) {
643 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
644 if (~val & CALDONE_MASK) {
645 /* Calibrate IO lines */
646 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
647 PDB_MASK, PDB_MASK);
648 ret = regmap_read_poll_timeout(sdhci_am654->base,
649 PHY_STAT1, val,
650 val & CALDONE_MASK,
651 1, 20);
652 if (ret)
653 return ret;
654 }
655 }
656
657 /* Enable pins by setting IO mux to 0 */
658 if (sdhci_am654->flags & IOMUX_PRESENT)
659 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
660 IOMUX_ENABLE_MASK, 0);
661
662 /* Set slot type based on SD or eMMC */
663 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
664 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
665
666 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
667 ctl_cfg_2);
668
669 /* Enable tuning for SDR50 */
670 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
671 TUNINGFORSDR50_MASK);
672
673 ret = sdhci_setup_host(host);
674 if (ret)
675 return ret;
676
677 ret = sdhci_am654_cqe_add_host(host);
678 if (ret)
679 goto err_cleanup_host;
680
681 ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
682 if (ret)
683 goto err_cleanup_host;
684
685 ret = __sdhci_add_host(host);
686 if (ret)
687 goto err_cleanup_host;
688
689 return 0;
690
691err_cleanup_host:
692 sdhci_cleanup_host(host);
693 return ret;
694}
695
696static int sdhci_am654_get_of_property(struct platform_device *pdev,
697 struct sdhci_am654_data *sdhci_am654)
698{
699 struct device *dev = &pdev->dev;
700 int drv_strength;
701 int ret;
702
703 if (sdhci_am654->flags & DLL_PRESENT) {
704 ret = device_property_read_u32(dev, "ti,trm-icp",
705 &sdhci_am654->trm_icp);
706 if (ret)
707 return ret;
708
709 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
710 &drv_strength);
711 if (ret)
712 return ret;
713
714 switch (drv_strength) {
715 case 50:
716 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
717 break;
718 case 33:
719 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
720 break;
721 case 66:
722 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
723 break;
724 case 100:
725 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
726 break;
727 case 40:
728 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
729 break;
730 default:
731 dev_err(dev, "Invalid driver strength\n");
732 return -EINVAL;
733 }
734 }
735
736 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
737 device_property_read_u32(dev, "ti,clkbuf-sel",
738 &sdhci_am654->clkbuf_sel);
739
740 if (device_property_read_bool(dev, "ti,fails-without-test-cd"))
741 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST;
742
743 sdhci_get_of_property(pdev);
744
745 return 0;
746}
747
748static const struct of_device_id sdhci_am654_of_match[] = {
749 {
750 .compatible = "ti,am654-sdhci-5.1",
751 .data = &sdhci_am654_drvdata,
752 },
753 {
754 .compatible = "ti,j721e-sdhci-8bit",
755 .data = &sdhci_j721e_8bit_drvdata,
756 },
757 {
758 .compatible = "ti,j721e-sdhci-4bit",
759 .data = &sdhci_j721e_4bit_drvdata,
760 },
761 {
762 .compatible = "ti,am64-sdhci-8bit",
763 .data = &sdhci_j721e_8bit_drvdata,
764 },
765 {
766 .compatible = "ti,am64-sdhci-4bit",
767 .data = &sdhci_j721e_4bit_drvdata,
768 },
769 {
770 .compatible = "ti,am62-sdhci",
771 .data = &sdhci_j721e_4bit_drvdata,
772 },
773 { /* sentinel */ }
774};
775MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
776
777static int sdhci_am654_probe(struct platform_device *pdev)
778{
779 const struct sdhci_am654_driver_data *drvdata;
780 const struct soc_device_attribute *soc;
781 struct sdhci_pltfm_host *pltfm_host;
782 struct sdhci_am654_data *sdhci_am654;
783 const struct of_device_id *match;
784 struct sdhci_host *host;
785 struct clk *clk_xin;
786 struct device *dev = &pdev->dev;
787 void __iomem *base;
788 int ret;
789
790 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
791 drvdata = match->data;
792
793 /* Update drvdata based on SoC revision */
794 soc = soc_device_match(sdhci_am654_devices);
795 if (soc && soc->data)
796 drvdata = soc->data;
797
798 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
799 if (IS_ERR(host))
800 return PTR_ERR(host);
801
802 pltfm_host = sdhci_priv(host);
803 sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
804 sdhci_am654->flags = drvdata->flags;
805
806 clk_xin = devm_clk_get(dev, "clk_xin");
807 if (IS_ERR(clk_xin)) {
808 dev_err(dev, "clk_xin clock not found.\n");
809 ret = PTR_ERR(clk_xin);
810 goto err_pltfm_free;
811 }
812
813 pltfm_host->clk = clk_xin;
814
815 /* Clocks are enabled using pm_runtime */
816 pm_runtime_enable(dev);
817 ret = pm_runtime_resume_and_get(dev);
818 if (ret)
819 goto pm_runtime_disable;
820
821 base = devm_platform_ioremap_resource(pdev, 1);
822 if (IS_ERR(base)) {
823 ret = PTR_ERR(base);
824 goto pm_runtime_put;
825 }
826
827 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
828 &sdhci_am654_regmap_config);
829 if (IS_ERR(sdhci_am654->base)) {
830 dev_err(dev, "Failed to initialize regmap\n");
831 ret = PTR_ERR(sdhci_am654->base);
832 goto pm_runtime_put;
833 }
834
835 ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
836 if (ret)
837 goto pm_runtime_put;
838
839 ret = mmc_of_parse(host->mmc);
840 if (ret) {
841 dev_err(dev, "parsing dt failed (%d)\n", ret);
842 goto pm_runtime_put;
843 }
844
845 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
846
847 ret = sdhci_am654_init(host);
848 if (ret)
849 goto pm_runtime_put;
850
851 return 0;
852
853pm_runtime_put:
854 pm_runtime_put_sync(dev);
855pm_runtime_disable:
856 pm_runtime_disable(dev);
857err_pltfm_free:
858 sdhci_pltfm_free(pdev);
859 return ret;
860}
861
862static int sdhci_am654_remove(struct platform_device *pdev)
863{
864 struct sdhci_host *host = platform_get_drvdata(pdev);
865 int ret;
866
867 sdhci_remove_host(host, true);
868 ret = pm_runtime_put_sync(&pdev->dev);
869 if (ret < 0)
870 return ret;
871
872 pm_runtime_disable(&pdev->dev);
873 sdhci_pltfm_free(pdev);
874
875 return 0;
876}
877
878static struct platform_driver sdhci_am654_driver = {
879 .driver = {
880 .name = "sdhci-am654",
881 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
882 .of_match_table = sdhci_am654_of_match,
883 },
884 .probe = sdhci_am654_probe,
885 .remove = sdhci_am654_remove,
886};
887
888module_platform_driver(sdhci_am654_driver);
889
890MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
891MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
892MODULE_LICENSE("GPL");