tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (C) 2013-2017 Broadcom
3
4#include <linux/err.h>
5#include <linux/io.h>
6#include <linux/init.h>
7#include <linux/of.h>
8#include <linux/platform_device.h>
9#include <linux/pinctrl/pinctrl.h>
10#include <linux/pinctrl/pinmux.h>
11#include <linux/pinctrl/pinconf.h>
12#include <linux/pinctrl/pinconf-generic.h>
13#include <linux/regmap.h>
14#include <linux/slab.h>
15#include "../core.h"
16#include "../pinctrl-utils.h"
17
18/* BCM281XX Pin Control Registers Definitions */
19
20/* Function Select bits are the same for all pin control registers */
21#define BCM281XX_PIN_REG_F_SEL_MASK 0x0700
22#define BCM281XX_PIN_REG_F_SEL_SHIFT 8
23
24/* Standard pin register */
25#define BCM281XX_STD_PIN_REG_DRV_STR_MASK 0x0007
26#define BCM281XX_STD_PIN_REG_DRV_STR_SHIFT 0
27#define BCM281XX_STD_PIN_REG_INPUT_DIS_MASK 0x0008
28#define BCM281XX_STD_PIN_REG_INPUT_DIS_SHIFT 3
29#define BCM281XX_STD_PIN_REG_SLEW_MASK 0x0010
30#define BCM281XX_STD_PIN_REG_SLEW_SHIFT 4
31#define BCM281XX_STD_PIN_REG_PULL_UP_MASK 0x0020
32#define BCM281XX_STD_PIN_REG_PULL_UP_SHIFT 5
33#define BCM281XX_STD_PIN_REG_PULL_DN_MASK 0x0040
34#define BCM281XX_STD_PIN_REG_PULL_DN_SHIFT 6
35#define BCM281XX_STD_PIN_REG_HYST_MASK 0x0080
36#define BCM281XX_STD_PIN_REG_HYST_SHIFT 7
37
38/* I2C pin register */
39#define BCM281XX_I2C_PIN_REG_INPUT_DIS_MASK 0x0004
40#define BCM281XX_I2C_PIN_REG_INPUT_DIS_SHIFT 2
41#define BCM281XX_I2C_PIN_REG_SLEW_MASK 0x0008
42#define BCM281XX_I2C_PIN_REG_SLEW_SHIFT 3
43#define BCM281XX_I2C_PIN_REG_PULL_UP_STR_MASK 0x0070
44#define BCM281XX_I2C_PIN_REG_PULL_UP_STR_SHIFT 4
45
46/* HDMI pin register */
47#define BCM281XX_HDMI_PIN_REG_INPUT_DIS_MASK 0x0008
48#define BCM281XX_HDMI_PIN_REG_INPUT_DIS_SHIFT 3
49#define BCM281XX_HDMI_PIN_REG_MODE_MASK 0x0010
50#define BCM281XX_HDMI_PIN_REG_MODE_SHIFT 4
51
52/*
53 * bcm281xx_pin_type - types of pin register
54 */
55enum bcm281xx_pin_type {
56 BCM281XX_PIN_TYPE_UNKNOWN = 0,
57 BCM281XX_PIN_TYPE_STD,
58 BCM281XX_PIN_TYPE_I2C,
59 BCM281XX_PIN_TYPE_HDMI,
60};
61
62static enum bcm281xx_pin_type std_pin = BCM281XX_PIN_TYPE_STD;
63static enum bcm281xx_pin_type i2c_pin = BCM281XX_PIN_TYPE_I2C;
64static enum bcm281xx_pin_type hdmi_pin = BCM281XX_PIN_TYPE_HDMI;
65
66/*
67 * bcm281xx_pin_function- define pin function
68 */
69struct bcm281xx_pin_function {
70 const char *name;
71 const char * const *groups;
72 const unsigned ngroups;
73};
74
75/*
76 * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data
77 * @reg_base - base of pinctrl registers
78 */
79struct bcm281xx_pinctrl_data {
80 void __iomem *reg_base;
81
82 /* List of all pins */
83 const struct pinctrl_pin_desc *pins;
84 const unsigned npins;
85
86 const struct bcm281xx_pin_function *functions;
87 const unsigned nfunctions;
88
89 struct regmap *regmap;
90};
91
92/*
93 * Pin number definition. The order here must be the same as defined in the
94 * PADCTRLREG block in the RDB.
95 */
96#define BCM281XX_PIN_ADCSYNC 0
97#define BCM281XX_PIN_BAT_RM 1
98#define BCM281XX_PIN_BSC1_SCL 2
99#define BCM281XX_PIN_BSC1_SDA 3
100#define BCM281XX_PIN_BSC2_SCL 4
101#define BCM281XX_PIN_BSC2_SDA 5
102#define BCM281XX_PIN_CLASSGPWR 6
103#define BCM281XX_PIN_CLK_CX8 7
104#define BCM281XX_PIN_CLKOUT_0 8
105#define BCM281XX_PIN_CLKOUT_1 9
106#define BCM281XX_PIN_CLKOUT_2 10
107#define BCM281XX_PIN_CLKOUT_3 11
108#define BCM281XX_PIN_CLKREQ_IN_0 12
109#define BCM281XX_PIN_CLKREQ_IN_1 13
110#define BCM281XX_PIN_CWS_SYS_REQ1 14
111#define BCM281XX_PIN_CWS_SYS_REQ2 15
112#define BCM281XX_PIN_CWS_SYS_REQ3 16
113#define BCM281XX_PIN_DIGMIC1_CLK 17
114#define BCM281XX_PIN_DIGMIC1_DQ 18
115#define BCM281XX_PIN_DIGMIC2_CLK 19
116#define BCM281XX_PIN_DIGMIC2_DQ 20
117#define BCM281XX_PIN_GPEN13 21
118#define BCM281XX_PIN_GPEN14 22
119#define BCM281XX_PIN_GPEN15 23
120#define BCM281XX_PIN_GPIO00 24
121#define BCM281XX_PIN_GPIO01 25
122#define BCM281XX_PIN_GPIO02 26
123#define BCM281XX_PIN_GPIO03 27
124#define BCM281XX_PIN_GPIO04 28
125#define BCM281XX_PIN_GPIO05 29
126#define BCM281XX_PIN_GPIO06 30
127#define BCM281XX_PIN_GPIO07 31
128#define BCM281XX_PIN_GPIO08 32
129#define BCM281XX_PIN_GPIO09 33
130#define BCM281XX_PIN_GPIO10 34
131#define BCM281XX_PIN_GPIO11 35
132#define BCM281XX_PIN_GPIO12 36
133#define BCM281XX_PIN_GPIO13 37
134#define BCM281XX_PIN_GPIO14 38
135#define BCM281XX_PIN_GPS_PABLANK 39
136#define BCM281XX_PIN_GPS_TMARK 40
137#define BCM281XX_PIN_HDMI_SCL 41
138#define BCM281XX_PIN_HDMI_SDA 42
139#define BCM281XX_PIN_IC_DM 43
140#define BCM281XX_PIN_IC_DP 44
141#define BCM281XX_PIN_KP_COL_IP_0 45
142#define BCM281XX_PIN_KP_COL_IP_1 46
143#define BCM281XX_PIN_KP_COL_IP_2 47
144#define BCM281XX_PIN_KP_COL_IP_3 48
145#define BCM281XX_PIN_KP_ROW_OP_0 49
146#define BCM281XX_PIN_KP_ROW_OP_1 50
147#define BCM281XX_PIN_KP_ROW_OP_2 51
148#define BCM281XX_PIN_KP_ROW_OP_3 52
149#define BCM281XX_PIN_LCD_B_0 53
150#define BCM281XX_PIN_LCD_B_1 54
151#define BCM281XX_PIN_LCD_B_2 55
152#define BCM281XX_PIN_LCD_B_3 56
153#define BCM281XX_PIN_LCD_B_4 57
154#define BCM281XX_PIN_LCD_B_5 58
155#define BCM281XX_PIN_LCD_B_6 59
156#define BCM281XX_PIN_LCD_B_7 60
157#define BCM281XX_PIN_LCD_G_0 61
158#define BCM281XX_PIN_LCD_G_1 62
159#define BCM281XX_PIN_LCD_G_2 63
160#define BCM281XX_PIN_LCD_G_3 64
161#define BCM281XX_PIN_LCD_G_4 65
162#define BCM281XX_PIN_LCD_G_5 66
163#define BCM281XX_PIN_LCD_G_6 67
164#define BCM281XX_PIN_LCD_G_7 68
165#define BCM281XX_PIN_LCD_HSYNC 69
166#define BCM281XX_PIN_LCD_OE 70
167#define BCM281XX_PIN_LCD_PCLK 71
168#define BCM281XX_PIN_LCD_R_0 72
169#define BCM281XX_PIN_LCD_R_1 73
170#define BCM281XX_PIN_LCD_R_2 74
171#define BCM281XX_PIN_LCD_R_3 75
172#define BCM281XX_PIN_LCD_R_4 76
173#define BCM281XX_PIN_LCD_R_5 77
174#define BCM281XX_PIN_LCD_R_6 78
175#define BCM281XX_PIN_LCD_R_7 79
176#define BCM281XX_PIN_LCD_VSYNC 80
177#define BCM281XX_PIN_MDMGPIO0 81
178#define BCM281XX_PIN_MDMGPIO1 82
179#define BCM281XX_PIN_MDMGPIO2 83
180#define BCM281XX_PIN_MDMGPIO3 84
181#define BCM281XX_PIN_MDMGPIO4 85
182#define BCM281XX_PIN_MDMGPIO5 86
183#define BCM281XX_PIN_MDMGPIO6 87
184#define BCM281XX_PIN_MDMGPIO7 88
185#define BCM281XX_PIN_MDMGPIO8 89
186#define BCM281XX_PIN_MPHI_DATA_0 90
187#define BCM281XX_PIN_MPHI_DATA_1 91
188#define BCM281XX_PIN_MPHI_DATA_2 92
189#define BCM281XX_PIN_MPHI_DATA_3 93
190#define BCM281XX_PIN_MPHI_DATA_4 94
191#define BCM281XX_PIN_MPHI_DATA_5 95
192#define BCM281XX_PIN_MPHI_DATA_6 96
193#define BCM281XX_PIN_MPHI_DATA_7 97
194#define BCM281XX_PIN_MPHI_DATA_8 98
195#define BCM281XX_PIN_MPHI_DATA_9 99
196#define BCM281XX_PIN_MPHI_DATA_10 100
197#define BCM281XX_PIN_MPHI_DATA_11 101
198#define BCM281XX_PIN_MPHI_DATA_12 102
199#define BCM281XX_PIN_MPHI_DATA_13 103
200#define BCM281XX_PIN_MPHI_DATA_14 104
201#define BCM281XX_PIN_MPHI_DATA_15 105
202#define BCM281XX_PIN_MPHI_HA0 106
203#define BCM281XX_PIN_MPHI_HAT0 107
204#define BCM281XX_PIN_MPHI_HAT1 108
205#define BCM281XX_PIN_MPHI_HCE0_N 109
206#define BCM281XX_PIN_MPHI_HCE1_N 110
207#define BCM281XX_PIN_MPHI_HRD_N 111
208#define BCM281XX_PIN_MPHI_HWR_N 112
209#define BCM281XX_PIN_MPHI_RUN0 113
210#define BCM281XX_PIN_MPHI_RUN1 114
211#define BCM281XX_PIN_MTX_SCAN_CLK 115
212#define BCM281XX_PIN_MTX_SCAN_DATA 116
213#define BCM281XX_PIN_NAND_AD_0 117
214#define BCM281XX_PIN_NAND_AD_1 118
215#define BCM281XX_PIN_NAND_AD_2 119
216#define BCM281XX_PIN_NAND_AD_3 120
217#define BCM281XX_PIN_NAND_AD_4 121
218#define BCM281XX_PIN_NAND_AD_5 122
219#define BCM281XX_PIN_NAND_AD_6 123
220#define BCM281XX_PIN_NAND_AD_7 124
221#define BCM281XX_PIN_NAND_ALE 125
222#define BCM281XX_PIN_NAND_CEN_0 126
223#define BCM281XX_PIN_NAND_CEN_1 127
224#define BCM281XX_PIN_NAND_CLE 128
225#define BCM281XX_PIN_NAND_OEN 129
226#define BCM281XX_PIN_NAND_RDY_0 130
227#define BCM281XX_PIN_NAND_RDY_1 131
228#define BCM281XX_PIN_NAND_WEN 132
229#define BCM281XX_PIN_NAND_WP 133
230#define BCM281XX_PIN_PC1 134
231#define BCM281XX_PIN_PC2 135
232#define BCM281XX_PIN_PMU_INT 136
233#define BCM281XX_PIN_PMU_SCL 137
234#define BCM281XX_PIN_PMU_SDA 138
235#define BCM281XX_PIN_RFST2G_MTSLOTEN3G 139
236#define BCM281XX_PIN_RGMII_0_RX_CTL 140
237#define BCM281XX_PIN_RGMII_0_RXC 141
238#define BCM281XX_PIN_RGMII_0_RXD_0 142
239#define BCM281XX_PIN_RGMII_0_RXD_1 143
240#define BCM281XX_PIN_RGMII_0_RXD_2 144
241#define BCM281XX_PIN_RGMII_0_RXD_3 145
242#define BCM281XX_PIN_RGMII_0_TX_CTL 146
243#define BCM281XX_PIN_RGMII_0_TXC 147
244#define BCM281XX_PIN_RGMII_0_TXD_0 148
245#define BCM281XX_PIN_RGMII_0_TXD_1 149
246#define BCM281XX_PIN_RGMII_0_TXD_2 150
247#define BCM281XX_PIN_RGMII_0_TXD_3 151
248#define BCM281XX_PIN_RGMII_1_RX_CTL 152
249#define BCM281XX_PIN_RGMII_1_RXC 153
250#define BCM281XX_PIN_RGMII_1_RXD_0 154
251#define BCM281XX_PIN_RGMII_1_RXD_1 155
252#define BCM281XX_PIN_RGMII_1_RXD_2 156
253#define BCM281XX_PIN_RGMII_1_RXD_3 157
254#define BCM281XX_PIN_RGMII_1_TX_CTL 158
255#define BCM281XX_PIN_RGMII_1_TXC 159
256#define BCM281XX_PIN_RGMII_1_TXD_0 160
257#define BCM281XX_PIN_RGMII_1_TXD_1 161
258#define BCM281XX_PIN_RGMII_1_TXD_2 162
259#define BCM281XX_PIN_RGMII_1_TXD_3 163
260#define BCM281XX_PIN_RGMII_GPIO_0 164
261#define BCM281XX_PIN_RGMII_GPIO_1 165
262#define BCM281XX_PIN_RGMII_GPIO_2 166
263#define BCM281XX_PIN_RGMII_GPIO_3 167
264#define BCM281XX_PIN_RTXDATA2G_TXDATA3G1 168
265#define BCM281XX_PIN_RTXEN2G_TXDATA3G2 169
266#define BCM281XX_PIN_RXDATA3G0 170
267#define BCM281XX_PIN_RXDATA3G1 171
268#define BCM281XX_PIN_RXDATA3G2 172
269#define BCM281XX_PIN_SDIO1_CLK 173
270#define BCM281XX_PIN_SDIO1_CMD 174
271#define BCM281XX_PIN_SDIO1_DATA_0 175
272#define BCM281XX_PIN_SDIO1_DATA_1 176
273#define BCM281XX_PIN_SDIO1_DATA_2 177
274#define BCM281XX_PIN_SDIO1_DATA_3 178
275#define BCM281XX_PIN_SDIO4_CLK 179
276#define BCM281XX_PIN_SDIO4_CMD 180
277#define BCM281XX_PIN_SDIO4_DATA_0 181
278#define BCM281XX_PIN_SDIO4_DATA_1 182
279#define BCM281XX_PIN_SDIO4_DATA_2 183
280#define BCM281XX_PIN_SDIO4_DATA_3 184
281#define BCM281XX_PIN_SIM_CLK 185
282#define BCM281XX_PIN_SIM_DATA 186
283#define BCM281XX_PIN_SIM_DET 187
284#define BCM281XX_PIN_SIM_RESETN 188
285#define BCM281XX_PIN_SIM2_CLK 189
286#define BCM281XX_PIN_SIM2_DATA 190
287#define BCM281XX_PIN_SIM2_DET 191
288#define BCM281XX_PIN_SIM2_RESETN 192
289#define BCM281XX_PIN_SRI_C 193
290#define BCM281XX_PIN_SRI_D 194
291#define BCM281XX_PIN_SRI_E 195
292#define BCM281XX_PIN_SSP_EXTCLK 196
293#define BCM281XX_PIN_SSP0_CLK 197
294#define BCM281XX_PIN_SSP0_FS 198
295#define BCM281XX_PIN_SSP0_RXD 199
296#define BCM281XX_PIN_SSP0_TXD 200
297#define BCM281XX_PIN_SSP2_CLK 201
298#define BCM281XX_PIN_SSP2_FS_0 202
299#define BCM281XX_PIN_SSP2_FS_1 203
300#define BCM281XX_PIN_SSP2_FS_2 204
301#define BCM281XX_PIN_SSP2_FS_3 205
302#define BCM281XX_PIN_SSP2_RXD_0 206
303#define BCM281XX_PIN_SSP2_RXD_1 207
304#define BCM281XX_PIN_SSP2_TXD_0 208
305#define BCM281XX_PIN_SSP2_TXD_1 209
306#define BCM281XX_PIN_SSP3_CLK 210
307#define BCM281XX_PIN_SSP3_FS 211
308#define BCM281XX_PIN_SSP3_RXD 212
309#define BCM281XX_PIN_SSP3_TXD 213
310#define BCM281XX_PIN_SSP4_CLK 214
311#define BCM281XX_PIN_SSP4_FS 215
312#define BCM281XX_PIN_SSP4_RXD 216
313#define BCM281XX_PIN_SSP4_TXD 217
314#define BCM281XX_PIN_SSP5_CLK 218
315#define BCM281XX_PIN_SSP5_FS 219
316#define BCM281XX_PIN_SSP5_RXD 220
317#define BCM281XX_PIN_SSP5_TXD 221
318#define BCM281XX_PIN_SSP6_CLK 222
319#define BCM281XX_PIN_SSP6_FS 223
320#define BCM281XX_PIN_SSP6_RXD 224
321#define BCM281XX_PIN_SSP6_TXD 225
322#define BCM281XX_PIN_STAT_1 226
323#define BCM281XX_PIN_STAT_2 227
324#define BCM281XX_PIN_SYSCLKEN 228
325#define BCM281XX_PIN_TRACECLK 229
326#define BCM281XX_PIN_TRACEDT00 230
327#define BCM281XX_PIN_TRACEDT01 231
328#define BCM281XX_PIN_TRACEDT02 232
329#define BCM281XX_PIN_TRACEDT03 233
330#define BCM281XX_PIN_TRACEDT04 234
331#define BCM281XX_PIN_TRACEDT05 235
332#define BCM281XX_PIN_TRACEDT06 236
333#define BCM281XX_PIN_TRACEDT07 237
334#define BCM281XX_PIN_TRACEDT08 238
335#define BCM281XX_PIN_TRACEDT09 239
336#define BCM281XX_PIN_TRACEDT10 240
337#define BCM281XX_PIN_TRACEDT11 241
338#define BCM281XX_PIN_TRACEDT12 242
339#define BCM281XX_PIN_TRACEDT13 243
340#define BCM281XX_PIN_TRACEDT14 244
341#define BCM281XX_PIN_TRACEDT15 245
342#define BCM281XX_PIN_TXDATA3G0 246
343#define BCM281XX_PIN_TXPWRIND 247
344#define BCM281XX_PIN_UARTB1_UCTS 248
345#define BCM281XX_PIN_UARTB1_URTS 249
346#define BCM281XX_PIN_UARTB1_URXD 250
347#define BCM281XX_PIN_UARTB1_UTXD 251
348#define BCM281XX_PIN_UARTB2_URXD 252
349#define BCM281XX_PIN_UARTB2_UTXD 253
350#define BCM281XX_PIN_UARTB3_UCTS 254
351#define BCM281XX_PIN_UARTB3_URTS 255
352#define BCM281XX_PIN_UARTB3_URXD 256
353#define BCM281XX_PIN_UARTB3_UTXD 257
354#define BCM281XX_PIN_UARTB4_UCTS 258
355#define BCM281XX_PIN_UARTB4_URTS 259
356#define BCM281XX_PIN_UARTB4_URXD 260
357#define BCM281XX_PIN_UARTB4_UTXD 261
358#define BCM281XX_PIN_VC_CAM1_SCL 262
359#define BCM281XX_PIN_VC_CAM1_SDA 263
360#define BCM281XX_PIN_VC_CAM2_SCL 264
361#define BCM281XX_PIN_VC_CAM2_SDA 265
362#define BCM281XX_PIN_VC_CAM3_SCL 266
363#define BCM281XX_PIN_VC_CAM3_SDA 267
364
365#define BCM281XX_PIN_DESC(a, b, c) \
366 { .number = a, .name = b, .drv_data = &c##_pin }
367
368/*
369 * Pin description definition. The order here must be the same as defined in
370 * the PADCTRLREG block in the RDB, since the pin number is used as an index
371 * into this array.
372 */
373static const struct pinctrl_pin_desc bcm281xx_pinctrl_pins[] = {
374 BCM281XX_PIN_DESC(BCM281XX_PIN_ADCSYNC, "adcsync", std),
375 BCM281XX_PIN_DESC(BCM281XX_PIN_BAT_RM, "bat_rm", std),
376 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SCL, "bsc1_scl", i2c),
377 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SDA, "bsc1_sda", i2c),
378 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SCL, "bsc2_scl", i2c),
379 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SDA, "bsc2_sda", i2c),
380 BCM281XX_PIN_DESC(BCM281XX_PIN_CLASSGPWR, "classgpwr", std),
381 BCM281XX_PIN_DESC(BCM281XX_PIN_CLK_CX8, "clk_cx8", std),
382 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_0, "clkout_0", std),
383 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_1, "clkout_1", std),
384 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_2, "clkout_2", std),
385 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_3, "clkout_3", std),
386 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_0, "clkreq_in_0", std),
387 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_1, "clkreq_in_1", std),
388 BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ1, "cws_sys_req1", std),
389 BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ2, "cws_sys_req2", std),
390 BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ3, "cws_sys_req3", std),
391 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_CLK, "digmic1_clk", std),
392 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_DQ, "digmic1_dq", std),
393 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_CLK, "digmic2_clk", std),
394 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_DQ, "digmic2_dq", std),
395 BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN13, "gpen13", std),
396 BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN14, "gpen14", std),
397 BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN15, "gpen15", std),
398 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO00, "gpio00", std),
399 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO01, "gpio01", std),
400 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO02, "gpio02", std),
401 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO03, "gpio03", std),
402 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO04, "gpio04", std),
403 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO05, "gpio05", std),
404 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO06, "gpio06", std),
405 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO07, "gpio07", std),
406 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO08, "gpio08", std),
407 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO09, "gpio09", std),
408 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO10, "gpio10", std),
409 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO11, "gpio11", std),
410 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO12, "gpio12", std),
411 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO13, "gpio13", std),
412 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO14, "gpio14", std),
413 BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_PABLANK, "gps_pablank", std),
414 BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_TMARK, "gps_tmark", std),
415 BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SCL, "hdmi_scl", hdmi),
416 BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SDA, "hdmi_sda", hdmi),
417 BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DM, "ic_dm", std),
418 BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DP, "ic_dp", std),
419 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_0, "kp_col_ip_0", std),
420 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_1, "kp_col_ip_1", std),
421 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_2, "kp_col_ip_2", std),
422 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_3, "kp_col_ip_3", std),
423 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_0, "kp_row_op_0", std),
424 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_1, "kp_row_op_1", std),
425 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_2, "kp_row_op_2", std),
426 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_3, "kp_row_op_3", std),
427 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_0, "lcd_b_0", std),
428 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_1, "lcd_b_1", std),
429 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_2, "lcd_b_2", std),
430 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_3, "lcd_b_3", std),
431 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_4, "lcd_b_4", std),
432 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_5, "lcd_b_5", std),
433 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_6, "lcd_b_6", std),
434 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_7, "lcd_b_7", std),
435 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_0, "lcd_g_0", std),
436 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_1, "lcd_g_1", std),
437 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_2, "lcd_g_2", std),
438 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_3, "lcd_g_3", std),
439 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_4, "lcd_g_4", std),
440 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_5, "lcd_g_5", std),
441 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_6, "lcd_g_6", std),
442 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_7, "lcd_g_7", std),
443 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_HSYNC, "lcd_hsync", std),
444 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_OE, "lcd_oe", std),
445 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_PCLK, "lcd_pclk", std),
446 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_0, "lcd_r_0", std),
447 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_1, "lcd_r_1", std),
448 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_2, "lcd_r_2", std),
449 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_3, "lcd_r_3", std),
450 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_4, "lcd_r_4", std),
451 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_5, "lcd_r_5", std),
452 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_6, "lcd_r_6", std),
453 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_7, "lcd_r_7", std),
454 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_VSYNC, "lcd_vsync", std),
455 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO0, "mdmgpio0", std),
456 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO1, "mdmgpio1", std),
457 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO2, "mdmgpio2", std),
458 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO3, "mdmgpio3", std),
459 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO4, "mdmgpio4", std),
460 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO5, "mdmgpio5", std),
461 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO6, "mdmgpio6", std),
462 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO7, "mdmgpio7", std),
463 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO8, "mdmgpio8", std),
464 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_0, "mphi_data_0", std),
465 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_1, "mphi_data_1", std),
466 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_2, "mphi_data_2", std),
467 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_3, "mphi_data_3", std),
468 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_4, "mphi_data_4", std),
469 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_5, "mphi_data_5", std),
470 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_6, "mphi_data_6", std),
471 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_7, "mphi_data_7", std),
472 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_8, "mphi_data_8", std),
473 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_9, "mphi_data_9", std),
474 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_10, "mphi_data_10", std),
475 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_11, "mphi_data_11", std),
476 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_12, "mphi_data_12", std),
477 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_13, "mphi_data_13", std),
478 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_14, "mphi_data_14", std),
479 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_15, "mphi_data_15", std),
480 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HA0, "mphi_ha0", std),
481 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT0, "mphi_hat0", std),
482 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT1, "mphi_hat1", std),
483 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE0_N, "mphi_hce0_n", std),
484 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE1_N, "mphi_hce1_n", std),
485 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HRD_N, "mphi_hrd_n", std),
486 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HWR_N, "mphi_hwr_n", std),
487 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN0, "mphi_run0", std),
488 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN1, "mphi_run1", std),
489 BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std),
490 BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_DATA, "mtx_scan_data", std),
491 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_0, "nand_ad_0", std),
492 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_1, "nand_ad_1", std),
493 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_2, "nand_ad_2", std),
494 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_3, "nand_ad_3", std),
495 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_4, "nand_ad_4", std),
496 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_5, "nand_ad_5", std),
497 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_6, "nand_ad_6", std),
498 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_7, "nand_ad_7", std),
499 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_ALE, "nand_ale", std),
500 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_0, "nand_cen_0", std),
501 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_1, "nand_cen_1", std),
502 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CLE, "nand_cle", std),
503 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_OEN, "nand_oen", std),
504 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_0, "nand_rdy_0", std),
505 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_1, "nand_rdy_1", std),
506 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WEN, "nand_wen", std),
507 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WP, "nand_wp", std),
508 BCM281XX_PIN_DESC(BCM281XX_PIN_PC1, "pc1", std),
509 BCM281XX_PIN_DESC(BCM281XX_PIN_PC2, "pc2", std),
510 BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_INT, "pmu_int", std),
511 BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SCL, "pmu_scl", i2c),
512 BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SDA, "pmu_sda", i2c),
513 BCM281XX_PIN_DESC(BCM281XX_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g",
514 std),
515 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std),
516 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXC, "rgmii_0_rxc", std),
517 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std),
518 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std),
519 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std),
520 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std),
521 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std),
522 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXC, "rgmii_0_txc", std),
523 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std),
524 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std),
525 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std),
526 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std),
527 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std),
528 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXC, "rgmii_1_rxc", std),
529 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std),
530 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std),
531 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std),
532 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std),
533 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std),
534 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXC, "rgmii_1_txc", std),
535 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std),
536 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std),
537 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std),
538 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std),
539 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std),
540 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std),
541 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std),
542 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std),
543 BCM281XX_PIN_DESC(BCM281XX_PIN_RTXDATA2G_TXDATA3G1,
544 "rtxdata2g_txdata3g1", std),
545 BCM281XX_PIN_DESC(BCM281XX_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2",
546 std),
547 BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G0, "rxdata3g0", std),
548 BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G1, "rxdata3g1", std),
549 BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G2, "rxdata3g2", std),
550 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CLK, "sdio1_clk", std),
551 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CMD, "sdio1_cmd", std),
552 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_0, "sdio1_data_0", std),
553 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_1, "sdio1_data_1", std),
554 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_2, "sdio1_data_2", std),
555 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_3, "sdio1_data_3", std),
556 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CLK, "sdio4_clk", std),
557 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CMD, "sdio4_cmd", std),
558 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_0, "sdio4_data_0", std),
559 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_1, "sdio4_data_1", std),
560 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_2, "sdio4_data_2", std),
561 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_3, "sdio4_data_3", std),
562 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_CLK, "sim_clk", std),
563 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DATA, "sim_data", std),
564 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DET, "sim_det", std),
565 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_RESETN, "sim_resetn", std),
566 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_CLK, "sim2_clk", std),
567 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DATA, "sim2_data", std),
568 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DET, "sim2_det", std),
569 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_RESETN, "sim2_resetn", std),
570 BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_C, "sri_c", std),
571 BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_D, "sri_d", std),
572 BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_E, "sri_e", std),
573 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP_EXTCLK, "ssp_extclk", std),
574 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_CLK, "ssp0_clk", std),
575 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_FS, "ssp0_fs", std),
576 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_RXD, "ssp0_rxd", std),
577 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_TXD, "ssp0_txd", std),
578 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_CLK, "ssp2_clk", std),
579 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_0, "ssp2_fs_0", std),
580 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_1, "ssp2_fs_1", std),
581 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_2, "ssp2_fs_2", std),
582 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_3, "ssp2_fs_3", std),
583 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_0, "ssp2_rxd_0", std),
584 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_1, "ssp2_rxd_1", std),
585 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_0, "ssp2_txd_0", std),
586 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_1, "ssp2_txd_1", std),
587 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_CLK, "ssp3_clk", std),
588 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_FS, "ssp3_fs", std),
589 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_RXD, "ssp3_rxd", std),
590 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_TXD, "ssp3_txd", std),
591 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_CLK, "ssp4_clk", std),
592 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_FS, "ssp4_fs", std),
593 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_RXD, "ssp4_rxd", std),
594 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_TXD, "ssp4_txd", std),
595 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_CLK, "ssp5_clk", std),
596 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_FS, "ssp5_fs", std),
597 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_RXD, "ssp5_rxd", std),
598 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_TXD, "ssp5_txd", std),
599 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_CLK, "ssp6_clk", std),
600 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_FS, "ssp6_fs", std),
601 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_RXD, "ssp6_rxd", std),
602 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_TXD, "ssp6_txd", std),
603 BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_1, "stat_1", std),
604 BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_2, "stat_2", std),
605 BCM281XX_PIN_DESC(BCM281XX_PIN_SYSCLKEN, "sysclken", std),
606 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACECLK, "traceclk", std),
607 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT00, "tracedt00", std),
608 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT01, "tracedt01", std),
609 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT02, "tracedt02", std),
610 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT03, "tracedt03", std),
611 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT04, "tracedt04", std),
612 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT05, "tracedt05", std),
613 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT06, "tracedt06", std),
614 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT07, "tracedt07", std),
615 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT08, "tracedt08", std),
616 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT09, "tracedt09", std),
617 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT10, "tracedt10", std),
618 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT11, "tracedt11", std),
619 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT12, "tracedt12", std),
620 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT13, "tracedt13", std),
621 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT14, "tracedt14", std),
622 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT15, "tracedt15", std),
623 BCM281XX_PIN_DESC(BCM281XX_PIN_TXDATA3G0, "txdata3g0", std),
624 BCM281XX_PIN_DESC(BCM281XX_PIN_TXPWRIND, "txpwrind", std),
625 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UCTS, "uartb1_ucts", std),
626 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URTS, "uartb1_urts", std),
627 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URXD, "uartb1_urxd", std),
628 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UTXD, "uartb1_utxd", std),
629 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_URXD, "uartb2_urxd", std),
630 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_UTXD, "uartb2_utxd", std),
631 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UCTS, "uartb3_ucts", std),
632 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URTS, "uartb3_urts", std),
633 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URXD, "uartb3_urxd", std),
634 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UTXD, "uartb3_utxd", std),
635 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UCTS, "uartb4_ucts", std),
636 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URTS, "uartb4_urts", std),
637 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URXD, "uartb4_urxd", std),
638 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UTXD, "uartb4_utxd", std),
639 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c),
640 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c),
641 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c),
642 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c),
643 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c),
644 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c),
645};
646
647static const char * const bcm281xx_alt_groups[] = {
648 "adcsync",
649 "bat_rm",
650 "bsc1_scl",
651 "bsc1_sda",
652 "bsc2_scl",
653 "bsc2_sda",
654 "classgpwr",
655 "clk_cx8",
656 "clkout_0",
657 "clkout_1",
658 "clkout_2",
659 "clkout_3",
660 "clkreq_in_0",
661 "clkreq_in_1",
662 "cws_sys_req1",
663 "cws_sys_req2",
664 "cws_sys_req3",
665 "digmic1_clk",
666 "digmic1_dq",
667 "digmic2_clk",
668 "digmic2_dq",
669 "gpen13",
670 "gpen14",
671 "gpen15",
672 "gpio00",
673 "gpio01",
674 "gpio02",
675 "gpio03",
676 "gpio04",
677 "gpio05",
678 "gpio06",
679 "gpio07",
680 "gpio08",
681 "gpio09",
682 "gpio10",
683 "gpio11",
684 "gpio12",
685 "gpio13",
686 "gpio14",
687 "gps_pablank",
688 "gps_tmark",
689 "hdmi_scl",
690 "hdmi_sda",
691 "ic_dm",
692 "ic_dp",
693 "kp_col_ip_0",
694 "kp_col_ip_1",
695 "kp_col_ip_2",
696 "kp_col_ip_3",
697 "kp_row_op_0",
698 "kp_row_op_1",
699 "kp_row_op_2",
700 "kp_row_op_3",
701 "lcd_b_0",
702 "lcd_b_1",
703 "lcd_b_2",
704 "lcd_b_3",
705 "lcd_b_4",
706 "lcd_b_5",
707 "lcd_b_6",
708 "lcd_b_7",
709 "lcd_g_0",
710 "lcd_g_1",
711 "lcd_g_2",
712 "lcd_g_3",
713 "lcd_g_4",
714 "lcd_g_5",
715 "lcd_g_6",
716 "lcd_g_7",
717 "lcd_hsync",
718 "lcd_oe",
719 "lcd_pclk",
720 "lcd_r_0",
721 "lcd_r_1",
722 "lcd_r_2",
723 "lcd_r_3",
724 "lcd_r_4",
725 "lcd_r_5",
726 "lcd_r_6",
727 "lcd_r_7",
728 "lcd_vsync",
729 "mdmgpio0",
730 "mdmgpio1",
731 "mdmgpio2",
732 "mdmgpio3",
733 "mdmgpio4",
734 "mdmgpio5",
735 "mdmgpio6",
736 "mdmgpio7",
737 "mdmgpio8",
738 "mphi_data_0",
739 "mphi_data_1",
740 "mphi_data_2",
741 "mphi_data_3",
742 "mphi_data_4",
743 "mphi_data_5",
744 "mphi_data_6",
745 "mphi_data_7",
746 "mphi_data_8",
747 "mphi_data_9",
748 "mphi_data_10",
749 "mphi_data_11",
750 "mphi_data_12",
751 "mphi_data_13",
752 "mphi_data_14",
753 "mphi_data_15",
754 "mphi_ha0",
755 "mphi_hat0",
756 "mphi_hat1",
757 "mphi_hce0_n",
758 "mphi_hce1_n",
759 "mphi_hrd_n",
760 "mphi_hwr_n",
761 "mphi_run0",
762 "mphi_run1",
763 "mtx_scan_clk",
764 "mtx_scan_data",
765 "nand_ad_0",
766 "nand_ad_1",
767 "nand_ad_2",
768 "nand_ad_3",
769 "nand_ad_4",
770 "nand_ad_5",
771 "nand_ad_6",
772 "nand_ad_7",
773 "nand_ale",
774 "nand_cen_0",
775 "nand_cen_1",
776 "nand_cle",
777 "nand_oen",
778 "nand_rdy_0",
779 "nand_rdy_1",
780 "nand_wen",
781 "nand_wp",
782 "pc1",
783 "pc2",
784 "pmu_int",
785 "pmu_scl",
786 "pmu_sda",
787 "rfst2g_mtsloten3g",
788 "rgmii_0_rx_ctl",
789 "rgmii_0_rxc",
790 "rgmii_0_rxd_0",
791 "rgmii_0_rxd_1",
792 "rgmii_0_rxd_2",
793 "rgmii_0_rxd_3",
794 "rgmii_0_tx_ctl",
795 "rgmii_0_txc",
796 "rgmii_0_txd_0",
797 "rgmii_0_txd_1",
798 "rgmii_0_txd_2",
799 "rgmii_0_txd_3",
800 "rgmii_1_rx_ctl",
801 "rgmii_1_rxc",
802 "rgmii_1_rxd_0",
803 "rgmii_1_rxd_1",
804 "rgmii_1_rxd_2",
805 "rgmii_1_rxd_3",
806 "rgmii_1_tx_ctl",
807 "rgmii_1_txc",
808 "rgmii_1_txd_0",
809 "rgmii_1_txd_1",
810 "rgmii_1_txd_2",
811 "rgmii_1_txd_3",
812 "rgmii_gpio_0",
813 "rgmii_gpio_1",
814 "rgmii_gpio_2",
815 "rgmii_gpio_3",
816 "rtxdata2g_txdata3g1",
817 "rtxen2g_txdata3g2",
818 "rxdata3g0",
819 "rxdata3g1",
820 "rxdata3g2",
821 "sdio1_clk",
822 "sdio1_cmd",
823 "sdio1_data_0",
824 "sdio1_data_1",
825 "sdio1_data_2",
826 "sdio1_data_3",
827 "sdio4_clk",
828 "sdio4_cmd",
829 "sdio4_data_0",
830 "sdio4_data_1",
831 "sdio4_data_2",
832 "sdio4_data_3",
833 "sim_clk",
834 "sim_data",
835 "sim_det",
836 "sim_resetn",
837 "sim2_clk",
838 "sim2_data",
839 "sim2_det",
840 "sim2_resetn",
841 "sri_c",
842 "sri_d",
843 "sri_e",
844 "ssp_extclk",
845 "ssp0_clk",
846 "ssp0_fs",
847 "ssp0_rxd",
848 "ssp0_txd",
849 "ssp2_clk",
850 "ssp2_fs_0",
851 "ssp2_fs_1",
852 "ssp2_fs_2",
853 "ssp2_fs_3",
854 "ssp2_rxd_0",
855 "ssp2_rxd_1",
856 "ssp2_txd_0",
857 "ssp2_txd_1",
858 "ssp3_clk",
859 "ssp3_fs",
860 "ssp3_rxd",
861 "ssp3_txd",
862 "ssp4_clk",
863 "ssp4_fs",
864 "ssp4_rxd",
865 "ssp4_txd",
866 "ssp5_clk",
867 "ssp5_fs",
868 "ssp5_rxd",
869 "ssp5_txd",
870 "ssp6_clk",
871 "ssp6_fs",
872 "ssp6_rxd",
873 "ssp6_txd",
874 "stat_1",
875 "stat_2",
876 "sysclken",
877 "traceclk",
878 "tracedt00",
879 "tracedt01",
880 "tracedt02",
881 "tracedt03",
882 "tracedt04",
883 "tracedt05",
884 "tracedt06",
885 "tracedt07",
886 "tracedt08",
887 "tracedt09",
888 "tracedt10",
889 "tracedt11",
890 "tracedt12",
891 "tracedt13",
892 "tracedt14",
893 "tracedt15",
894 "txdata3g0",
895 "txpwrind",
896 "uartb1_ucts",
897 "uartb1_urts",
898 "uartb1_urxd",
899 "uartb1_utxd",
900 "uartb2_urxd",
901 "uartb2_utxd",
902 "uartb3_ucts",
903 "uartb3_urts",
904 "uartb3_urxd",
905 "uartb3_utxd",
906 "uartb4_ucts",
907 "uartb4_urts",
908 "uartb4_urxd",
909 "uartb4_utxd",
910 "vc_cam1_scl",
911 "vc_cam1_sda",
912 "vc_cam2_scl",
913 "vc_cam2_sda",
914 "vc_cam3_scl",
915 "vc_cam3_sda",
916};
917
918/* Every pin can implement all ALT1-ALT4 functions */
919#define BCM281XX_PIN_FUNCTION(fcn_name) \
920{ \
921 .name = #fcn_name, \
922 .groups = bcm281xx_alt_groups, \
923 .ngroups = ARRAY_SIZE(bcm281xx_alt_groups), \
924}
925
926static const struct bcm281xx_pin_function bcm281xx_functions[] = {
927 BCM281XX_PIN_FUNCTION(alt1),
928 BCM281XX_PIN_FUNCTION(alt2),
929 BCM281XX_PIN_FUNCTION(alt3),
930 BCM281XX_PIN_FUNCTION(alt4),
931};
932
933static struct bcm281xx_pinctrl_data bcm281xx_pinctrl = {
934 .pins = bcm281xx_pinctrl_pins,
935 .npins = ARRAY_SIZE(bcm281xx_pinctrl_pins),
936 .functions = bcm281xx_functions,
937 .nfunctions = ARRAY_SIZE(bcm281xx_functions),
938};
939
940static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev,
941 unsigned pin)
942{
943 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
944
945 if (pin >= pdata->npins)
946 return BCM281XX_PIN_TYPE_UNKNOWN;
947
948 return *(enum bcm281xx_pin_type *)(pdata->pins[pin].drv_data);
949}
950
951#define BCM281XX_PIN_SHIFT(type, param) \
952 (BCM281XX_ ## type ## _PIN_REG_ ## param ## _SHIFT)
953
954#define BCM281XX_PIN_MASK(type, param) \
955 (BCM281XX_ ## type ## _PIN_REG_ ## param ## _MASK)
956
957/*
958 * This helper function is used to build up the value and mask used to write to
959 * a pin register, but does not actually write to the register.
960 */
961static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask,
962 u32 param_val, u32 param_shift,
963 u32 param_mask)
964{
965 *reg_val &= ~param_mask;
966 *reg_val |= (param_val << param_shift) & param_mask;
967 *reg_mask |= param_mask;
968}
969
970static const struct regmap_config bcm281xx_pinctrl_regmap_config = {
971 .reg_bits = 32,
972 .reg_stride = 4,
973 .val_bits = 32,
974 .max_register = BCM281XX_PIN_VC_CAM3_SDA,
975};
976
977static int bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
978{
979 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
980
981 return pdata->npins;
982}
983
984static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
985 unsigned group)
986{
987 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
988
989 return pdata->pins[group].name;
990}
991
992static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
993 unsigned group,
994 const unsigned **pins,
995 unsigned *num_pins)
996{
997 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
998
999 *pins = &pdata->pins[group].number;
1000 *num_pins = 1;
1001
1002 return 0;
1003}
1004
1005static void bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
1006 struct seq_file *s,
1007 unsigned offset)
1008{
1009 seq_printf(s, " %s", dev_name(pctldev->dev));
1010}
1011
1012static const struct pinctrl_ops bcm281xx_pinctrl_ops = {
1013 .get_groups_count = bcm281xx_pinctrl_get_groups_count,
1014 .get_group_name = bcm281xx_pinctrl_get_group_name,
1015 .get_group_pins = bcm281xx_pinctrl_get_group_pins,
1016 .pin_dbg_show = bcm281xx_pinctrl_pin_dbg_show,
1017 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1018 .dt_free_map = pinctrl_utils_free_map,
1019};
1020
1021static int bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev)
1022{
1023 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1024
1025 return pdata->nfunctions;
1026}
1027
1028static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev,
1029 unsigned function)
1030{
1031 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1032
1033 return pdata->functions[function].name;
1034}
1035
1036static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev,
1037 unsigned function,
1038 const char * const **groups,
1039 unsigned * const num_groups)
1040{
1041 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1042
1043 *groups = pdata->functions[function].groups;
1044 *num_groups = pdata->functions[function].ngroups;
1045
1046 return 0;
1047}
1048
1049static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev,
1050 unsigned function,
1051 unsigned group)
1052{
1053 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1054 const struct bcm281xx_pin_function *f = &pdata->functions[function];
1055 u32 offset = 4 * pdata->pins[group].number;
1056 int rc = 0;
1057
1058 dev_dbg(pctldev->dev,
1059 "%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n",
1060 __func__, f->name, function, pdata->pins[group].name,
1061 pdata->pins[group].number, offset);
1062
1063 rc = regmap_update_bits(pdata->regmap, offset,
1064 BCM281XX_PIN_REG_F_SEL_MASK,
1065 function << BCM281XX_PIN_REG_F_SEL_SHIFT);
1066 if (rc)
1067 dev_err(pctldev->dev,
1068 "Error updating register for pin %s (%d).\n",
1069 pdata->pins[group].name, pdata->pins[group].number);
1070
1071 return rc;
1072}
1073
1074static const struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = {
1075 .get_functions_count = bcm281xx_pinctrl_get_fcns_count,
1076 .get_function_name = bcm281xx_pinctrl_get_fcn_name,
1077 .get_function_groups = bcm281xx_pinctrl_get_fcn_groups,
1078 .set_mux = bcm281xx_pinmux_set,
1079};
1080
1081static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,
1082 unsigned pin,
1083 unsigned long *config)
1084{
1085 return -ENOTSUPP;
1086}
1087
1088
1089/* Goes through the configs and update register val/mask */
1090static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev,
1091 unsigned pin,
1092 unsigned long *configs,
1093 unsigned num_configs,
1094 u32 *val,
1095 u32 *mask)
1096{
1097 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1098 int i;
1099 enum pin_config_param param;
1100 u32 arg;
1101
1102 for (i = 0; i < num_configs; i++) {
1103 param = pinconf_to_config_param(configs[i]);
1104 arg = pinconf_to_config_argument(configs[i]);
1105
1106 switch (param) {
1107 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1108 arg = (arg >= 1 ? 1 : 0);
1109 bcm281xx_pin_update(val, mask, arg,
1110 BCM281XX_PIN_SHIFT(STD, HYST),
1111 BCM281XX_PIN_MASK(STD, HYST));
1112 break;
1113 /*
1114 * The pin bias can only be one of pull-up, pull-down, or
1115 * disable. The user does not need to specify a value for the
1116 * property, and the default value from pinconf-generic is
1117 * ignored.
1118 */
1119 case PIN_CONFIG_BIAS_DISABLE:
1120 bcm281xx_pin_update(val, mask, 0,
1121 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1122 BCM281XX_PIN_MASK(STD, PULL_UP));
1123 bcm281xx_pin_update(val, mask, 0,
1124 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1125 BCM281XX_PIN_MASK(STD, PULL_DN));
1126 break;
1127
1128 case PIN_CONFIG_BIAS_PULL_UP:
1129 bcm281xx_pin_update(val, mask, 1,
1130 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1131 BCM281XX_PIN_MASK(STD, PULL_UP));
1132 bcm281xx_pin_update(val, mask, 0,
1133 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1134 BCM281XX_PIN_MASK(STD, PULL_DN));
1135 break;
1136
1137 case PIN_CONFIG_BIAS_PULL_DOWN:
1138 bcm281xx_pin_update(val, mask, 0,
1139 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1140 BCM281XX_PIN_MASK(STD, PULL_UP));
1141 bcm281xx_pin_update(val, mask, 1,
1142 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1143 BCM281XX_PIN_MASK(STD, PULL_DN));
1144 break;
1145
1146 case PIN_CONFIG_SLEW_RATE:
1147 arg = (arg >= 1 ? 1 : 0);
1148 bcm281xx_pin_update(val, mask, arg,
1149 BCM281XX_PIN_SHIFT(STD, SLEW),
1150 BCM281XX_PIN_MASK(STD, SLEW));
1151 break;
1152
1153 case PIN_CONFIG_INPUT_ENABLE:
1154 /* inversed since register is for input _disable_ */
1155 arg = (arg >= 1 ? 0 : 1);
1156 bcm281xx_pin_update(val, mask, arg,
1157 BCM281XX_PIN_SHIFT(STD, INPUT_DIS),
1158 BCM281XX_PIN_MASK(STD, INPUT_DIS));
1159 break;
1160
1161 case PIN_CONFIG_DRIVE_STRENGTH:
1162 /* Valid range is 2-16 mA, even numbers only */
1163 if ((arg < 2) || (arg > 16) || (arg % 2)) {
1164 dev_err(pctldev->dev,
1165 "Invalid Drive Strength value (%d) for "
1166 "pin %s (%d). Valid values are "
1167 "(2..16) mA, even numbers only.\n",
1168 arg, pdata->pins[pin].name, pin);
1169 return -EINVAL;
1170 }
1171 bcm281xx_pin_update(val, mask, (arg/2)-1,
1172 BCM281XX_PIN_SHIFT(STD, DRV_STR),
1173 BCM281XX_PIN_MASK(STD, DRV_STR));
1174 break;
1175
1176 default:
1177 dev_err(pctldev->dev,
1178 "Unrecognized pin config %d for pin %s (%d).\n",
1179 param, pdata->pins[pin].name, pin);
1180 return -EINVAL;
1181
1182 } /* switch config */
1183 } /* for each config */
1184
1185 return 0;
1186}
1187
1188/*
1189 * The pull-up strength for an I2C pin is represented by bits 4-6 in the
1190 * register with the following mapping:
1191 * 0b000: No pull-up
1192 * 0b001: 1200 Ohm
1193 * 0b010: 1800 Ohm
1194 * 0b011: 720 Ohm
1195 * 0b100: 2700 Ohm
1196 * 0b101: 831 Ohm
1197 * 0b110: 1080 Ohm
1198 * 0b111: 568 Ohm
1199 * This array maps pull-up strength in Ohms to register values (1+index).
1200 */
1201static const u16 bcm281xx_pullup_map[] = {
1202 1200, 1800, 720, 2700, 831, 1080, 568
1203};
1204
1205/* Goes through the configs and update register val/mask */
1206static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev,
1207 unsigned pin,
1208 unsigned long *configs,
1209 unsigned num_configs,
1210 u32 *val,
1211 u32 *mask)
1212{
1213 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1214 int i, j;
1215 enum pin_config_param param;
1216 u32 arg;
1217
1218 for (i = 0; i < num_configs; i++) {
1219 param = pinconf_to_config_param(configs[i]);
1220 arg = pinconf_to_config_argument(configs[i]);
1221
1222 switch (param) {
1223 case PIN_CONFIG_BIAS_PULL_UP:
1224 for (j = 0; j < ARRAY_SIZE(bcm281xx_pullup_map); j++)
1225 if (bcm281xx_pullup_map[j] == arg)
1226 break;
1227
1228 if (j == ARRAY_SIZE(bcm281xx_pullup_map)) {
1229 dev_err(pctldev->dev,
1230 "Invalid pull-up value (%d) for pin %s "
1231 "(%d). Valid values are 568, 720, 831, "
1232 "1080, 1200, 1800, 2700 Ohms.\n",
1233 arg, pdata->pins[pin].name, pin);
1234 return -EINVAL;
1235 }
1236
1237 bcm281xx_pin_update(val, mask, j+1,
1238 BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
1239 BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
1240 break;
1241
1242 case PIN_CONFIG_BIAS_DISABLE:
1243 bcm281xx_pin_update(val, mask, 0,
1244 BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
1245 BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
1246 break;
1247
1248 case PIN_CONFIG_SLEW_RATE:
1249 arg = (arg >= 1 ? 1 : 0);
1250 bcm281xx_pin_update(val, mask, arg,
1251 BCM281XX_PIN_SHIFT(I2C, SLEW),
1252 BCM281XX_PIN_MASK(I2C, SLEW));
1253 break;
1254
1255 case PIN_CONFIG_INPUT_ENABLE:
1256 /* inversed since register is for input _disable_ */
1257 arg = (arg >= 1 ? 0 : 1);
1258 bcm281xx_pin_update(val, mask, arg,
1259 BCM281XX_PIN_SHIFT(I2C, INPUT_DIS),
1260 BCM281XX_PIN_MASK(I2C, INPUT_DIS));
1261 break;
1262
1263 default:
1264 dev_err(pctldev->dev,
1265 "Unrecognized pin config %d for pin %s (%d).\n",
1266 param, pdata->pins[pin].name, pin);
1267 return -EINVAL;
1268
1269 } /* switch config */
1270 } /* for each config */
1271
1272 return 0;
1273}
1274
1275/* Goes through the configs and update register val/mask */
1276static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev,
1277 unsigned pin,
1278 unsigned long *configs,
1279 unsigned num_configs,
1280 u32 *val,
1281 u32 *mask)
1282{
1283 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1284 int i;
1285 enum pin_config_param param;
1286 u32 arg;
1287
1288 for (i = 0; i < num_configs; i++) {
1289 param = pinconf_to_config_param(configs[i]);
1290 arg = pinconf_to_config_argument(configs[i]);
1291
1292 switch (param) {
1293 case PIN_CONFIG_SLEW_RATE:
1294 arg = (arg >= 1 ? 1 : 0);
1295 bcm281xx_pin_update(val, mask, arg,
1296 BCM281XX_PIN_SHIFT(HDMI, MODE),
1297 BCM281XX_PIN_MASK(HDMI, MODE));
1298 break;
1299
1300 case PIN_CONFIG_INPUT_ENABLE:
1301 /* inversed since register is for input _disable_ */
1302 arg = (arg >= 1 ? 0 : 1);
1303 bcm281xx_pin_update(val, mask, arg,
1304 BCM281XX_PIN_SHIFT(HDMI, INPUT_DIS),
1305 BCM281XX_PIN_MASK(HDMI, INPUT_DIS));
1306 break;
1307
1308 default:
1309 dev_err(pctldev->dev,
1310 "Unrecognized pin config %d for pin %s (%d).\n",
1311 param, pdata->pins[pin].name, pin);
1312 return -EINVAL;
1313
1314 } /* switch config */
1315 } /* for each config */
1316
1317 return 0;
1318}
1319
1320static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev,
1321 unsigned pin,
1322 unsigned long *configs,
1323 unsigned num_configs)
1324{
1325 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1326 enum bcm281xx_pin_type pin_type;
1327 u32 offset = 4 * pin;
1328 u32 cfg_val, cfg_mask;
1329 int rc;
1330
1331 cfg_val = 0;
1332 cfg_mask = 0;
1333 pin_type = pin_type_get(pctldev, pin);
1334
1335 /* Different pins have different configuration options */
1336 switch (pin_type) {
1337 case BCM281XX_PIN_TYPE_STD:
1338 rc = bcm281xx_std_pin_update(pctldev, pin, configs,
1339 num_configs, &cfg_val, &cfg_mask);
1340 break;
1341
1342 case BCM281XX_PIN_TYPE_I2C:
1343 rc = bcm281xx_i2c_pin_update(pctldev, pin, configs,
1344 num_configs, &cfg_val, &cfg_mask);
1345 break;
1346
1347 case BCM281XX_PIN_TYPE_HDMI:
1348 rc = bcm281xx_hdmi_pin_update(pctldev, pin, configs,
1349 num_configs, &cfg_val, &cfg_mask);
1350 break;
1351
1352 default:
1353 dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n",
1354 pdata->pins[pin].name, pin);
1355 return -EINVAL;
1356
1357 } /* switch pin type */
1358
1359 if (rc)
1360 return rc;
1361
1362 dev_dbg(pctldev->dev,
1363 "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n",
1364 __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask);
1365
1366 rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val);
1367 if (rc) {
1368 dev_err(pctldev->dev,
1369 "Error updating register for pin %s (%d).\n",
1370 pdata->pins[pin].name, pin);
1371 return rc;
1372 }
1373
1374 return 0;
1375}
1376
1377static const struct pinconf_ops bcm281xx_pinctrl_pinconf_ops = {
1378 .pin_config_get = bcm281xx_pinctrl_pin_config_get,
1379 .pin_config_set = bcm281xx_pinctrl_pin_config_set,
1380};
1381
1382static struct pinctrl_desc bcm281xx_pinctrl_desc = {
1383 /* name, pins, npins members initialized in probe function */
1384 .pctlops = &bcm281xx_pinctrl_ops,
1385 .pmxops = &bcm281xx_pinctrl_pinmux_ops,
1386 .confops = &bcm281xx_pinctrl_pinconf_ops,
1387 .owner = THIS_MODULE,
1388};
1389
1390static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
1391{
1392 struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl;
1393 struct pinctrl_dev *pctl;
1394
1395 /* So far We can assume there is only 1 bank of registers */
1396 pdata->reg_base = devm_platform_ioremap_resource(pdev, 0);
1397 if (IS_ERR(pdata->reg_base)) {
1398 dev_err(&pdev->dev, "Failed to ioremap MEM resource\n");
1399 return PTR_ERR(pdata->reg_base);
1400 }
1401
1402 /* Initialize the dynamic part of pinctrl_desc */
1403 pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base,
1404 &bcm281xx_pinctrl_regmap_config);
1405 if (IS_ERR(pdata->regmap)) {
1406 dev_err(&pdev->dev, "Regmap MMIO init failed.\n");
1407 return -ENODEV;
1408 }
1409
1410 bcm281xx_pinctrl_desc.name = dev_name(&pdev->dev);
1411 bcm281xx_pinctrl_desc.pins = bcm281xx_pinctrl.pins;
1412 bcm281xx_pinctrl_desc.npins = bcm281xx_pinctrl.npins;
1413
1414 pctl = devm_pinctrl_register(&pdev->dev, &bcm281xx_pinctrl_desc, pdata);
1415 if (IS_ERR(pctl)) {
1416 dev_err(&pdev->dev, "Failed to register pinctrl\n");
1417 return PTR_ERR(pctl);
1418 }
1419
1420 platform_set_drvdata(pdev, pdata);
1421
1422 return 0;
1423}
1424
1425static const struct of_device_id bcm281xx_pinctrl_of_match[] = {
1426 { .compatible = "brcm,bcm11351-pinctrl", },
1427 { },
1428};
1429
1430static struct platform_driver bcm281xx_pinctrl_driver = {
1431 .driver = {
1432 .name = "bcm281xx-pinctrl",
1433 .of_match_table = bcm281xx_pinctrl_of_match,
1434 },
1435};
1436builtin_platform_driver_probe(bcm281xx_pinctrl_driver, bcm281xx_pinctrl_probe);