tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/* NXP TJA1100 BroadRReach PHY driver
3 *
4 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
5 */
6#include <linux/delay.h>
7#include <linux/ethtool.h>
8#include <linux/ethtool_netlink.h>
9#include <linux/kernel.h>
10#include <linux/mdio.h>
11#include <linux/mii.h>
12#include <linux/module.h>
13#include <linux/phy.h>
14#include <linux/hwmon.h>
15#include <linux/bitfield.h>
16#include <linux/of_mdio.h>
17#include <linux/of_irq.h>
18
19#define PHY_ID_MASK 0xfffffff0
20#define PHY_ID_TJA1100 0x0180dc40
21#define PHY_ID_TJA1101 0x0180dd00
22#define PHY_ID_TJA1102 0x0180dc80
23
24#define MII_ECTRL 17
25#define MII_ECTRL_LINK_CONTROL BIT(15)
26#define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
27#define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
28#define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11)
29#define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
30#define MII_ECTRL_CABLE_TEST BIT(5)
31#define MII_ECTRL_CONFIG_EN BIT(2)
32#define MII_ECTRL_WAKE_REQUEST BIT(0)
33
34#define MII_CFG1 18
35#define MII_CFG1_MASTER_SLAVE BIT(15)
36#define MII_CFG1_AUTO_OP BIT(14)
37#define MII_CFG1_SLEEP_CONFIRM BIT(6)
38#define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
39#define MII_CFG1_LED_MODE_LINKUP 0
40#define MII_CFG1_LED_ENABLE BIT(3)
41
42#define MII_CFG2 19
43#define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
44#define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
45
46#define MII_INTSRC 21
47#define MII_INTSRC_LINK_FAIL BIT(10)
48#define MII_INTSRC_LINK_UP BIT(9)
49#define MII_INTSRC_MASK (MII_INTSRC_LINK_FAIL | MII_INTSRC_LINK_UP)
50#define MII_INTSRC_UV_ERR BIT(3)
51#define MII_INTSRC_TEMP_ERR BIT(1)
52
53#define MII_INTEN 22
54#define MII_INTEN_LINK_FAIL BIT(10)
55#define MII_INTEN_LINK_UP BIT(9)
56#define MII_INTEN_UV_ERR BIT(3)
57#define MII_INTEN_TEMP_ERR BIT(1)
58
59#define MII_COMMSTAT 23
60#define MII_COMMSTAT_LINK_UP BIT(15)
61#define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
62#define MII_COMMSTAT_SQI_MAX 7
63
64#define MII_GENSTAT 24
65#define MII_GENSTAT_PLL_LOCKED BIT(14)
66
67#define MII_EXTSTAT 25
68#define MII_EXTSTAT_SHORT_DETECT BIT(8)
69#define MII_EXTSTAT_OPEN_DETECT BIT(7)
70#define MII_EXTSTAT_POLARITY_DETECT BIT(6)
71
72#define MII_COMMCFG 27
73#define MII_COMMCFG_AUTO_OP BIT(15)
74
75struct tja11xx_priv {
76 char *hwmon_name;
77 struct device *hwmon_dev;
78 struct phy_device *phydev;
79 struct work_struct phy_register_work;
80};
81
82struct tja11xx_phy_stats {
83 const char *string;
84 u8 reg;
85 u8 off;
86 u16 mask;
87};
88
89static struct tja11xx_phy_stats tja11xx_hw_stats[] = {
90 { "phy_symbol_error_count", 20, 0, GENMASK(15, 0) },
91 { "phy_polarity_detect", 25, 6, BIT(6) },
92 { "phy_open_detect", 25, 7, BIT(7) },
93 { "phy_short_detect", 25, 8, BIT(8) },
94 { "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) },
95 { "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) },
96};
97
98static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set)
99{
100 int val;
101
102 return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set,
103 150, 30000, false);
104}
105
106static int phy_modify_check(struct phy_device *phydev, u8 reg,
107 u16 mask, u16 set)
108{
109 int ret;
110
111 ret = phy_modify(phydev, reg, mask, set);
112 if (ret)
113 return ret;
114
115 return tja11xx_check(phydev, reg, mask, set);
116}
117
118static int tja11xx_enable_reg_write(struct phy_device *phydev)
119{
120 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);
121}
122
123static int tja11xx_enable_link_control(struct phy_device *phydev)
124{
125 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
126}
127
128static int tja11xx_disable_link_control(struct phy_device *phydev)
129{
130 return phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
131}
132
133static int tja11xx_wakeup(struct phy_device *phydev)
134{
135 int ret;
136
137 ret = phy_read(phydev, MII_ECTRL);
138 if (ret < 0)
139 return ret;
140
141 switch (ret & MII_ECTRL_POWER_MODE_MASK) {
142 case MII_ECTRL_POWER_MODE_NO_CHANGE:
143 break;
144 case MII_ECTRL_POWER_MODE_NORMAL:
145 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
146 if (ret)
147 return ret;
148
149 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
150 if (ret)
151 return ret;
152 break;
153 case MII_ECTRL_POWER_MODE_STANDBY:
154 ret = phy_modify_check(phydev, MII_ECTRL,
155 MII_ECTRL_POWER_MODE_MASK,
156 MII_ECTRL_POWER_MODE_STANDBY);
157 if (ret)
158 return ret;
159
160 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK,
161 MII_ECTRL_POWER_MODE_NORMAL);
162 if (ret)
163 return ret;
164
165 ret = phy_modify_check(phydev, MII_GENSTAT,
166 MII_GENSTAT_PLL_LOCKED,
167 MII_GENSTAT_PLL_LOCKED);
168 if (ret)
169 return ret;
170
171 return tja11xx_enable_link_control(phydev);
172 default:
173 break;
174 }
175
176 return 0;
177}
178
179static int tja11xx_soft_reset(struct phy_device *phydev)
180{
181 int ret;
182
183 ret = tja11xx_enable_reg_write(phydev);
184 if (ret)
185 return ret;
186
187 return genphy_soft_reset(phydev);
188}
189
190static int tja11xx_config_aneg_cable_test(struct phy_device *phydev)
191{
192 bool finished = false;
193 int ret;
194
195 if (phydev->link)
196 return 0;
197
198 if (!phydev->drv->cable_test_start ||
199 !phydev->drv->cable_test_get_status)
200 return 0;
201
202 ret = ethnl_cable_test_alloc(phydev, ETHTOOL_MSG_CABLE_TEST_NTF);
203 if (ret)
204 return ret;
205
206 ret = phydev->drv->cable_test_start(phydev);
207 if (ret)
208 return ret;
209
210 /* According to the documentation this test takes 100 usec */
211 usleep_range(100, 200);
212
213 ret = phydev->drv->cable_test_get_status(phydev, &finished);
214 if (ret)
215 return ret;
216
217 if (finished)
218 ethnl_cable_test_finished(phydev);
219
220 return 0;
221}
222
223static int tja11xx_config_aneg(struct phy_device *phydev)
224{
225 int ret, changed = 0;
226 u16 ctl = 0;
227
228 switch (phydev->master_slave_set) {
229 case MASTER_SLAVE_CFG_MASTER_FORCE:
230 ctl |= MII_CFG1_MASTER_SLAVE;
231 break;
232 case MASTER_SLAVE_CFG_SLAVE_FORCE:
233 break;
234 case MASTER_SLAVE_CFG_UNKNOWN:
235 case MASTER_SLAVE_CFG_UNSUPPORTED:
236 goto do_test;
237 default:
238 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
239 return -ENOTSUPP;
240 }
241
242 changed = phy_modify_changed(phydev, MII_CFG1, MII_CFG1_MASTER_SLAVE, ctl);
243 if (changed < 0)
244 return changed;
245
246do_test:
247 ret = tja11xx_config_aneg_cable_test(phydev);
248 if (ret)
249 return ret;
250
251 return __genphy_config_aneg(phydev, changed);
252}
253
254static int tja11xx_config_init(struct phy_device *phydev)
255{
256 int ret;
257
258 ret = tja11xx_enable_reg_write(phydev);
259 if (ret)
260 return ret;
261
262 phydev->autoneg = AUTONEG_DISABLE;
263 phydev->speed = SPEED_100;
264 phydev->duplex = DUPLEX_FULL;
265
266 switch (phydev->phy_id & PHY_ID_MASK) {
267 case PHY_ID_TJA1100:
268 ret = phy_modify(phydev, MII_CFG1,
269 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
270 MII_CFG1_LED_ENABLE,
271 MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP |
272 MII_CFG1_LED_ENABLE);
273 if (ret)
274 return ret;
275 break;
276 case PHY_ID_TJA1101:
277 case PHY_ID_TJA1102:
278 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
279 if (ret)
280 return ret;
281 break;
282 default:
283 return -EINVAL;
284 }
285
286 ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
287 if (ret)
288 return ret;
289
290 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
291 MII_CFG2_SLEEP_REQUEST_TO_16MS);
292 if (ret)
293 return ret;
294
295 ret = tja11xx_wakeup(phydev);
296 if (ret < 0)
297 return ret;
298
299 /* ACK interrupts by reading the status register */
300 ret = phy_read(phydev, MII_INTSRC);
301 if (ret < 0)
302 return ret;
303
304 return 0;
305}
306
307static int tja11xx_read_status(struct phy_device *phydev)
308{
309 int ret;
310
311 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
312 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
313
314 ret = genphy_update_link(phydev);
315 if (ret)
316 return ret;
317
318 ret = phy_read(phydev, MII_CFG1);
319 if (ret < 0)
320 return ret;
321
322 if (ret & MII_CFG1_MASTER_SLAVE)
323 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
324 else
325 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
326
327 if (phydev->link) {
328 ret = phy_read(phydev, MII_COMMSTAT);
329 if (ret < 0)
330 return ret;
331
332 if (!(ret & MII_COMMSTAT_LINK_UP))
333 phydev->link = 0;
334 }
335
336 return 0;
337}
338
339static int tja11xx_get_sqi(struct phy_device *phydev)
340{
341 int ret;
342
343 ret = phy_read(phydev, MII_COMMSTAT);
344 if (ret < 0)
345 return ret;
346
347 return FIELD_GET(MII_COMMSTAT_SQI_STATE, ret);
348}
349
350static int tja11xx_get_sqi_max(struct phy_device *phydev)
351{
352 return MII_COMMSTAT_SQI_MAX;
353}
354
355static int tja11xx_get_sset_count(struct phy_device *phydev)
356{
357 return ARRAY_SIZE(tja11xx_hw_stats);
358}
359
360static void tja11xx_get_strings(struct phy_device *phydev, u8 *data)
361{
362 int i;
363
364 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
365 strncpy(data + i * ETH_GSTRING_LEN,
366 tja11xx_hw_stats[i].string, ETH_GSTRING_LEN);
367 }
368}
369
370static void tja11xx_get_stats(struct phy_device *phydev,
371 struct ethtool_stats *stats, u64 *data)
372{
373 int i, ret;
374
375 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
376 ret = phy_read(phydev, tja11xx_hw_stats[i].reg);
377 if (ret < 0)
378 data[i] = U64_MAX;
379 else {
380 data[i] = ret & tja11xx_hw_stats[i].mask;
381 data[i] >>= tja11xx_hw_stats[i].off;
382 }
383 }
384}
385
386static int tja11xx_hwmon_read(struct device *dev,
387 enum hwmon_sensor_types type,
388 u32 attr, int channel, long *value)
389{
390 struct phy_device *phydev = dev_get_drvdata(dev);
391 int ret;
392
393 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) {
394 ret = phy_read(phydev, MII_INTSRC);
395 if (ret < 0)
396 return ret;
397
398 *value = !!(ret & MII_INTSRC_TEMP_ERR);
399 return 0;
400 }
401
402 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) {
403 ret = phy_read(phydev, MII_INTSRC);
404 if (ret < 0)
405 return ret;
406
407 *value = !!(ret & MII_INTSRC_UV_ERR);
408 return 0;
409 }
410
411 return -EOPNOTSUPP;
412}
413
414static umode_t tja11xx_hwmon_is_visible(const void *data,
415 enum hwmon_sensor_types type,
416 u32 attr, int channel)
417{
418 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm)
419 return 0444;
420
421 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm)
422 return 0444;
423
424 return 0;
425}
426
427static const struct hwmon_channel_info *tja11xx_hwmon_info[] = {
428 HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM),
429 HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM),
430 NULL
431};
432
433static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = {
434 .is_visible = tja11xx_hwmon_is_visible,
435 .read = tja11xx_hwmon_read,
436};
437
438static const struct hwmon_chip_info tja11xx_hwmon_chip_info = {
439 .ops = &tja11xx_hwmon_hwmon_ops,
440 .info = tja11xx_hwmon_info,
441};
442
443static int tja11xx_hwmon_register(struct phy_device *phydev,
444 struct tja11xx_priv *priv)
445{
446 struct device *dev = &phydev->mdio.dev;
447
448 priv->hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev));
449 if (IS_ERR(priv->hwmon_name))
450 return PTR_ERR(priv->hwmon_name);
451
452 priv->hwmon_dev =
453 devm_hwmon_device_register_with_info(dev, priv->hwmon_name,
454 phydev,
455 &tja11xx_hwmon_chip_info,
456 NULL);
457
458 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
459}
460
461static int tja11xx_probe(struct phy_device *phydev)
462{
463 struct device *dev = &phydev->mdio.dev;
464 struct tja11xx_priv *priv;
465
466 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
467 if (!priv)
468 return -ENOMEM;
469
470 priv->phydev = phydev;
471
472 return tja11xx_hwmon_register(phydev, priv);
473}
474
475static void tja1102_p1_register(struct work_struct *work)
476{
477 struct tja11xx_priv *priv = container_of(work, struct tja11xx_priv,
478 phy_register_work);
479 struct phy_device *phydev_phy0 = priv->phydev;
480 struct mii_bus *bus = phydev_phy0->mdio.bus;
481 struct device *dev = &phydev_phy0->mdio.dev;
482 struct device_node *np = dev->of_node;
483 struct device_node *child;
484 int ret;
485
486 for_each_available_child_of_node(np, child) {
487 struct phy_device *phy;
488 int addr;
489
490 addr = of_mdio_parse_addr(dev, child);
491 if (addr < 0) {
492 dev_err(dev, "Can't parse addr\n");
493 continue;
494 } else if (addr != phydev_phy0->mdio.addr + 1) {
495 /* Currently we care only about double PHY chip TJA1102.
496 * If some day NXP will decide to bring chips with more
497 * PHYs, this logic should be reworked.
498 */
499 dev_err(dev, "Unexpected address. Should be: %i\n",
500 phydev_phy0->mdio.addr + 1);
501 continue;
502 }
503
504 if (mdiobus_is_registered_device(bus, addr)) {
505 dev_err(dev, "device is already registered\n");
506 continue;
507 }
508
509 /* Real PHY ID of Port 1 is 0 */
510 phy = phy_device_create(bus, addr, PHY_ID_TJA1102, false, NULL);
511 if (IS_ERR(phy)) {
512 dev_err(dev, "Can't create PHY device for Port 1: %i\n",
513 addr);
514 continue;
515 }
516
517 /* Overwrite parent device. phy_device_create() set parent to
518 * the mii_bus->dev, which is not correct in case.
519 */
520 phy->mdio.dev.parent = dev;
521
522 ret = of_mdiobus_phy_device_register(bus, phy, child, addr);
523 if (ret) {
524 /* All resources needed for Port 1 should be already
525 * available for Port 0. Both ports use the same
526 * interrupt line, so -EPROBE_DEFER would make no sense
527 * here.
528 */
529 dev_err(dev, "Can't register Port 1. Unexpected error: %i\n",
530 ret);
531 phy_device_free(phy);
532 }
533 }
534}
535
536static int tja1102_p0_probe(struct phy_device *phydev)
537{
538 struct device *dev = &phydev->mdio.dev;
539 struct tja11xx_priv *priv;
540 int ret;
541
542 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
543 if (!priv)
544 return -ENOMEM;
545
546 priv->phydev = phydev;
547 INIT_WORK(&priv->phy_register_work, tja1102_p1_register);
548
549 ret = tja11xx_hwmon_register(phydev, priv);
550 if (ret)
551 return ret;
552
553 schedule_work(&priv->phy_register_work);
554
555 return 0;
556}
557
558static int tja1102_match_phy_device(struct phy_device *phydev, bool port0)
559{
560 int ret;
561
562 if ((phydev->phy_id & PHY_ID_MASK) != PHY_ID_TJA1102)
563 return 0;
564
565 ret = phy_read(phydev, MII_PHYSID2);
566 if (ret < 0)
567 return ret;
568
569 /* TJA1102 Port 1 has phyid 0 and doesn't support temperature
570 * and undervoltage alarms.
571 */
572 if (port0)
573 return ret ? 1 : 0;
574
575 return !ret;
576}
577
578static int tja1102_p0_match_phy_device(struct phy_device *phydev)
579{
580 return tja1102_match_phy_device(phydev, true);
581}
582
583static int tja1102_p1_match_phy_device(struct phy_device *phydev)
584{
585 return tja1102_match_phy_device(phydev, false);
586}
587
588static int tja11xx_ack_interrupt(struct phy_device *phydev)
589{
590 int ret;
591
592 ret = phy_read(phydev, MII_INTSRC);
593
594 return (ret < 0) ? ret : 0;
595}
596
597static int tja11xx_config_intr(struct phy_device *phydev)
598{
599 int value = 0;
600 int err;
601
602 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
603 err = tja11xx_ack_interrupt(phydev);
604 if (err)
605 return err;
606
607 value = MII_INTEN_LINK_FAIL | MII_INTEN_LINK_UP |
608 MII_INTEN_UV_ERR | MII_INTEN_TEMP_ERR;
609 err = phy_write(phydev, MII_INTEN, value);
610 } else {
611 err = phy_write(phydev, MII_INTEN, value);
612 if (err)
613 return err;
614
615 err = tja11xx_ack_interrupt(phydev);
616 }
617
618 return err;
619}
620
621static irqreturn_t tja11xx_handle_interrupt(struct phy_device *phydev)
622{
623 struct device *dev = &phydev->mdio.dev;
624 int irq_status;
625
626 irq_status = phy_read(phydev, MII_INTSRC);
627 if (irq_status < 0) {
628 phy_error(phydev);
629 return IRQ_NONE;
630 }
631
632 if (irq_status & MII_INTSRC_TEMP_ERR)
633 dev_warn(dev, "Overtemperature error detected (temp > 155C°).\n");
634 if (irq_status & MII_INTSRC_UV_ERR)
635 dev_warn(dev, "Undervoltage error detected.\n");
636
637 if (!(irq_status & MII_INTSRC_MASK))
638 return IRQ_NONE;
639
640 phy_trigger_machine(phydev);
641
642 return IRQ_HANDLED;
643}
644
645static int tja11xx_cable_test_start(struct phy_device *phydev)
646{
647 int ret;
648
649 ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
650 if (ret)
651 return ret;
652
653 ret = tja11xx_wakeup(phydev);
654 if (ret < 0)
655 return ret;
656
657 ret = tja11xx_disable_link_control(phydev);
658 if (ret < 0)
659 return ret;
660
661 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST);
662}
663
664/*
665 * | BI_DA+ | BI_DA- | Result
666 * | open | open | open
667 * | + short to - | - short to + | short
668 * | short to Vdd | open | open
669 * | open | shot to Vdd | open
670 * | short to Vdd | short to Vdd | short
671 * | shot to GND | open | open
672 * | open | shot to GND | open
673 * | short to GND | shot to GND | short
674 * | connected to active link partner (master) | shot and open
675 */
676static int tja11xx_cable_test_report_trans(u32 result)
677{
678 u32 mask = MII_EXTSTAT_SHORT_DETECT | MII_EXTSTAT_OPEN_DETECT;
679
680 if ((result & mask) == mask) {
681 /* connected to active link partner (master) */
682 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
683 } else if ((result & mask) == 0) {
684 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
685 } else if (result & MII_EXTSTAT_SHORT_DETECT) {
686 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
687 } else if (result & MII_EXTSTAT_OPEN_DETECT) {
688 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
689 } else {
690 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
691 }
692}
693
694static int tja11xx_cable_test_report(struct phy_device *phydev)
695{
696 int ret;
697
698 ret = phy_read(phydev, MII_EXTSTAT);
699 if (ret < 0)
700 return ret;
701
702 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
703 tja11xx_cable_test_report_trans(ret));
704
705 return 0;
706}
707
708static int tja11xx_cable_test_get_status(struct phy_device *phydev,
709 bool *finished)
710{
711 int ret;
712
713 *finished = false;
714
715 ret = phy_read(phydev, MII_ECTRL);
716 if (ret < 0)
717 return ret;
718
719 if (!(ret & MII_ECTRL_CABLE_TEST)) {
720 *finished = true;
721
722 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
723 if (ret)
724 return ret;
725
726 return tja11xx_cable_test_report(phydev);
727 }
728
729 return 0;
730}
731
732static struct phy_driver tja11xx_driver[] = {
733 {
734 PHY_ID_MATCH_MODEL(PHY_ID_TJA1100),
735 .name = "NXP TJA1100",
736 .features = PHY_BASIC_T1_FEATURES,
737 .probe = tja11xx_probe,
738 .soft_reset = tja11xx_soft_reset,
739 .config_aneg = tja11xx_config_aneg,
740 .config_init = tja11xx_config_init,
741 .read_status = tja11xx_read_status,
742 .get_sqi = tja11xx_get_sqi,
743 .get_sqi_max = tja11xx_get_sqi_max,
744 .suspend = genphy_suspend,
745 .resume = genphy_resume,
746 .set_loopback = genphy_loopback,
747 /* Statistics */
748 .get_sset_count = tja11xx_get_sset_count,
749 .get_strings = tja11xx_get_strings,
750 .get_stats = tja11xx_get_stats,
751 }, {
752 PHY_ID_MATCH_MODEL(PHY_ID_TJA1101),
753 .name = "NXP TJA1101",
754 .features = PHY_BASIC_T1_FEATURES,
755 .probe = tja11xx_probe,
756 .soft_reset = tja11xx_soft_reset,
757 .config_aneg = tja11xx_config_aneg,
758 .config_init = tja11xx_config_init,
759 .read_status = tja11xx_read_status,
760 .get_sqi = tja11xx_get_sqi,
761 .get_sqi_max = tja11xx_get_sqi_max,
762 .suspend = genphy_suspend,
763 .resume = genphy_resume,
764 .set_loopback = genphy_loopback,
765 /* Statistics */
766 .get_sset_count = tja11xx_get_sset_count,
767 .get_strings = tja11xx_get_strings,
768 .get_stats = tja11xx_get_stats,
769 }, {
770 .name = "NXP TJA1102 Port 0",
771 .features = PHY_BASIC_T1_FEATURES,
772 .flags = PHY_POLL_CABLE_TEST,
773 .probe = tja1102_p0_probe,
774 .soft_reset = tja11xx_soft_reset,
775 .config_aneg = tja11xx_config_aneg,
776 .config_init = tja11xx_config_init,
777 .read_status = tja11xx_read_status,
778 .get_sqi = tja11xx_get_sqi,
779 .get_sqi_max = tja11xx_get_sqi_max,
780 .match_phy_device = tja1102_p0_match_phy_device,
781 .suspend = genphy_suspend,
782 .resume = genphy_resume,
783 .set_loopback = genphy_loopback,
784 /* Statistics */
785 .get_sset_count = tja11xx_get_sset_count,
786 .get_strings = tja11xx_get_strings,
787 .get_stats = tja11xx_get_stats,
788 .config_intr = tja11xx_config_intr,
789 .handle_interrupt = tja11xx_handle_interrupt,
790 .cable_test_start = tja11xx_cable_test_start,
791 .cable_test_get_status = tja11xx_cable_test_get_status,
792 }, {
793 .name = "NXP TJA1102 Port 1",
794 .features = PHY_BASIC_T1_FEATURES,
795 .flags = PHY_POLL_CABLE_TEST,
796 /* currently no probe for Port 1 is need */
797 .soft_reset = tja11xx_soft_reset,
798 .config_aneg = tja11xx_config_aneg,
799 .config_init = tja11xx_config_init,
800 .read_status = tja11xx_read_status,
801 .get_sqi = tja11xx_get_sqi,
802 .get_sqi_max = tja11xx_get_sqi_max,
803 .match_phy_device = tja1102_p1_match_phy_device,
804 .suspend = genphy_suspend,
805 .resume = genphy_resume,
806 .set_loopback = genphy_loopback,
807 /* Statistics */
808 .get_sset_count = tja11xx_get_sset_count,
809 .get_strings = tja11xx_get_strings,
810 .get_stats = tja11xx_get_stats,
811 .config_intr = tja11xx_config_intr,
812 .handle_interrupt = tja11xx_handle_interrupt,
813 .cable_test_start = tja11xx_cable_test_start,
814 .cable_test_get_status = tja11xx_cable_test_get_status,
815 }
816};
817
818module_phy_driver(tja11xx_driver);
819
820static struct mdio_device_id __maybe_unused tja11xx_tbl[] = {
821 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) },
822 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) },
823 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) },
824 { }
825};
826
827MODULE_DEVICE_TABLE(mdio, tja11xx_tbl);
828
829MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
830MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver");
831MODULE_LICENSE("GPL");