tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
2/*
3 * include/linux/spi/spidev.h
4 *
5 * Copyright (C) 2006 SWAPP
6 * Andrea Paterniani <a.paterniani@swapp-eng.it>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef SPIDEV_H
24#define SPIDEV_H
25
26#include <linux/types.h>
27#include <linux/ioctl.h>
28
29/* User space versions of kernel symbols for SPI clocking modes,
30 * matching <linux/spi/spi.h>
31 */
32
33#define SPI_CPHA 0x01
34#define SPI_CPOL 0x02
35
36#define SPI_MODE_0 (0|0)
37#define SPI_MODE_1 (0|SPI_CPHA)
38#define SPI_MODE_2 (SPI_CPOL|0)
39#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
40
41#define SPI_CS_HIGH 0x04
42#define SPI_LSB_FIRST 0x08
43#define SPI_3WIRE 0x10
44#define SPI_LOOP 0x20
45#define SPI_NO_CS 0x40
46#define SPI_READY 0x80
47#define SPI_TX_DUAL 0x100
48#define SPI_TX_QUAD 0x200
49#define SPI_RX_DUAL 0x400
50#define SPI_RX_QUAD 0x800
51#define SPI_CS_WORD 0x1000
52#define SPI_TX_OCTAL 0x2000
53#define SPI_RX_OCTAL 0x4000
54#define SPI_3WIRE_HIZ 0x8000
55
56/*---------------------------------------------------------------------------*/
57
58/* IOCTL commands */
59
60#define SPI_IOC_MAGIC 'k'
61
62/**
63 * struct spi_ioc_transfer - describes a single SPI transfer
64 * @tx_buf: Holds pointer to userspace buffer with transmit data, or null.
65 * If no data is provided, zeroes are shifted out.
66 * @rx_buf: Holds pointer to userspace buffer for receive data, or null.
67 * @len: Length of tx and rx buffers, in bytes.
68 * @speed_hz: Temporary override of the device's bitrate.
69 * @bits_per_word: Temporary override of the device's wordsize.
70 * @delay_usecs: If nonzero, how long to delay after the last bit transfer
71 * before optionally deselecting the device before the next transfer.
72 * @cs_change: True to deselect device before starting the next transfer.
73 * @word_delay_usecs: If nonzero, how long to wait between words within one
74 * transfer. This property needs explicit support in the SPI controller,
75 * otherwise it is silently ignored.
76 *
77 * This structure is mapped directly to the kernel spi_transfer structure;
78 * the fields have the same meanings, except of course that the pointers
79 * are in a different address space (and may be of different sizes in some
80 * cases, such as 32-bit i386 userspace over a 64-bit x86_64 kernel).
81 * Zero-initialize the structure, including currently unused fields, to
82 * accommodate potential future updates.
83 *
84 * SPI_IOC_MESSAGE gives userspace the equivalent of kernel spi_sync().
85 * Pass it an array of related transfers, they'll execute together.
86 * Each transfer may be half duplex (either direction) or full duplex.
87 *
88 * struct spi_ioc_transfer mesg[4];
89 * ...
90 * status = ioctl(fd, SPI_IOC_MESSAGE(4), mesg);
91 *
92 * So for example one transfer might send a nine bit command (right aligned
93 * in a 16-bit word), the next could read a block of 8-bit data before
94 * terminating that command by temporarily deselecting the chip; the next
95 * could send a different nine bit command (re-selecting the chip), and the
96 * last transfer might write some register values.
97 */
98struct spi_ioc_transfer {
99 __u64 tx_buf;
100 __u64 rx_buf;
101
102 __u32 len;
103 __u32 speed_hz;
104
105 __u16 delay_usecs;
106 __u8 bits_per_word;
107 __u8 cs_change;
108 __u8 tx_nbits;
109 __u8 rx_nbits;
110 __u8 word_delay_usecs;
111 __u8 pad;
112
113 /* If the contents of 'struct spi_ioc_transfer' ever change
114 * incompatibly, then the ioctl number (currently 0) must change;
115 * ioctls with constant size fields get a bit more in the way of
116 * error checking than ones (like this) where that field varies.
117 *
118 * NOTE: struct layout is the same in 64bit and 32bit userspace.
119 */
120};
121
122/* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */
123#define SPI_MSGSIZE(N) \
124 ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \
125 ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0)
126#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)])
127
128
129/* Read / Write of SPI mode (SPI_MODE_0..SPI_MODE_3) (limited to 8 bits) */
130#define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, __u8)
131#define SPI_IOC_WR_MODE _IOW(SPI_IOC_MAGIC, 1, __u8)
132
133/* Read / Write SPI bit justification */
134#define SPI_IOC_RD_LSB_FIRST _IOR(SPI_IOC_MAGIC, 2, __u8)
135#define SPI_IOC_WR_LSB_FIRST _IOW(SPI_IOC_MAGIC, 2, __u8)
136
137/* Read / Write SPI device word length (1..N) */
138#define SPI_IOC_RD_BITS_PER_WORD _IOR(SPI_IOC_MAGIC, 3, __u8)
139#define SPI_IOC_WR_BITS_PER_WORD _IOW(SPI_IOC_MAGIC, 3, __u8)
140
141/* Read / Write SPI device default max speed hz */
142#define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, __u32)
143#define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, __u32)
144
145/* Read / Write of the SPI mode field */
146#define SPI_IOC_RD_MODE32 _IOR(SPI_IOC_MAGIC, 5, __u32)
147#define SPI_IOC_WR_MODE32 _IOW(SPI_IOC_MAGIC, 5, __u32)
148
149
150
151#endif /* SPIDEV_H */