tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef _HWMGR_H_
24#define _HWMGR_H_
25
26#include <linux/seq_file.h>
27#include "amd_powerplay.h"
28#include "hardwaremanager.h"
29#include "hwmgr_ppt.h"
30#include "ppatomctrl.h"
31#include "power_state.h"
32#include "smu_helper.h"
33
34struct pp_hwmgr;
35struct phm_fan_speed_info;
36struct pp_atomctrl_voltage_table;
37
38#define VOLTAGE_SCALE 4
39#define VOLTAGE_VID_OFFSET_SCALE1 625
40#define VOLTAGE_VID_OFFSET_SCALE2 100
41
42enum DISPLAY_GAP {
43 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
44 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
45 DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
46 DISPLAY_GAP_IGNORE = 3 /* Do not wait. */
47};
48typedef enum DISPLAY_GAP DISPLAY_GAP;
49
50enum BACO_STATE {
51 BACO_STATE_OUT = 0,
52 BACO_STATE_IN,
53};
54
55struct vi_dpm_level {
56 bool enabled;
57 uint32_t value;
58 uint32_t param1;
59};
60
61struct vi_dpm_table {
62 uint32_t count;
63 struct vi_dpm_level dpm_level[1];
64};
65
66#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
67#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
68#define PCIE_PERF_REQ_GEN1 2
69#define PCIE_PERF_REQ_GEN2 3
70#define PCIE_PERF_REQ_GEN3 4
71
72enum PHM_BackEnd_Magic {
73 PHM_Dummy_Magic = 0xAA5555AA,
74 PHM_RV770_Magic = 0xDCBAABCD,
75 PHM_Kong_Magic = 0x239478DF,
76 PHM_NIslands_Magic = 0x736C494E,
77 PHM_Sumo_Magic = 0x8339FA11,
78 PHM_SIslands_Magic = 0x369431AC,
79 PHM_Trinity_Magic = 0x96751873,
80 PHM_CIslands_Magic = 0x38AC78B0,
81 PHM_Kv_Magic = 0xDCBBABC0,
82 PHM_VIslands_Magic = 0x20130307,
83 PHM_Cz_Magic = 0x67DCBA25,
84 PHM_Rv_Magic = 0x20161121
85};
86
87struct phm_set_power_state_input {
88 const struct pp_hw_power_state *pcurrent_state;
89 const struct pp_hw_power_state *pnew_state;
90};
91
92struct phm_clock_array {
93 uint32_t count;
94 uint32_t values[1];
95};
96
97struct phm_clock_voltage_dependency_record {
98 uint32_t clk;
99 uint32_t v;
100};
101
102struct phm_vceclock_voltage_dependency_record {
103 uint32_t ecclk;
104 uint32_t evclk;
105 uint32_t v;
106};
107
108struct phm_uvdclock_voltage_dependency_record {
109 uint32_t vclk;
110 uint32_t dclk;
111 uint32_t v;
112};
113
114struct phm_samuclock_voltage_dependency_record {
115 uint32_t samclk;
116 uint32_t v;
117};
118
119struct phm_acpclock_voltage_dependency_record {
120 uint32_t acpclk;
121 uint32_t v;
122};
123
124struct phm_clock_voltage_dependency_table {
125 uint32_t count; /* Number of entries. */
126 struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
127};
128
129struct phm_phase_shedding_limits_record {
130 uint32_t Voltage;
131 uint32_t Sclk;
132 uint32_t Mclk;
133};
134
135struct phm_uvd_clock_voltage_dependency_record {
136 uint32_t vclk;
137 uint32_t dclk;
138 uint32_t v;
139};
140
141struct phm_uvd_clock_voltage_dependency_table {
142 uint8_t count;
143 struct phm_uvd_clock_voltage_dependency_record entries[1];
144};
145
146struct phm_acp_clock_voltage_dependency_record {
147 uint32_t acpclk;
148 uint32_t v;
149};
150
151struct phm_acp_clock_voltage_dependency_table {
152 uint32_t count;
153 struct phm_acp_clock_voltage_dependency_record entries[1];
154};
155
156struct phm_vce_clock_voltage_dependency_record {
157 uint32_t ecclk;
158 uint32_t evclk;
159 uint32_t v;
160};
161
162struct phm_phase_shedding_limits_table {
163 uint32_t count;
164 struct phm_phase_shedding_limits_record entries[1];
165};
166
167struct phm_vceclock_voltage_dependency_table {
168 uint8_t count; /* Number of entries. */
169 struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
170};
171
172struct phm_uvdclock_voltage_dependency_table {
173 uint8_t count; /* Number of entries. */
174 struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
175};
176
177struct phm_samuclock_voltage_dependency_table {
178 uint8_t count; /* Number of entries. */
179 struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
180};
181
182struct phm_acpclock_voltage_dependency_table {
183 uint32_t count; /* Number of entries. */
184 struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
185};
186
187struct phm_vce_clock_voltage_dependency_table {
188 uint8_t count;
189 struct phm_vce_clock_voltage_dependency_record entries[1];
190};
191
192
193enum SMU_ASIC_RESET_MODE
194{
195 SMU_ASIC_RESET_MODE_0,
196 SMU_ASIC_RESET_MODE_1,
197 SMU_ASIC_RESET_MODE_2,
198};
199
200struct pp_smumgr_func {
201 char *name;
202 int (*smu_init)(struct pp_hwmgr *hwmgr);
203 int (*smu_fini)(struct pp_hwmgr *hwmgr);
204 int (*start_smu)(struct pp_hwmgr *hwmgr);
205 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
206 uint32_t firmware);
207 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
208 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
209 uint32_t firmware);
210 uint32_t (*get_argument)(struct pp_hwmgr *hwmgr);
211 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
212 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
213 uint16_t msg, uint32_t parameter);
214 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
215 void **table);
216 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
217 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
218 int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
219 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
220 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
221 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
222 int (*init_smc_table)(struct pp_hwmgr *hwmgr);
223 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
224 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
225 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
226 uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
227 uint32_t (*get_mac_definition)(uint32_t value);
228 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
229 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
230 int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
231 int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */
232};
233
234struct pp_hwmgr_func {
235 int (*backend_init)(struct pp_hwmgr *hw_mgr);
236 int (*backend_fini)(struct pp_hwmgr *hw_mgr);
237 int (*asic_setup)(struct pp_hwmgr *hw_mgr);
238 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
239
240 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
241 struct pp_power_state *prequest_ps,
242 const struct pp_power_state *pcurrent_ps);
243
244 int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr);
245
246 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
247 enum amd_dpm_forced_level level);
248
249 int (*dynamic_state_management_enable)(
250 struct pp_hwmgr *hw_mgr);
251 int (*dynamic_state_management_disable)(
252 struct pp_hwmgr *hw_mgr);
253
254 int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
255 struct pp_hw_power_state *hw_ps);
256
257 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
258 unsigned long, struct pp_power_state *);
259 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
260 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
261 void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
262 void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
263 void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate);
264 uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
265 uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
266 int (*power_state_set)(struct pp_hwmgr *hwmgr,
267 const void *state);
268 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
269 int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr);
270 int (*display_config_changed)(struct pp_hwmgr *hwmgr);
271 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
272 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
273 const uint32_t *msg_id);
274 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
275 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
276 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
277 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
278 void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
279 uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
280 int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
281 int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
282 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
283 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
284 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
285 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
286 int (*register_irq_handlers)(struct pp_hwmgr *hwmgr);
287 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
288 int (*check_states_equal)(struct pp_hwmgr *hwmgr,
289 const struct pp_hw_power_state *pstate1,
290 const struct pp_hw_power_state *pstate2,
291 bool *equal);
292 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
293 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
294 bool cc6_disable, bool pstate_disable,
295 bool pstate_switch_disable);
296 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
297 struct amd_pp_simple_clock_info *info);
298 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
299 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
300 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
301 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
302 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
303 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
304 enum amd_pp_clock_type type,
305 struct pp_clock_levels_with_latency *clocks);
306 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
307 enum amd_pp_clock_type type,
308 struct pp_clock_levels_with_voltage *clocks);
309 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
310 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
311 struct pp_display_clock_request *clock);
312 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
313 int (*power_off_asic)(struct pp_hwmgr *hwmgr);
314 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
315 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
316 int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
317 int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
318 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
319 int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
320 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
321 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
322 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
323 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
324 int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
325 int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
326 int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
327 int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
328 uint32_t virtual_addr_low,
329 uint32_t virtual_addr_hi,
330 uint32_t mc_addr_low,
331 uint32_t mc_addr_hi,
332 uint32_t size);
333 int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr,
334 bool enable,
335 bool lock);
336 int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
337 struct PP_TemperatureRange *range);
338 int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
339 int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
340 int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
341 enum PP_OD_DPM_TABLE_COMMAND type,
342 long *input, uint32_t size);
343 int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
344 int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
345 int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
346 int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
347 int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
348 int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
349 int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
350 int (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr, bool *cap);
351 int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
352 int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
353 int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
354 int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
355 int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
356 int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
357 int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
358 int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
359 int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
360 int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr,
361 bool disable);
362};
363
364struct pp_table_func {
365 int (*pptable_init)(struct pp_hwmgr *hw_mgr);
366 int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
367 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
368 int (*pptable_get_vce_state_table_entry)(
369 struct pp_hwmgr *hwmgr,
370 unsigned long i,
371 struct amd_vce_state *vce_state,
372 void **clock_info,
373 unsigned long *flag);
374};
375
376union phm_cac_leakage_record {
377 struct {
378 uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */
379 uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */
380 };
381 struct {
382 uint16_t Vddc1;
383 uint16_t Vddc2;
384 uint16_t Vddc3;
385 };
386};
387
388struct phm_cac_leakage_table {
389 uint32_t count;
390 union phm_cac_leakage_record entries[1];
391};
392
393struct phm_samu_clock_voltage_dependency_record {
394 uint32_t samclk;
395 uint32_t v;
396};
397
398
399struct phm_samu_clock_voltage_dependency_table {
400 uint8_t count;
401 struct phm_samu_clock_voltage_dependency_record entries[1];
402};
403
404struct phm_cac_tdp_table {
405 uint16_t usTDP;
406 uint16_t usConfigurableTDP;
407 uint16_t usTDC;
408 uint16_t usBatteryPowerLimit;
409 uint16_t usSmallPowerLimit;
410 uint16_t usLowCACLeakage;
411 uint16_t usHighCACLeakage;
412 uint16_t usMaximumPowerDeliveryLimit;
413 uint16_t usEDCLimit;
414 uint16_t usOperatingTempMinLimit;
415 uint16_t usOperatingTempMaxLimit;
416 uint16_t usOperatingTempStep;
417 uint16_t usOperatingTempHyst;
418 uint16_t usDefaultTargetOperatingTemp;
419 uint16_t usTargetOperatingTemp;
420 uint16_t usPowerTuneDataSetID;
421 uint16_t usSoftwareShutdownTemp;
422 uint16_t usClockStretchAmount;
423 uint16_t usTemperatureLimitHotspot;
424 uint16_t usTemperatureLimitLiquid1;
425 uint16_t usTemperatureLimitLiquid2;
426 uint16_t usTemperatureLimitVrVddc;
427 uint16_t usTemperatureLimitVrMvdd;
428 uint16_t usTemperatureLimitPlx;
429 uint8_t ucLiquid1_I2C_address;
430 uint8_t ucLiquid2_I2C_address;
431 uint8_t ucLiquid_I2C_Line;
432 uint8_t ucVr_I2C_address;
433 uint8_t ucVr_I2C_Line;
434 uint8_t ucPlx_I2C_address;
435 uint8_t ucPlx_I2C_Line;
436 uint32_t usBoostPowerLimit;
437 uint8_t ucCKS_LDO_REFSEL;
438};
439
440struct phm_tdp_table {
441 uint16_t usTDP;
442 uint16_t usConfigurableTDP;
443 uint16_t usTDC;
444 uint16_t usBatteryPowerLimit;
445 uint16_t usSmallPowerLimit;
446 uint16_t usLowCACLeakage;
447 uint16_t usHighCACLeakage;
448 uint16_t usMaximumPowerDeliveryLimit;
449 uint16_t usEDCLimit;
450 uint16_t usOperatingTempMinLimit;
451 uint16_t usOperatingTempMaxLimit;
452 uint16_t usOperatingTempStep;
453 uint16_t usOperatingTempHyst;
454 uint16_t usDefaultTargetOperatingTemp;
455 uint16_t usTargetOperatingTemp;
456 uint16_t usPowerTuneDataSetID;
457 uint16_t usSoftwareShutdownTemp;
458 uint16_t usClockStretchAmount;
459 uint16_t usTemperatureLimitTedge;
460 uint16_t usTemperatureLimitHotspot;
461 uint16_t usTemperatureLimitLiquid1;
462 uint16_t usTemperatureLimitLiquid2;
463 uint16_t usTemperatureLimitHBM;
464 uint16_t usTemperatureLimitVrVddc;
465 uint16_t usTemperatureLimitVrMvdd;
466 uint16_t usTemperatureLimitPlx;
467 uint8_t ucLiquid1_I2C_address;
468 uint8_t ucLiquid2_I2C_address;
469 uint8_t ucLiquid_I2C_Line;
470 uint8_t ucVr_I2C_address;
471 uint8_t ucVr_I2C_Line;
472 uint8_t ucPlx_I2C_address;
473 uint8_t ucPlx_I2C_Line;
474 uint8_t ucLiquid_I2C_LineSDA;
475 uint8_t ucVr_I2C_LineSDA;
476 uint8_t ucPlx_I2C_LineSDA;
477 uint32_t usBoostPowerLimit;
478 uint16_t usBoostStartTemperature;
479 uint16_t usBoostStopTemperature;
480 uint32_t ulBoostClock;
481};
482
483struct phm_ppm_table {
484 uint8_t ppm_design;
485 uint16_t cpu_core_number;
486 uint32_t platform_tdp;
487 uint32_t small_ac_platform_tdp;
488 uint32_t platform_tdc;
489 uint32_t small_ac_platform_tdc;
490 uint32_t apu_tdp;
491 uint32_t dgpu_tdp;
492 uint32_t dgpu_ulv_power;
493 uint32_t tj_max;
494};
495
496struct phm_vq_budgeting_record {
497 uint32_t ulCUs;
498 uint32_t ulSustainableSOCPowerLimitLow;
499 uint32_t ulSustainableSOCPowerLimitHigh;
500 uint32_t ulMinSclkLow;
501 uint32_t ulMinSclkHigh;
502 uint8_t ucDispConfig;
503 uint32_t ulDClk;
504 uint32_t ulEClk;
505 uint32_t ulSustainableSclk;
506 uint32_t ulSustainableCUs;
507};
508
509struct phm_vq_budgeting_table {
510 uint8_t numEntries;
511 struct phm_vq_budgeting_record entries[1];
512};
513
514struct phm_clock_and_voltage_limits {
515 uint32_t sclk;
516 uint32_t mclk;
517 uint32_t gfxclk;
518 uint16_t vddc;
519 uint16_t vddci;
520 uint16_t vddgfx;
521 uint16_t vddmem;
522};
523
524/* Structure to hold PPTable information */
525
526struct phm_ppt_v1_information {
527 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
528 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
529 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
530 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
531 struct phm_clock_array *valid_sclk_values;
532 struct phm_clock_array *valid_mclk_values;
533 struct phm_clock_array *valid_socclk_values;
534 struct phm_clock_array *valid_dcefclk_values;
535 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
536 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
537 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
538 struct phm_ppm_table *ppm_parameter_table;
539 struct phm_cac_tdp_table *cac_dtp_table;
540 struct phm_tdp_table *tdp_table;
541 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
542 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
543 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
544 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
545 struct phm_ppt_v1_pcie_table *pcie_table;
546 struct phm_ppt_v1_gpio_table *gpio_table;
547 uint16_t us_ulv_voltage_offset;
548 uint16_t us_ulv_smnclk_did;
549 uint16_t us_ulv_mp1clk_did;
550 uint16_t us_ulv_gfxclk_bypass;
551 uint16_t us_gfxclk_slew_rate;
552 uint16_t us_min_gfxclk_freq_limit;
553};
554
555struct phm_ppt_v2_information {
556 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
557 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
558 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
559 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
560 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
561 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
562 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
563 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
564
565 struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
566
567 struct phm_clock_array *valid_sclk_values;
568 struct phm_clock_array *valid_mclk_values;
569 struct phm_clock_array *valid_socclk_values;
570 struct phm_clock_array *valid_dcefclk_values;
571
572 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
573 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
574
575 struct phm_ppm_table *ppm_parameter_table;
576 struct phm_cac_tdp_table *cac_dtp_table;
577 struct phm_tdp_table *tdp_table;
578
579 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
580 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
581 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
582 struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
583
584 struct phm_ppt_v1_pcie_table *pcie_table;
585
586 uint16_t us_ulv_voltage_offset;
587 uint16_t us_ulv_smnclk_did;
588 uint16_t us_ulv_mp1clk_did;
589 uint16_t us_ulv_gfxclk_bypass;
590 uint16_t us_gfxclk_slew_rate;
591 uint16_t us_min_gfxclk_freq_limit;
592
593 uint8_t uc_gfx_dpm_voltage_mode;
594 uint8_t uc_soc_dpm_voltage_mode;
595 uint8_t uc_uclk_dpm_voltage_mode;
596 uint8_t uc_uvd_dpm_voltage_mode;
597 uint8_t uc_vce_dpm_voltage_mode;
598 uint8_t uc_mp0_dpm_voltage_mode;
599 uint8_t uc_dcef_dpm_voltage_mode;
600};
601
602struct phm_ppt_v3_information
603{
604 uint8_t uc_thermal_controller_type;
605
606 uint16_t us_small_power_limit1;
607 uint16_t us_small_power_limit2;
608 uint16_t us_boost_power_limit;
609
610 uint16_t us_od_turbo_power_limit;
611 uint16_t us_od_powersave_power_limit;
612 uint16_t us_software_shutdown_temp;
613
614 uint32_t *power_saving_clock_max;
615 uint32_t *power_saving_clock_min;
616
617 uint8_t *od_feature_capabilities;
618 uint32_t *od_settings_max;
619 uint32_t *od_settings_min;
620
621 void *smc_pptable;
622};
623
624struct phm_dynamic_state_info {
625 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
626 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
627 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
628 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
629 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
630 struct phm_clock_array *valid_sclk_values;
631 struct phm_clock_array *valid_mclk_values;
632 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
633 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
634 uint32_t mclk_sclk_ratio;
635 uint32_t sclk_mclk_delta;
636 uint32_t vddc_vddci_delta;
637 uint32_t min_vddc_for_pcie_gen2;
638 struct phm_cac_leakage_table *cac_leakage_table;
639 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
640
641 struct phm_vce_clock_voltage_dependency_table
642 *vce_clock_voltage_dependency_table;
643 struct phm_uvd_clock_voltage_dependency_table
644 *uvd_clock_voltage_dependency_table;
645 struct phm_acp_clock_voltage_dependency_table
646 *acp_clock_voltage_dependency_table;
647 struct phm_samu_clock_voltage_dependency_table
648 *samu_clock_voltage_dependency_table;
649
650 struct phm_ppm_table *ppm_parameter_table;
651 struct phm_cac_tdp_table *cac_dtp_table;
652 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
653};
654
655struct pp_fan_info {
656 bool bNoFan;
657 uint8_t ucTachometerPulsesPerRevolution;
658 uint32_t ulMinRPM;
659 uint32_t ulMaxRPM;
660};
661
662struct pp_advance_fan_control_parameters {
663 uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
664 uint16_t usTMed; /* The middle temperature where we change slopes. */
665 uint16_t usTHigh; /* The high temperature for setting the second slope. */
666 uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */
667 uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */
668 uint16_t usPWMHigh; /* The PWM value at THigh. */
669 uint8_t ucTHyst; /* Temperature hysteresis. Integer. */
670 uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */
671 uint16_t usTMax; /* The max temperature */
672 uint8_t ucFanControlMode;
673 uint16_t usFanPWMMinLimit;
674 uint16_t usFanPWMMaxLimit;
675 uint16_t usFanPWMStep;
676 uint16_t usDefaultMaxFanPWM;
677 uint16_t usFanOutputSensitivity;
678 uint16_t usDefaultFanOutputSensitivity;
679 uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */
680 uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
681 uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */
682 uint16_t usFanRPMStep; /* Step increments/decerements, in percent */
683 uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
684 uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
685 uint16_t usFanCurrentLow; /* Low current */
686 uint16_t usFanCurrentHigh; /* High current */
687 uint16_t usFanRPMLow; /* Low RPM */
688 uint16_t usFanRPMHigh; /* High RPM */
689 uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
690 uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */
691 uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */
692 uint16_t usFanGainEdge; /* The following is added for Fiji */
693 uint16_t usFanGainHotspot;
694 uint16_t usFanGainLiquid;
695 uint16_t usFanGainVrVddc;
696 uint16_t usFanGainVrMvdd;
697 uint16_t usFanGainPlx;
698 uint16_t usFanGainHbm;
699 uint8_t ucEnableZeroRPM;
700 uint8_t ucFanStopTemperature;
701 uint8_t ucFanStartTemperature;
702 uint32_t ulMaxFanSCLKAcousticLimit; /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
703 uint32_t ulTargetGfxClk;
704 uint16_t usZeroRPMStartTemperature;
705 uint16_t usZeroRPMStopTemperature;
706 uint16_t usMGpuThrottlingRPMLimit;
707};
708
709struct pp_thermal_controller_info {
710 uint8_t ucType;
711 uint8_t ucI2cLine;
712 uint8_t ucI2cAddress;
713 uint8_t use_hw_fan_control;
714 struct pp_fan_info fanInfo;
715 struct pp_advance_fan_control_parameters advanceFanControlParameters;
716};
717
718struct phm_microcode_version_info {
719 uint32_t SMC;
720 uint32_t DMCU;
721 uint32_t MC;
722 uint32_t NB;
723};
724
725enum PP_TABLE_VERSION {
726 PP_TABLE_V0 = 0,
727 PP_TABLE_V1,
728 PP_TABLE_V2,
729 PP_TABLE_MAX
730};
731
732/**
733 * The main hardware manager structure.
734 */
735#define Workload_Policy_Max 6
736
737struct pp_hwmgr {
738 void *adev;
739 uint32_t chip_family;
740 uint32_t chip_id;
741 uint32_t smu_version;
742 bool not_vf;
743 bool pm_en;
744 bool pp_one_vf;
745 struct mutex smu_lock;
746 struct mutex msg_lock;
747
748 uint32_t pp_table_version;
749 void *device;
750 struct pp_smumgr *smumgr;
751 const void *soft_pp_table;
752 uint32_t soft_pp_table_size;
753 void *hardcode_pp_table;
754 bool need_pp_table_upload;
755
756 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
757 uint32_t num_vce_state_tables;
758
759 enum amd_dpm_forced_level dpm_level;
760 enum amd_dpm_forced_level saved_dpm_level;
761 enum amd_dpm_forced_level request_dpm_level;
762 uint32_t usec_timeout;
763 void *pptable;
764 struct phm_platform_descriptor platform_descriptor;
765 void *backend;
766
767 void *smu_backend;
768 const struct pp_smumgr_func *smumgr_funcs;
769 bool is_kicker;
770
771 enum PP_DAL_POWERLEVEL dal_power_level;
772 struct phm_dynamic_state_info dyn_state;
773 const struct pp_hwmgr_func *hwmgr_func;
774 const struct pp_table_func *pptable_func;
775
776 struct pp_power_state *ps;
777 uint32_t num_ps;
778 struct pp_thermal_controller_info thermal_controller;
779 bool fan_ctrl_is_in_default_mode;
780 uint32_t fan_ctrl_default_mode;
781 bool fan_ctrl_enabled;
782 uint32_t tmin;
783 struct phm_microcode_version_info microcode_version_info;
784 uint32_t ps_size;
785 struct pp_power_state *current_ps;
786 struct pp_power_state *request_ps;
787 struct pp_power_state *boot_ps;
788 struct pp_power_state *uvd_ps;
789 const struct amd_pp_display_configuration *display_config;
790 uint32_t feature_mask;
791 bool avfs_supported;
792 /* UMD Pstate */
793 bool en_umd_pstate;
794 uint32_t power_profile_mode;
795 uint32_t default_power_profile_mode;
796 uint32_t pstate_sclk;
797 uint32_t pstate_mclk;
798 bool od_enabled;
799 uint32_t power_limit;
800 uint32_t default_power_limit;
801 uint32_t workload_mask;
802 uint32_t workload_prority[Workload_Policy_Max];
803 uint32_t workload_setting[Workload_Policy_Max];
804 bool gfxoff_state_changed_by_workload;
805};
806
807int hwmgr_early_init(struct pp_hwmgr *hwmgr);
808int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
809int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
810int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
811int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
812int hwmgr_suspend(struct pp_hwmgr *hwmgr);
813int hwmgr_resume(struct pp_hwmgr *hwmgr);
814
815int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
816 enum amd_pp_task task_id,
817 enum amd_pm_state_type *user_state);
818
819
820#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
821
822
823#endif /* _HWMGR_H_ */