tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019, Intel Corporation
4 */
5
6/dts-v1/;
7#include <dt-bindings/reset/altr,rst-mgr-s10.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/clock/agilex-clock.h>
10
11/ {
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
19 ranges;
20
21 service_reserved: svcbuffer@0 {
22 compatible = "shared-dma-pool";
23 reg = <0x0 0x0 0x0 0x1000000>;
24 alignment = <0x1000>;
25 no-map;
26 };
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu0: cpu@0 {
34 compatible = "arm,cortex-a53";
35 device_type = "cpu";
36 enable-method = "psci";
37 reg = <0x0>;
38 };
39
40 cpu1: cpu@1 {
41 compatible = "arm,cortex-a53";
42 device_type = "cpu";
43 enable-method = "psci";
44 reg = <0x1>;
45 };
46
47 cpu2: cpu@2 {
48 compatible = "arm,cortex-a53";
49 device_type = "cpu";
50 enable-method = "psci";
51 reg = <0x2>;
52 };
53
54 cpu3: cpu@3 {
55 compatible = "arm,cortex-a53";
56 device_type = "cpu";
57 enable-method = "psci";
58 reg = <0x3>;
59 };
60 };
61
62 pmu {
63 compatible = "arm,armv8-pmuv3";
64 interrupts = <0 170 4>,
65 <0 171 4>,
66 <0 172 4>,
67 <0 173 4>;
68 interrupt-affinity = <&cpu0>,
69 <&cpu1>,
70 <&cpu2>,
71 <&cpu3>;
72 interrupt-parent = <&intc>;
73 };
74
75 psci {
76 compatible = "arm,psci-0.2";
77 method = "smc";
78 };
79
80 intc: intc@fffc1000 {
81 compatible = "arm,gic-400", "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
83 interrupt-controller;
84 reg = <0x0 0xfffc1000 0x0 0x1000>,
85 <0x0 0xfffc2000 0x0 0x2000>,
86 <0x0 0xfffc4000 0x0 0x2000>,
87 <0x0 0xfffc6000 0x0 0x2000>;
88 };
89
90 soc {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "simple-bus";
94 device_type = "soc";
95 interrupt-parent = <&intc>;
96 ranges = <0 0 0 0xffffffff>;
97
98 base_fpga_region {
99 #address-cells = <0x1>;
100 #size-cells = <0x1>;
101 compatible = "fpga-region";
102 fpga-mgr = <&fpga_mgr>;
103 };
104
105 clkmgr: clock-controller@ffd10000 {
106 compatible = "intel,agilex-clkmgr";
107 reg = <0xffd10000 0x1000>;
108 #clock-cells = <1>;
109 };
110
111 clocks {
112 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
113 #clock-cells = <0>;
114 compatible = "fixed-clock";
115 };
116
117 cb_intosc_ls_clk: cb-intosc-ls-clk {
118 #clock-cells = <0>;
119 compatible = "fixed-clock";
120 };
121
122 f2s_free_clk: f2s-free-clk {
123 #clock-cells = <0>;
124 compatible = "fixed-clock";
125 };
126
127 osc1: osc1 {
128 #clock-cells = <0>;
129 compatible = "fixed-clock";
130 };
131
132 qspi_clk: qspi-clk {
133 #clock-cells = <0>;
134 compatible = "fixed-clock";
135 clock-frequency = <200000000>;
136 };
137 };
138
139 gmac0: ethernet@ff800000 {
140 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
141 reg = <0xff800000 0x2000>;
142 interrupts = <0 90 4>;
143 interrupt-names = "macirq";
144 mac-address = [00 00 00 00 00 00];
145 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
146 reset-names = "stmmaceth", "stmmaceth-ocp";
147 tx-fifo-depth = <16384>;
148 rx-fifo-depth = <16384>;
149 snps,multicast-filter-bins = <256>;
150 iommus = <&smmu 1>;
151 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
152 clocks = <&clkmgr AGILEX_EMAC0_CLK>;
153 clock-names = "stmmaceth";
154 status = "disabled";
155 };
156
157 gmac1: ethernet@ff802000 {
158 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
159 reg = <0xff802000 0x2000>;
160 interrupts = <0 91 4>;
161 interrupt-names = "macirq";
162 mac-address = [00 00 00 00 00 00];
163 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
164 reset-names = "stmmaceth", "stmmaceth-ocp";
165 tx-fifo-depth = <16384>;
166 rx-fifo-depth = <16384>;
167 snps,multicast-filter-bins = <256>;
168 iommus = <&smmu 2>;
169 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
170 clocks = <&clkmgr AGILEX_EMAC1_CLK>;
171 clock-names = "stmmaceth";
172 status = "disabled";
173 };
174
175 gmac2: ethernet@ff804000 {
176 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
177 reg = <0xff804000 0x2000>;
178 interrupts = <0 92 4>;
179 interrupt-names = "macirq";
180 mac-address = [00 00 00 00 00 00];
181 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
182 reset-names = "stmmaceth", "stmmaceth-ocp";
183 tx-fifo-depth = <16384>;
184 rx-fifo-depth = <16384>;
185 snps,multicast-filter-bins = <256>;
186 iommus = <&smmu 3>;
187 altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
188 clocks = <&clkmgr AGILEX_EMAC2_CLK>;
189 clock-names = "stmmaceth";
190 status = "disabled";
191 };
192
193 gpio0: gpio@ffc03200 {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "snps,dw-apb-gpio";
197 reg = <0xffc03200 0x100>;
198 resets = <&rst GPIO0_RESET>;
199 status = "disabled";
200
201 porta: gpio-controller@0 {
202 compatible = "snps,dw-apb-gpio-port";
203 gpio-controller;
204 #gpio-cells = <2>;
205 snps,nr-gpios = <24>;
206 reg = <0>;
207 interrupt-controller;
208 #interrupt-cells = <2>;
209 interrupts = <0 110 4>;
210 };
211 };
212
213 gpio1: gpio@ffc03300 {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "snps,dw-apb-gpio";
217 reg = <0xffc03300 0x100>;
218 resets = <&rst GPIO1_RESET>;
219 status = "disabled";
220
221 portb: gpio-controller@0 {
222 compatible = "snps,dw-apb-gpio-port";
223 gpio-controller;
224 #gpio-cells = <2>;
225 snps,nr-gpios = <24>;
226 reg = <0>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
229 interrupts = <0 111 4>;
230 };
231 };
232
233 i2c0: i2c@ffc02800 {
234 #address-cells = <1>;
235 #size-cells = <0>;
236 compatible = "snps,designware-i2c";
237 reg = <0xffc02800 0x100>;
238 interrupts = <0 103 4>;
239 resets = <&rst I2C0_RESET>;
240 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
241 status = "disabled";
242 };
243
244 i2c1: i2c@ffc02900 {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 compatible = "snps,designware-i2c";
248 reg = <0xffc02900 0x100>;
249 interrupts = <0 104 4>;
250 resets = <&rst I2C1_RESET>;
251 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
252 status = "disabled";
253 };
254
255 i2c2: i2c@ffc02a00 {
256 #address-cells = <1>;
257 #size-cells = <0>;
258 compatible = "snps,designware-i2c";
259 reg = <0xffc02a00 0x100>;
260 interrupts = <0 105 4>;
261 resets = <&rst I2C2_RESET>;
262 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
263 status = "disabled";
264 };
265
266 i2c3: i2c@ffc02b00 {
267 #address-cells = <1>;
268 #size-cells = <0>;
269 compatible = "snps,designware-i2c";
270 reg = <0xffc02b00 0x100>;
271 interrupts = <0 106 4>;
272 resets = <&rst I2C3_RESET>;
273 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
274 status = "disabled";
275 };
276
277 i2c4: i2c@ffc02c00 {
278 #address-cells = <1>;
279 #size-cells = <0>;
280 compatible = "snps,designware-i2c";
281 reg = <0xffc02c00 0x100>;
282 interrupts = <0 107 4>;
283 resets = <&rst I2C4_RESET>;
284 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
285 status = "disabled";
286 };
287
288 mmc: dwmmc0@ff808000 {
289 #address-cells = <1>;
290 #size-cells = <0>;
291 compatible = "altr,socfpga-dw-mshc";
292 reg = <0xff808000 0x1000>;
293 interrupts = <0 96 4>;
294 fifo-depth = <0x400>;
295 resets = <&rst SDMMC_RESET>;
296 reset-names = "reset";
297 clocks = <&clkmgr AGILEX_L4_MP_CLK>,
298 <&clkmgr AGILEX_SDMMC_CLK>;
299 clock-names = "biu", "ciu";
300 iommus = <&smmu 5>;
301 status = "disabled";
302 };
303
304 nand: nand@ffb90000 {
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "altr,socfpga-denali-nand";
308 reg = <0xffb90000 0x10000>,
309 <0xffb80000 0x1000>;
310 reg-names = "nand_data", "denali_reg";
311 interrupts = <0 97 4>;
312 clocks = <&clkmgr AGILEX_NAND_CLK>,
313 <&clkmgr AGILEX_NAND_X_CLK>,
314 <&clkmgr AGILEX_NAND_ECC_CLK>;
315 clock-names = "nand", "nand_x", "ecc";
316 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
317 status = "disabled";
318 };
319
320 ocram: sram@ffe00000 {
321 compatible = "mmio-sram";
322 reg = <0xffe00000 0x40000>;
323 };
324
325 pdma: pdma@ffda0000 {
326 compatible = "arm,pl330", "arm,primecell";
327 reg = <0xffda0000 0x1000>;
328 interrupts = <0 81 4>,
329 <0 82 4>,
330 <0 83 4>,
331 <0 84 4>,
332 <0 85 4>,
333 <0 86 4>,
334 <0 87 4>,
335 <0 88 4>,
336 <0 89 4>;
337 #dma-cells = <1>;
338 #dma-channels = <8>;
339 #dma-requests = <32>;
340 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
341 reset-names = "dma", "dma-ocp";
342 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
343 clock-names = "apb_pclk";
344 };
345
346 rst: rstmgr@ffd11000 {
347 #reset-cells = <1>;
348 compatible = "altr,stratix10-rst-mgr";
349 reg = <0xffd11000 0x100>;
350 };
351
352 smmu: iommu@fa000000 {
353 compatible = "arm,mmu-500", "arm,smmu-v2";
354 reg = <0xfa000000 0x40000>;
355 #global-interrupts = <2>;
356 #iommu-cells = <1>;
357 interrupt-parent = <&intc>;
358 interrupts = <0 128 4>, /* Global Secure Fault */
359 <0 129 4>, /* Global Non-secure Fault */
360 /* Non-secure Context Interrupts (32) */
361 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
362 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
363 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
364 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
365 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
366 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
367 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
368 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
369 stream-match-mask = <0x7ff0>;
370 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
371 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
372 <&clkmgr AGILEX_L4_MAIN_CLK>;
373 status = "disabled";
374 };
375
376 spi0: spi@ffda4000 {
377 compatible = "snps,dw-apb-ssi";
378 #address-cells = <1>;
379 #size-cells = <0>;
380 reg = <0xffda4000 0x1000>;
381 interrupts = <0 99 4>;
382 resets = <&rst SPIM0_RESET>;
383 reset-names = "spi";
384 reg-io-width = <4>;
385 num-cs = <4>;
386 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
387 status = "disabled";
388 };
389
390 spi1: spi@ffda5000 {
391 compatible = "snps,dw-apb-ssi";
392 #address-cells = <1>;
393 #size-cells = <0>;
394 reg = <0xffda5000 0x1000>;
395 interrupts = <0 100 4>;
396 resets = <&rst SPIM1_RESET>;
397 reset-names = "spi";
398 reg-io-width = <4>;
399 num-cs = <4>;
400 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
401 status = "disabled";
402 };
403
404 sysmgr: sysmgr@ffd12000 {
405 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
406 reg = <0xffd12000 0x500>;
407 };
408
409 /* Local timer */
410 timer {
411 compatible = "arm,armv8-timer";
412 interrupts = <1 13 0xf08>,
413 <1 14 0xf08>,
414 <1 11 0xf08>,
415 <1 10 0xf08>;
416 };
417
418 timer0: timer0@ffc03000 {
419 compatible = "snps,dw-apb-timer";
420 interrupts = <0 113 4>;
421 reg = <0xffc03000 0x100>;
422 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
423 clock-names = "timer";
424 };
425
426 timer1: timer1@ffc03100 {
427 compatible = "snps,dw-apb-timer";
428 interrupts = <0 114 4>;
429 reg = <0xffc03100 0x100>;
430 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
431 clock-names = "timer";
432 };
433
434 timer2: timer2@ffd00000 {
435 compatible = "snps,dw-apb-timer";
436 interrupts = <0 115 4>;
437 reg = <0xffd00000 0x100>;
438 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
439 clock-names = "timer";
440 };
441
442 timer3: timer3@ffd00100 {
443 compatible = "snps,dw-apb-timer";
444 interrupts = <0 116 4>;
445 reg = <0xffd00100 0x100>;
446 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
447 clock-names = "timer";
448 };
449
450 uart0: serial0@ffc02000 {
451 compatible = "snps,dw-apb-uart";
452 reg = <0xffc02000 0x100>;
453 interrupts = <0 108 4>;
454 reg-shift = <2>;
455 reg-io-width = <4>;
456 resets = <&rst UART0_RESET>;
457 status = "disabled";
458 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
459 };
460
461 uart1: serial1@ffc02100 {
462 compatible = "snps,dw-apb-uart";
463 reg = <0xffc02100 0x100>;
464 interrupts = <0 109 4>;
465 reg-shift = <2>;
466 reg-io-width = <4>;
467 resets = <&rst UART1_RESET>;
468 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
469 status = "disabled";
470 };
471
472 usbphy0: usbphy@0 {
473 #phy-cells = <0>;
474 compatible = "usb-nop-xceiv";
475 status = "okay";
476 };
477
478 usb0: usb@ffb00000 {
479 compatible = "snps,dwc2";
480 reg = <0xffb00000 0x40000>;
481 interrupts = <0 93 4>;
482 phys = <&usbphy0>;
483 phy-names = "usb2-phy";
484 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
485 reset-names = "dwc2", "dwc2-ecc";
486 clocks = <&clkmgr AGILEX_USB_CLK>;
487 iommus = <&smmu 6>;
488 status = "disabled";
489 };
490
491 usb1: usb@ffb40000 {
492 compatible = "snps,dwc2";
493 reg = <0xffb40000 0x40000>;
494 interrupts = <0 94 4>;
495 phys = <&usbphy0>;
496 phy-names = "usb2-phy";
497 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
498 reset-names = "dwc2", "dwc2-ecc";
499 iommus = <&smmu 7>;
500 clocks = <&clkmgr AGILEX_USB_CLK>;
501 status = "disabled";
502 };
503
504 watchdog0: watchdog@ffd00200 {
505 compatible = "snps,dw-wdt";
506 reg = <0xffd00200 0x100>;
507 interrupts = <0 117 4>;
508 resets = <&rst WATCHDOG0_RESET>;
509 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
510 status = "disabled";
511 };
512
513 watchdog1: watchdog@ffd00300 {
514 compatible = "snps,dw-wdt";
515 reg = <0xffd00300 0x100>;
516 interrupts = <0 118 4>;
517 resets = <&rst WATCHDOG1_RESET>;
518 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
519 status = "disabled";
520 };
521
522 watchdog2: watchdog@ffd00400 {
523 compatible = "snps,dw-wdt";
524 reg = <0xffd00400 0x100>;
525 interrupts = <0 125 4>;
526 resets = <&rst WATCHDOG2_RESET>;
527 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
528 status = "disabled";
529 };
530
531 watchdog3: watchdog@ffd00500 {
532 compatible = "snps,dw-wdt";
533 reg = <0xffd00500 0x100>;
534 interrupts = <0 126 4>;
535 resets = <&rst WATCHDOG3_RESET>;
536 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
537 status = "disabled";
538 };
539
540 sdr: sdr@f8011100 {
541 compatible = "altr,sdr-ctl", "syscon";
542 reg = <0xf8011100 0xc0>;
543 };
544
545 eccmgr {
546 compatible = "altr,socfpga-s10-ecc-manager",
547 "altr,socfpga-a10-ecc-manager";
548 altr,sysmgr-syscon = <&sysmgr>;
549 #address-cells = <1>;
550 #size-cells = <1>;
551 interrupts = <0 15 4>;
552 interrupt-controller;
553 #interrupt-cells = <2>;
554 ranges;
555
556 sdramedac {
557 compatible = "altr,sdram-edac-s10";
558 altr,sdr-syscon = <&sdr>;
559 interrupts = <16 4>;
560 };
561
562 ocram-ecc@ff8cc000 {
563 compatible = "altr,socfpga-s10-ocram-ecc",
564 "altr,socfpga-a10-ocram-ecc";
565 reg = <0xff8cc000 0x100>;
566 altr,ecc-parent = <&ocram>;
567 interrupts = <1 4>;
568 };
569
570 usb0-ecc@ff8c4000 {
571 compatible = "altr,socfpga-s10-usb-ecc",
572 "altr,socfpga-usb-ecc";
573 reg = <0xff8c4000 0x100>;
574 altr,ecc-parent = <&usb0>;
575 interrupts = <2 4>;
576 };
577
578 emac0-rx-ecc@ff8c0000 {
579 compatible = "altr,socfpga-s10-eth-mac-ecc",
580 "altr,socfpga-eth-mac-ecc";
581 reg = <0xff8c0000 0x100>;
582 altr,ecc-parent = <&gmac0>;
583 interrupts = <4 4>;
584 };
585
586 emac0-tx-ecc@ff8c0400 {
587 compatible = "altr,socfpga-s10-eth-mac-ecc",
588 "altr,socfpga-eth-mac-ecc";
589 reg = <0xff8c0400 0x100>;
590 altr,ecc-parent = <&gmac0>;
591 interrupts = <5 4>;
592 };
593
594 sdmmca-ecc@ff8c8c00 {
595 compatible = "altr,socfpga-s10-sdmmc-ecc",
596 "altr,socfpga-sdmmc-ecc";
597 reg = <0xff8c8c00 0x100>;
598 altr,ecc-parent = <&mmc>;
599 interrupts = <14 4>,
600 <15 4>;
601 };
602 };
603
604 qspi: spi@ff8d2000 {
605 compatible = "cdns,qspi-nor";
606 #address-cells = <1>;
607 #size-cells = <0>;
608 reg = <0xff8d2000 0x100>,
609 <0xff900000 0x100000>;
610 interrupts = <0 3 4>;
611 cdns,fifo-depth = <128>;
612 cdns,fifo-width = <4>;
613 cdns,trigger-address = <0x00000000>;
614 clocks = <&qspi_clk>;
615
616 status = "disabled";
617 };
618
619 firmware {
620 svc {
621 compatible = "intel,agilex-svc";
622 method = "smc";
623 memory-region = <&service_reserved>;
624
625 fpga_mgr: fpga-mgr {
626 compatible = "intel,agilex-soc-fpga-mgr";
627 };
628 };
629 };
630 };
631};