tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/pinctrl/rockchip.h>
7#include <dt-bindings/clock/rk3288-cru.h>
8#include <dt-bindings/power/rk3288-power.h>
9#include <dt-bindings/thermal/thermal.h>
10#include <dt-bindings/soc/rockchip,boot-mode.h>
11
12/ {
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 compatible = "rockchip,rk3288";
17
18 interrupt-parent = <&gic>;
19
20 aliases {
21 ethernet0 = &gmac;
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 i2c4 = &i2c4;
27 i2c5 = &i2c5;
28 mshc0 = &emmc;
29 mshc1 = &sdmmc;
30 mshc2 = &sdio0;
31 mshc3 = &sdio1;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 spi0 = &spi0;
38 spi1 = &spi1;
39 spi2 = &spi2;
40 };
41
42 arm-pmu {
43 compatible = "arm,cortex-a12-pmu";
44 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
48 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54 enable-method = "rockchip,rk3066-smp";
55 rockchip,pmu = <&pmu>;
56
57 cpu0: cpu@500 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a12";
60 reg = <0x500>;
61 resets = <&cru SRST_CORE0>;
62 operating-points-v2 = <&cpu_opp_table>;
63 #cooling-cells = <2>; /* min followed by max */
64 clock-latency = <40000>;
65 clocks = <&cru ARMCLK>;
66 dynamic-power-coefficient = <370>;
67 };
68 cpu1: cpu@501 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a12";
71 reg = <0x501>;
72 resets = <&cru SRST_CORE1>;
73 operating-points-v2 = <&cpu_opp_table>;
74 #cooling-cells = <2>; /* min followed by max */
75 clock-latency = <40000>;
76 clocks = <&cru ARMCLK>;
77 dynamic-power-coefficient = <370>;
78 };
79 cpu2: cpu@502 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a12";
82 reg = <0x502>;
83 resets = <&cru SRST_CORE2>;
84 operating-points-v2 = <&cpu_opp_table>;
85 #cooling-cells = <2>; /* min followed by max */
86 clock-latency = <40000>;
87 clocks = <&cru ARMCLK>;
88 dynamic-power-coefficient = <370>;
89 };
90 cpu3: cpu@503 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a12";
93 reg = <0x503>;
94 resets = <&cru SRST_CORE3>;
95 operating-points-v2 = <&cpu_opp_table>;
96 #cooling-cells = <2>; /* min followed by max */
97 clock-latency = <40000>;
98 clocks = <&cru ARMCLK>;
99 dynamic-power-coefficient = <370>;
100 };
101 };
102
103 cpu_opp_table: cpu-opp-table {
104 compatible = "operating-points-v2";
105 opp-shared;
106
107 opp-126000000 {
108 opp-hz = /bits/ 64 <126000000>;
109 opp-microvolt = <900000>;
110 };
111 opp-216000000 {
112 opp-hz = /bits/ 64 <216000000>;
113 opp-microvolt = <900000>;
114 };
115 opp-312000000 {
116 opp-hz = /bits/ 64 <312000000>;
117 opp-microvolt = <900000>;
118 };
119 opp-408000000 {
120 opp-hz = /bits/ 64 <408000000>;
121 opp-microvolt = <900000>;
122 };
123 opp-600000000 {
124 opp-hz = /bits/ 64 <600000000>;
125 opp-microvolt = <900000>;
126 };
127 opp-696000000 {
128 opp-hz = /bits/ 64 <696000000>;
129 opp-microvolt = <950000>;
130 };
131 opp-816000000 {
132 opp-hz = /bits/ 64 <816000000>;
133 opp-microvolt = <1000000>;
134 };
135 opp-1008000000 {
136 opp-hz = /bits/ 64 <1008000000>;
137 opp-microvolt = <1050000>;
138 };
139 opp-1200000000 {
140 opp-hz = /bits/ 64 <1200000000>;
141 opp-microvolt = <1100000>;
142 };
143 opp-1416000000 {
144 opp-hz = /bits/ 64 <1416000000>;
145 opp-microvolt = <1200000>;
146 };
147 opp-1512000000 {
148 opp-hz = /bits/ 64 <1512000000>;
149 opp-microvolt = <1300000>;
150 };
151 opp-1608000000 {
152 opp-hz = /bits/ 64 <1608000000>;
153 opp-microvolt = <1350000>;
154 };
155 };
156
157 amba: bus {
158 compatible = "simple-bus";
159 #address-cells = <2>;
160 #size-cells = <2>;
161 ranges;
162
163 dmac_peri: dma-controller@ff250000 {
164 compatible = "arm,pl330", "arm,primecell";
165 reg = <0x0 0xff250000 0x0 0x4000>;
166 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
168 #dma-cells = <1>;
169 arm,pl330-broken-no-flushp;
170 arm,pl330-periph-burst;
171 clocks = <&cru ACLK_DMAC2>;
172 clock-names = "apb_pclk";
173 };
174
175 dmac_bus_ns: dma-controller@ff600000 {
176 compatible = "arm,pl330", "arm,primecell";
177 reg = <0x0 0xff600000 0x0 0x4000>;
178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
180 #dma-cells = <1>;
181 arm,pl330-broken-no-flushp;
182 arm,pl330-periph-burst;
183 clocks = <&cru ACLK_DMAC1>;
184 clock-names = "apb_pclk";
185 status = "disabled";
186 };
187
188 dmac_bus_s: dma-controller@ffb20000 {
189 compatible = "arm,pl330", "arm,primecell";
190 reg = <0x0 0xffb20000 0x0 0x4000>;
191 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
193 #dma-cells = <1>;
194 arm,pl330-broken-no-flushp;
195 arm,pl330-periph-burst;
196 clocks = <&cru ACLK_DMAC1>;
197 clock-names = "apb_pclk";
198 };
199 };
200
201 reserved-memory {
202 #address-cells = <2>;
203 #size-cells = <2>;
204 ranges;
205
206 /*
207 * The rk3288 cannot use the memory area above 0xfe000000
208 * for dma operations for some reason. While there is
209 * probably a better solution available somewhere, we
210 * haven't found it yet and while devices with 2GB of ram
211 * are not affected, this issue prevents 4GB from booting.
212 * So to make these devices at least bootable, block
213 * this area for the time being until the real solution
214 * is found.
215 */
216 dma-unusable@fe000000 {
217 reg = <0x0 0xfe000000 0x0 0x1000000>;
218 };
219 };
220
221 xin24m: oscillator {
222 compatible = "fixed-clock";
223 clock-frequency = <24000000>;
224 clock-output-names = "xin24m";
225 #clock-cells = <0>;
226 };
227
228 timer {
229 compatible = "arm,armv7-timer";
230 arm,cpu-registers-not-fw-configured;
231 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
232 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
233 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
234 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
235 clock-frequency = <24000000>;
236 arm,no-tick-in-suspend;
237 };
238
239 timer: timer@ff810000 {
240 compatible = "rockchip,rk3288-timer";
241 reg = <0x0 0xff810000 0x0 0x20>;
242 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&xin24m>, <&cru PCLK_TIMER>;
244 clock-names = "timer", "pclk";
245 };
246
247 display-subsystem {
248 compatible = "rockchip,display-subsystem";
249 ports = <&vopl_out>, <&vopb_out>;
250 };
251
252 sdmmc: mmc@ff0c0000 {
253 compatible = "rockchip,rk3288-dw-mshc";
254 max-frequency = <150000000>;
255 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
256 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
257 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
258 fifo-depth = <0x100>;
259 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
260 reg = <0x0 0xff0c0000 0x0 0x4000>;
261 resets = <&cru SRST_MMC0>;
262 reset-names = "reset";
263 status = "disabled";
264 };
265
266 sdio0: mmc@ff0d0000 {
267 compatible = "rockchip,rk3288-dw-mshc";
268 max-frequency = <150000000>;
269 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
270 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
271 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
272 fifo-depth = <0x100>;
273 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
274 reg = <0x0 0xff0d0000 0x0 0x4000>;
275 resets = <&cru SRST_SDIO0>;
276 reset-names = "reset";
277 status = "disabled";
278 };
279
280 sdio1: mmc@ff0e0000 {
281 compatible = "rockchip,rk3288-dw-mshc";
282 max-frequency = <150000000>;
283 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
284 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
285 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
286 fifo-depth = <0x100>;
287 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
288 reg = <0x0 0xff0e0000 0x0 0x4000>;
289 resets = <&cru SRST_SDIO1>;
290 reset-names = "reset";
291 status = "disabled";
292 };
293
294 emmc: mmc@ff0f0000 {
295 compatible = "rockchip,rk3288-dw-mshc";
296 max-frequency = <150000000>;
297 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
298 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
299 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
300 fifo-depth = <0x100>;
301 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
302 reg = <0x0 0xff0f0000 0x0 0x4000>;
303 resets = <&cru SRST_EMMC>;
304 reset-names = "reset";
305 status = "disabled";
306 };
307
308 saradc: saradc@ff100000 {
309 compatible = "rockchip,saradc";
310 reg = <0x0 0xff100000 0x0 0x100>;
311 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
312 #io-channel-cells = <1>;
313 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
314 clock-names = "saradc", "apb_pclk";
315 resets = <&cru SRST_SARADC>;
316 reset-names = "saradc-apb";
317 status = "disabled";
318 };
319
320 spi0: spi@ff110000 {
321 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
322 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
323 clock-names = "spiclk", "apb_pclk";
324 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
325 dma-names = "tx", "rx";
326 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
329 reg = <0x0 0xff110000 0x0 0x1000>;
330 #address-cells = <1>;
331 #size-cells = <0>;
332 status = "disabled";
333 };
334
335 spi1: spi@ff120000 {
336 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
337 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
338 clock-names = "spiclk", "apb_pclk";
339 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
340 dma-names = "tx", "rx";
341 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
344 reg = <0x0 0xff120000 0x0 0x1000>;
345 #address-cells = <1>;
346 #size-cells = <0>;
347 status = "disabled";
348 };
349
350 spi2: spi@ff130000 {
351 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
352 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
353 clock-names = "spiclk", "apb_pclk";
354 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
355 dma-names = "tx", "rx";
356 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
359 reg = <0x0 0xff130000 0x0 0x1000>;
360 #address-cells = <1>;
361 #size-cells = <0>;
362 status = "disabled";
363 };
364
365 i2c1: i2c@ff140000 {
366 compatible = "rockchip,rk3288-i2c";
367 reg = <0x0 0xff140000 0x0 0x1000>;
368 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
369 #address-cells = <1>;
370 #size-cells = <0>;
371 clock-names = "i2c";
372 clocks = <&cru PCLK_I2C1>;
373 pinctrl-names = "default";
374 pinctrl-0 = <&i2c1_xfer>;
375 status = "disabled";
376 };
377
378 i2c3: i2c@ff150000 {
379 compatible = "rockchip,rk3288-i2c";
380 reg = <0x0 0xff150000 0x0 0x1000>;
381 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
382 #address-cells = <1>;
383 #size-cells = <0>;
384 clock-names = "i2c";
385 clocks = <&cru PCLK_I2C3>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&i2c3_xfer>;
388 status = "disabled";
389 };
390
391 i2c4: i2c@ff160000 {
392 compatible = "rockchip,rk3288-i2c";
393 reg = <0x0 0xff160000 0x0 0x1000>;
394 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
395 #address-cells = <1>;
396 #size-cells = <0>;
397 clock-names = "i2c";
398 clocks = <&cru PCLK_I2C4>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&i2c4_xfer>;
401 status = "disabled";
402 };
403
404 i2c5: i2c@ff170000 {
405 compatible = "rockchip,rk3288-i2c";
406 reg = <0x0 0xff170000 0x0 0x1000>;
407 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
408 #address-cells = <1>;
409 #size-cells = <0>;
410 clock-names = "i2c";
411 clocks = <&cru PCLK_I2C5>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&i2c5_xfer>;
414 status = "disabled";
415 };
416
417 uart0: serial@ff180000 {
418 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
419 reg = <0x0 0xff180000 0x0 0x100>;
420 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
421 reg-shift = <2>;
422 reg-io-width = <4>;
423 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
424 clock-names = "baudclk", "apb_pclk";
425 dmas = <&dmac_peri 1>, <&dmac_peri 2>;
426 dma-names = "tx", "rx";
427 pinctrl-names = "default";
428 pinctrl-0 = <&uart0_xfer>;
429 status = "disabled";
430 };
431
432 uart1: serial@ff190000 {
433 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
434 reg = <0x0 0xff190000 0x0 0x100>;
435 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
436 reg-shift = <2>;
437 reg-io-width = <4>;
438 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
439 clock-names = "baudclk", "apb_pclk";
440 dmas = <&dmac_peri 3>, <&dmac_peri 4>;
441 dma-names = "tx", "rx";
442 pinctrl-names = "default";
443 pinctrl-0 = <&uart1_xfer>;
444 status = "disabled";
445 };
446
447 uart2: serial@ff690000 {
448 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
449 reg = <0x0 0xff690000 0x0 0x100>;
450 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
451 reg-shift = <2>;
452 reg-io-width = <4>;
453 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
454 clock-names = "baudclk", "apb_pclk";
455 pinctrl-names = "default";
456 pinctrl-0 = <&uart2_xfer>;
457 status = "disabled";
458 };
459
460 uart3: serial@ff1b0000 {
461 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
462 reg = <0x0 0xff1b0000 0x0 0x100>;
463 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
464 reg-shift = <2>;
465 reg-io-width = <4>;
466 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
467 clock-names = "baudclk", "apb_pclk";
468 dmas = <&dmac_peri 7>, <&dmac_peri 8>;
469 dma-names = "tx", "rx";
470 pinctrl-names = "default";
471 pinctrl-0 = <&uart3_xfer>;
472 status = "disabled";
473 };
474
475 uart4: serial@ff1c0000 {
476 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
477 reg = <0x0 0xff1c0000 0x0 0x100>;
478 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
479 reg-shift = <2>;
480 reg-io-width = <4>;
481 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
482 clock-names = "baudclk", "apb_pclk";
483 dmas = <&dmac_peri 9>, <&dmac_peri 10>;
484 dma-names = "tx", "rx";
485 pinctrl-names = "default";
486 pinctrl-0 = <&uart4_xfer>;
487 status = "disabled";
488 };
489
490 thermal-zones {
491 reserve_thermal: reserve_thermal {
492 polling-delay-passive = <1000>; /* milliseconds */
493 polling-delay = <5000>; /* milliseconds */
494
495 thermal-sensors = <&tsadc 0>;
496 };
497
498 cpu_thermal: cpu_thermal {
499 polling-delay-passive = <100>; /* milliseconds */
500 polling-delay = <5000>; /* milliseconds */
501
502 thermal-sensors = <&tsadc 1>;
503
504 trips {
505 cpu_alert0: cpu_alert0 {
506 temperature = <70000>; /* millicelsius */
507 hysteresis = <2000>; /* millicelsius */
508 type = "passive";
509 };
510 cpu_alert1: cpu_alert1 {
511 temperature = <75000>; /* millicelsius */
512 hysteresis = <2000>; /* millicelsius */
513 type = "passive";
514 };
515 cpu_crit: cpu_crit {
516 temperature = <90000>; /* millicelsius */
517 hysteresis = <2000>; /* millicelsius */
518 type = "critical";
519 };
520 };
521
522 cooling-maps {
523 map0 {
524 trip = <&cpu_alert0>;
525 cooling-device =
526 <&cpu0 THERMAL_NO_LIMIT 6>,
527 <&cpu1 THERMAL_NO_LIMIT 6>,
528 <&cpu2 THERMAL_NO_LIMIT 6>,
529 <&cpu3 THERMAL_NO_LIMIT 6>;
530 };
531 map1 {
532 trip = <&cpu_alert1>;
533 cooling-device =
534 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
535 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
536 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
537 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
538 };
539 };
540 };
541
542 gpu_thermal: gpu_thermal {
543 polling-delay-passive = <100>; /* milliseconds */
544 polling-delay = <5000>; /* milliseconds */
545
546 thermal-sensors = <&tsadc 2>;
547
548 trips {
549 gpu_alert0: gpu_alert0 {
550 temperature = <70000>; /* millicelsius */
551 hysteresis = <2000>; /* millicelsius */
552 type = "passive";
553 };
554 gpu_crit: gpu_crit {
555 temperature = <90000>; /* millicelsius */
556 hysteresis = <2000>; /* millicelsius */
557 type = "critical";
558 };
559 };
560
561 cooling-maps {
562 map0 {
563 trip = <&gpu_alert0>;
564 cooling-device =
565 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
566 };
567 };
568 };
569 };
570
571 tsadc: tsadc@ff280000 {
572 compatible = "rockchip,rk3288-tsadc";
573 reg = <0x0 0xff280000 0x0 0x100>;
574 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
576 clock-names = "tsadc", "apb_pclk";
577 resets = <&cru SRST_TSADC>;
578 reset-names = "tsadc-apb";
579 pinctrl-names = "init", "default", "sleep";
580 pinctrl-0 = <&otp_pin>;
581 pinctrl-1 = <&otp_out>;
582 pinctrl-2 = <&otp_pin>;
583 #thermal-sensor-cells = <1>;
584 rockchip,grf = <&grf>;
585 rockchip,hw-tshut-temp = <95000>;
586 status = "disabled";
587 };
588
589 gmac: ethernet@ff290000 {
590 compatible = "rockchip,rk3288-gmac";
591 reg = <0x0 0xff290000 0x0 0x10000>;
592 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
594 interrupt-names = "macirq", "eth_wake_irq";
595 rockchip,grf = <&grf>;
596 clocks = <&cru SCLK_MAC>,
597 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
598 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
599 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
600 clock-names = "stmmaceth",
601 "mac_clk_rx", "mac_clk_tx",
602 "clk_mac_ref", "clk_mac_refout",
603 "aclk_mac", "pclk_mac";
604 resets = <&cru SRST_MAC>;
605 reset-names = "stmmaceth";
606 status = "disabled";
607 };
608
609 usb_host0_ehci: usb@ff500000 {
610 compatible = "generic-ehci";
611 reg = <0x0 0xff500000 0x0 0x100>;
612 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&cru HCLK_USBHOST0>;
614 phys = <&usbphy1>;
615 phy-names = "usb";
616 status = "disabled";
617 };
618
619 /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
620 usb_host0_ohci: usb@ff520000 {
621 compatible = "generic-ohci";
622 reg = <0x0 0xff520000 0x0 0x100>;
623 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&cru HCLK_USBHOST0>;
625 phys = <&usbphy1>;
626 phy-names = "usb";
627 status = "disabled";
628 };
629
630 usb_host1: usb@ff540000 {
631 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
632 "snps,dwc2";
633 reg = <0x0 0xff540000 0x0 0x40000>;
634 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&cru HCLK_USBHOST1>;
636 clock-names = "otg";
637 dr_mode = "host";
638 phys = <&usbphy2>;
639 phy-names = "usb2-phy";
640 snps,reset-phy-on-wake;
641 status = "disabled";
642 };
643
644 usb_otg: usb@ff580000 {
645 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
646 "snps,dwc2";
647 reg = <0x0 0xff580000 0x0 0x40000>;
648 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&cru HCLK_OTG0>;
650 clock-names = "otg";
651 dr_mode = "otg";
652 g-np-tx-fifo-size = <16>;
653 g-rx-fifo-size = <275>;
654 g-tx-fifo-size = <256 128 128 64 64 32>;
655 phys = <&usbphy0>;
656 phy-names = "usb2-phy";
657 status = "disabled";
658 };
659
660 usb_hsic: usb@ff5c0000 {
661 compatible = "generic-ehci";
662 reg = <0x0 0xff5c0000 0x0 0x100>;
663 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&cru HCLK_HSIC>;
665 status = "disabled";
666 };
667
668 i2c0: i2c@ff650000 {
669 compatible = "rockchip,rk3288-i2c";
670 reg = <0x0 0xff650000 0x0 0x1000>;
671 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
672 #address-cells = <1>;
673 #size-cells = <0>;
674 clock-names = "i2c";
675 clocks = <&cru PCLK_I2C0>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&i2c0_xfer>;
678 status = "disabled";
679 };
680
681 i2c2: i2c@ff660000 {
682 compatible = "rockchip,rk3288-i2c";
683 reg = <0x0 0xff660000 0x0 0x1000>;
684 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
685 #address-cells = <1>;
686 #size-cells = <0>;
687 clock-names = "i2c";
688 clocks = <&cru PCLK_I2C2>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&i2c2_xfer>;
691 status = "disabled";
692 };
693
694 pwm0: pwm@ff680000 {
695 compatible = "rockchip,rk3288-pwm";
696 reg = <0x0 0xff680000 0x0 0x10>;
697 #pwm-cells = <3>;
698 pinctrl-names = "default";
699 pinctrl-0 = <&pwm0_pin>;
700 clocks = <&cru PCLK_RKPWM>;
701 clock-names = "pwm";
702 status = "disabled";
703 };
704
705 pwm1: pwm@ff680010 {
706 compatible = "rockchip,rk3288-pwm";
707 reg = <0x0 0xff680010 0x0 0x10>;
708 #pwm-cells = <3>;
709 pinctrl-names = "default";
710 pinctrl-0 = <&pwm1_pin>;
711 clocks = <&cru PCLK_RKPWM>;
712 clock-names = "pwm";
713 status = "disabled";
714 };
715
716 pwm2: pwm@ff680020 {
717 compatible = "rockchip,rk3288-pwm";
718 reg = <0x0 0xff680020 0x0 0x10>;
719 #pwm-cells = <3>;
720 pinctrl-names = "default";
721 pinctrl-0 = <&pwm2_pin>;
722 clocks = <&cru PCLK_RKPWM>;
723 clock-names = "pwm";
724 status = "disabled";
725 };
726
727 pwm3: pwm@ff680030 {
728 compatible = "rockchip,rk3288-pwm";
729 reg = <0x0 0xff680030 0x0 0x10>;
730 #pwm-cells = <3>;
731 pinctrl-names = "default";
732 pinctrl-0 = <&pwm3_pin>;
733 clocks = <&cru PCLK_RKPWM>;
734 clock-names = "pwm";
735 status = "disabled";
736 };
737
738 bus_intmem: sram@ff700000 {
739 compatible = "mmio-sram";
740 reg = <0x0 0xff700000 0x0 0x18000>;
741 #address-cells = <1>;
742 #size-cells = <1>;
743 ranges = <0 0x0 0xff700000 0x18000>;
744 smp-sram@0 {
745 compatible = "rockchip,rk3066-smp-sram";
746 reg = <0x00 0x10>;
747 };
748 };
749
750 pmu_sram: sram@ff720000 {
751 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
752 reg = <0x0 0xff720000 0x0 0x1000>;
753 };
754
755 pmu: power-management@ff730000 {
756 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
757 reg = <0x0 0xff730000 0x0 0x100>;
758
759 power: power-controller {
760 compatible = "rockchip,rk3288-power-controller";
761 #power-domain-cells = <1>;
762 #address-cells = <1>;
763 #size-cells = <0>;
764
765 assigned-clocks = <&cru SCLK_EDP_24M>;
766 assigned-clock-parents = <&xin24m>;
767
768 /*
769 * Note: Although SCLK_* are the working clocks
770 * of device without including on the NOC, needed for
771 * synchronous reset.
772 *
773 * The clocks on the which NOC:
774 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
775 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
776 * ACLK_RGA is on ACLK_RGA_NIU.
777 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
778 *
779 * Which clock are device clocks:
780 * clocks devices
781 * *_IEP IEP:Image Enhancement Processor
782 * *_ISP ISP:Image Signal Processing
783 * *_VIP VIP:Video Input Processor
784 * *_VOP* VOP:Visual Output Processor
785 * *_RGA RGA
786 * *_EDP* EDP
787 * *_LVDS_* LVDS
788 * *_HDMI HDMI
789 * *_MIPI_* MIPI
790 */
791 pd_vio@RK3288_PD_VIO {
792 reg = <RK3288_PD_VIO>;
793 clocks = <&cru ACLK_IEP>,
794 <&cru ACLK_ISP>,
795 <&cru ACLK_RGA>,
796 <&cru ACLK_VIP>,
797 <&cru ACLK_VOP0>,
798 <&cru ACLK_VOP1>,
799 <&cru DCLK_VOP0>,
800 <&cru DCLK_VOP1>,
801 <&cru HCLK_IEP>,
802 <&cru HCLK_ISP>,
803 <&cru HCLK_RGA>,
804 <&cru HCLK_VIP>,
805 <&cru HCLK_VOP0>,
806 <&cru HCLK_VOP1>,
807 <&cru PCLK_EDP_CTRL>,
808 <&cru PCLK_HDMI_CTRL>,
809 <&cru PCLK_LVDS_PHY>,
810 <&cru PCLK_MIPI_CSI>,
811 <&cru PCLK_MIPI_DSI0>,
812 <&cru PCLK_MIPI_DSI1>,
813 <&cru SCLK_EDP_24M>,
814 <&cru SCLK_EDP>,
815 <&cru SCLK_ISP_JPE>,
816 <&cru SCLK_ISP>,
817 <&cru SCLK_RGA>;
818 pm_qos = <&qos_vio0_iep>,
819 <&qos_vio1_vop>,
820 <&qos_vio1_isp_w0>,
821 <&qos_vio1_isp_w1>,
822 <&qos_vio0_vop>,
823 <&qos_vio0_vip>,
824 <&qos_vio2_rga_r>,
825 <&qos_vio2_rga_w>,
826 <&qos_vio1_isp_r>;
827 };
828
829 /*
830 * Note: The following 3 are HEVC(H.265) clocks,
831 * and on the ACLK_HEVC_NIU (NOC).
832 */
833 pd_hevc@RK3288_PD_HEVC {
834 reg = <RK3288_PD_HEVC>;
835 clocks = <&cru ACLK_HEVC>,
836 <&cru SCLK_HEVC_CABAC>,
837 <&cru SCLK_HEVC_CORE>;
838 pm_qos = <&qos_hevc_r>,
839 <&qos_hevc_w>;
840 };
841
842 /*
843 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
844 * (video endecoder & decoder) clocks that on the
845 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
846 */
847 pd_video@RK3288_PD_VIDEO {
848 reg = <RK3288_PD_VIDEO>;
849 clocks = <&cru ACLK_VCODEC>,
850 <&cru HCLK_VCODEC>;
851 pm_qos = <&qos_video>;
852 };
853
854 /*
855 * Note: ACLK_GPU is the GPU clock,
856 * and on the ACLK_GPU_NIU (NOC).
857 */
858 pd_gpu@RK3288_PD_GPU {
859 reg = <RK3288_PD_GPU>;
860 clocks = <&cru ACLK_GPU>;
861 pm_qos = <&qos_gpu_r>,
862 <&qos_gpu_w>;
863 };
864 };
865
866 reboot-mode {
867 compatible = "syscon-reboot-mode";
868 offset = <0x94>;
869 mode-normal = <BOOT_NORMAL>;
870 mode-recovery = <BOOT_RECOVERY>;
871 mode-bootloader = <BOOT_FASTBOOT>;
872 mode-loader = <BOOT_BL_DOWNLOAD>;
873 };
874 };
875
876 sgrf: syscon@ff740000 {
877 compatible = "rockchip,rk3288-sgrf", "syscon";
878 reg = <0x0 0xff740000 0x0 0x1000>;
879 };
880
881 cru: clock-controller@ff760000 {
882 compatible = "rockchip,rk3288-cru";
883 reg = <0x0 0xff760000 0x0 0x1000>;
884 rockchip,grf = <&grf>;
885 #clock-cells = <1>;
886 #reset-cells = <1>;
887 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
888 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
889 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
890 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
891 <&cru PCLK_PERI>;
892 assigned-clock-rates = <594000000>, <400000000>,
893 <500000000>, <300000000>,
894 <150000000>, <75000000>,
895 <300000000>, <150000000>,
896 <75000000>;
897 };
898
899 grf: syscon@ff770000 {
900 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
901 reg = <0x0 0xff770000 0x0 0x1000>;
902
903 edp_phy: edp-phy {
904 compatible = "rockchip,rk3288-dp-phy";
905 clocks = <&cru SCLK_EDP_24M>;
906 clock-names = "24m";
907 #phy-cells = <0>;
908 status = "disabled";
909 };
910
911 io_domains: io-domains {
912 compatible = "rockchip,rk3288-io-voltage-domain";
913 status = "disabled";
914 };
915
916 usbphy: usbphy {
917 compatible = "rockchip,rk3288-usb-phy";
918 #address-cells = <1>;
919 #size-cells = <0>;
920 status = "disabled";
921
922 usbphy0: usb-phy@320 {
923 #phy-cells = <0>;
924 reg = <0x320>;
925 clocks = <&cru SCLK_OTGPHY0>;
926 clock-names = "phyclk";
927 #clock-cells = <0>;
928 resets = <&cru SRST_USBOTG_PHY>;
929 reset-names = "phy-reset";
930 };
931
932 usbphy1: usb-phy@334 {
933 #phy-cells = <0>;
934 reg = <0x334>;
935 clocks = <&cru SCLK_OTGPHY1>;
936 clock-names = "phyclk";
937 #clock-cells = <0>;
938 resets = <&cru SRST_USBHOST0_PHY>;
939 reset-names = "phy-reset";
940 };
941
942 usbphy2: usb-phy@348 {
943 #phy-cells = <0>;
944 reg = <0x348>;
945 clocks = <&cru SCLK_OTGPHY2>;
946 clock-names = "phyclk";
947 #clock-cells = <0>;
948 resets = <&cru SRST_USBHOST1_PHY>;
949 reset-names = "phy-reset";
950 };
951 };
952 };
953
954 wdt: watchdog@ff800000 {
955 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
956 reg = <0x0 0xff800000 0x0 0x100>;
957 clocks = <&cru PCLK_WDT>;
958 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
959 status = "disabled";
960 };
961
962 spdif: sound@ff88b0000 {
963 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
964 reg = <0x0 0xff8b0000 0x0 0x10000>;
965 #sound-dai-cells = <0>;
966 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
967 clock-names = "mclk", "hclk";
968 dmas = <&dmac_bus_s 3>;
969 dma-names = "tx";
970 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
971 pinctrl-names = "default";
972 pinctrl-0 = <&spdif_tx>;
973 rockchip,grf = <&grf>;
974 status = "disabled";
975 };
976
977 i2s: i2s@ff890000 {
978 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
979 reg = <0x0 0xff890000 0x0 0x10000>;
980 #sound-dai-cells = <0>;
981 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
983 clock-names = "i2s_clk", "i2s_hclk";
984 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
985 dma-names = "tx", "rx";
986 pinctrl-names = "default";
987 pinctrl-0 = <&i2s0_bus>;
988 rockchip,playback-channels = <8>;
989 rockchip,capture-channels = <2>;
990 status = "disabled";
991 };
992
993 crypto: cypto-controller@ff8a0000 {
994 compatible = "rockchip,rk3288-crypto";
995 reg = <0x0 0xff8a0000 0x0 0x4000>;
996 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
998 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
999 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
1000 resets = <&cru SRST_CRYPTO>;
1001 reset-names = "crypto-rst";
1002 status = "okay";
1003 };
1004
1005 iep_mmu: iommu@ff900800 {
1006 compatible = "rockchip,iommu";
1007 reg = <0x0 0xff900800 0x0 0x40>;
1008 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1009 interrupt-names = "iep_mmu";
1010 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1011 clock-names = "aclk", "iface";
1012 #iommu-cells = <0>;
1013 status = "disabled";
1014 };
1015
1016 isp_mmu: iommu@ff914000 {
1017 compatible = "rockchip,iommu";
1018 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1019 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1020 interrupt-names = "isp_mmu";
1021 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1022 clock-names = "aclk", "iface";
1023 #iommu-cells = <0>;
1024 rockchip,disable-mmu-reset;
1025 status = "disabled";
1026 };
1027
1028 rga: rga@ff920000 {
1029 compatible = "rockchip,rk3288-rga";
1030 reg = <0x0 0xff920000 0x0 0x180>;
1031 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1033 clock-names = "aclk", "hclk", "sclk";
1034 power-domains = <&power RK3288_PD_VIO>;
1035 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1036 reset-names = "core", "axi", "ahb";
1037 };
1038
1039 vopb: vop@ff930000 {
1040 compatible = "rockchip,rk3288-vop";
1041 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
1042 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1043 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1044 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1045 power-domains = <&power RK3288_PD_VIO>;
1046 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1047 reset-names = "axi", "ahb", "dclk";
1048 iommus = <&vopb_mmu>;
1049 status = "disabled";
1050
1051 vopb_out: port {
1052 #address-cells = <1>;
1053 #size-cells = <0>;
1054
1055 vopb_out_hdmi: endpoint@0 {
1056 reg = <0>;
1057 remote-endpoint = <&hdmi_in_vopb>;
1058 };
1059
1060 vopb_out_edp: endpoint@1 {
1061 reg = <1>;
1062 remote-endpoint = <&edp_in_vopb>;
1063 };
1064
1065 vopb_out_mipi: endpoint@2 {
1066 reg = <2>;
1067 remote-endpoint = <&mipi_in_vopb>;
1068 };
1069
1070 vopb_out_lvds: endpoint@3 {
1071 reg = <3>;
1072 remote-endpoint = <&lvds_in_vopb>;
1073 };
1074 };
1075 };
1076
1077 vopb_mmu: iommu@ff930300 {
1078 compatible = "rockchip,iommu";
1079 reg = <0x0 0xff930300 0x0 0x100>;
1080 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1081 interrupt-names = "vopb_mmu";
1082 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1083 clock-names = "aclk", "iface";
1084 power-domains = <&power RK3288_PD_VIO>;
1085 #iommu-cells = <0>;
1086 status = "disabled";
1087 };
1088
1089 vopl: vop@ff940000 {
1090 compatible = "rockchip,rk3288-vop";
1091 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
1092 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1094 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1095 power-domains = <&power RK3288_PD_VIO>;
1096 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1097 reset-names = "axi", "ahb", "dclk";
1098 iommus = <&vopl_mmu>;
1099 status = "disabled";
1100
1101 vopl_out: port {
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1104
1105 vopl_out_hdmi: endpoint@0 {
1106 reg = <0>;
1107 remote-endpoint = <&hdmi_in_vopl>;
1108 };
1109
1110 vopl_out_edp: endpoint@1 {
1111 reg = <1>;
1112 remote-endpoint = <&edp_in_vopl>;
1113 };
1114
1115 vopl_out_mipi: endpoint@2 {
1116 reg = <2>;
1117 remote-endpoint = <&mipi_in_vopl>;
1118 };
1119
1120 vopl_out_lvds: endpoint@3 {
1121 reg = <3>;
1122 remote-endpoint = <&lvds_in_vopl>;
1123 };
1124 };
1125 };
1126
1127 vopl_mmu: iommu@ff940300 {
1128 compatible = "rockchip,iommu";
1129 reg = <0x0 0xff940300 0x0 0x100>;
1130 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1131 interrupt-names = "vopl_mmu";
1132 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1133 clock-names = "aclk", "iface";
1134 power-domains = <&power RK3288_PD_VIO>;
1135 #iommu-cells = <0>;
1136 status = "disabled";
1137 };
1138
1139 mipi_dsi: mipi@ff960000 {
1140 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1141 reg = <0x0 0xff960000 0x0 0x4000>;
1142 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1144 clock-names = "ref", "pclk";
1145 power-domains = <&power RK3288_PD_VIO>;
1146 rockchip,grf = <&grf>;
1147 status = "disabled";
1148
1149 ports {
1150 mipi_in: port {
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1153 mipi_in_vopb: endpoint@0 {
1154 reg = <0>;
1155 remote-endpoint = <&vopb_out_mipi>;
1156 };
1157 mipi_in_vopl: endpoint@1 {
1158 reg = <1>;
1159 remote-endpoint = <&vopl_out_mipi>;
1160 };
1161 };
1162 };
1163 };
1164
1165 lvds: lvds@ff96c000 {
1166 compatible = "rockchip,rk3288-lvds";
1167 reg = <0x0 0xff96c000 0x0 0x4000>;
1168 clocks = <&cru PCLK_LVDS_PHY>;
1169 clock-names = "pclk_lvds";
1170 pinctrl-names = "lcdc";
1171 pinctrl-0 = <&lcdc_ctl>;
1172 power-domains = <&power RK3288_PD_VIO>;
1173 rockchip,grf = <&grf>;
1174 status = "disabled";
1175
1176 ports {
1177 #address-cells = <1>;
1178 #size-cells = <0>;
1179
1180 lvds_in: port@0 {
1181 reg = <0>;
1182
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1185
1186 lvds_in_vopb: endpoint@0 {
1187 reg = <0>;
1188 remote-endpoint = <&vopb_out_lvds>;
1189 };
1190 lvds_in_vopl: endpoint@1 {
1191 reg = <1>;
1192 remote-endpoint = <&vopl_out_lvds>;
1193 };
1194 };
1195 };
1196 };
1197
1198 edp: dp@ff970000 {
1199 compatible = "rockchip,rk3288-dp";
1200 reg = <0x0 0xff970000 0x0 0x4000>;
1201 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1202 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1203 clock-names = "dp", "pclk";
1204 phys = <&edp_phy>;
1205 phy-names = "dp";
1206 resets = <&cru SRST_EDP>;
1207 reset-names = "dp";
1208 rockchip,grf = <&grf>;
1209 status = "disabled";
1210
1211 ports {
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1214 edp_in: port@0 {
1215 reg = <0>;
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1218 edp_in_vopb: endpoint@0 {
1219 reg = <0>;
1220 remote-endpoint = <&vopb_out_edp>;
1221 };
1222 edp_in_vopl: endpoint@1 {
1223 reg = <1>;
1224 remote-endpoint = <&vopl_out_edp>;
1225 };
1226 };
1227 };
1228 };
1229
1230 hdmi: hdmi@ff980000 {
1231 compatible = "rockchip,rk3288-dw-hdmi";
1232 reg = <0x0 0xff980000 0x0 0x20000>;
1233 reg-io-width = <4>;
1234 #sound-dai-cells = <0>;
1235 rockchip,grf = <&grf>;
1236 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1237 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1238 clock-names = "iahb", "isfr", "cec";
1239 power-domains = <&power RK3288_PD_VIO>;
1240 status = "disabled";
1241
1242 ports {
1243 hdmi_in: port {
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1246 hdmi_in_vopb: endpoint@0 {
1247 reg = <0>;
1248 remote-endpoint = <&vopb_out_hdmi>;
1249 };
1250 hdmi_in_vopl: endpoint@1 {
1251 reg = <1>;
1252 remote-endpoint = <&vopl_out_hdmi>;
1253 };
1254 };
1255 };
1256 };
1257
1258 vpu: video-codec@ff9a0000 {
1259 compatible = "rockchip,rk3288-vpu";
1260 reg = <0x0 0xff9a0000 0x0 0x800>;
1261 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1263 interrupt-names = "vepu", "vdpu";
1264 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1265 clock-names = "aclk", "hclk";
1266 iommus = <&vpu_mmu>;
1267 power-domains = <&power RK3288_PD_VIDEO>;
1268 };
1269
1270 vpu_mmu: iommu@ff9a0800 {
1271 compatible = "rockchip,iommu";
1272 reg = <0x0 0xff9a0800 0x0 0x100>;
1273 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1274 interrupt-names = "vpu_mmu";
1275 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1276 clock-names = "aclk", "iface";
1277 #iommu-cells = <0>;
1278 power-domains = <&power RK3288_PD_VIDEO>;
1279 };
1280
1281 hevc_mmu: iommu@ff9c0440 {
1282 compatible = "rockchip,iommu";
1283 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1284 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1285 interrupt-names = "hevc_mmu";
1286 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1287 clock-names = "aclk", "iface";
1288 #iommu-cells = <0>;
1289 status = "disabled";
1290 };
1291
1292 gpu: gpu@ffa30000 {
1293 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1294 reg = <0x0 0xffa30000 0x0 0x10000>;
1295 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1296 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1297 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1298 interrupt-names = "job", "mmu", "gpu";
1299 clocks = <&cru ACLK_GPU>;
1300 operating-points-v2 = <&gpu_opp_table>;
1301 #cooling-cells = <2>; /* min followed by max */
1302 power-domains = <&power RK3288_PD_GPU>;
1303 status = "disabled";
1304 };
1305
1306 gpu_opp_table: gpu-opp-table {
1307 compatible = "operating-points-v2";
1308
1309 opp-100000000 {
1310 opp-hz = /bits/ 64 <100000000>;
1311 opp-microvolt = <950000>;
1312 };
1313 opp-200000000 {
1314 opp-hz = /bits/ 64 <200000000>;
1315 opp-microvolt = <950000>;
1316 };
1317 opp-300000000 {
1318 opp-hz = /bits/ 64 <300000000>;
1319 opp-microvolt = <1000000>;
1320 };
1321 opp-400000000 {
1322 opp-hz = /bits/ 64 <400000000>;
1323 opp-microvolt = <1100000>;
1324 };
1325 opp-600000000 {
1326 opp-hz = /bits/ 64 <600000000>;
1327 opp-microvolt = <1250000>;
1328 };
1329 };
1330
1331 qos_gpu_r: qos@ffaa0000 {
1332 compatible = "syscon";
1333 reg = <0x0 0xffaa0000 0x0 0x20>;
1334 };
1335
1336 qos_gpu_w: qos@ffaa0080 {
1337 compatible = "syscon";
1338 reg = <0x0 0xffaa0080 0x0 0x20>;
1339 };
1340
1341 qos_vio1_vop: qos@ffad0000 {
1342 compatible = "syscon";
1343 reg = <0x0 0xffad0000 0x0 0x20>;
1344 };
1345
1346 qos_vio1_isp_w0: qos@ffad0100 {
1347 compatible = "syscon";
1348 reg = <0x0 0xffad0100 0x0 0x20>;
1349 };
1350
1351 qos_vio1_isp_w1: qos@ffad0180 {
1352 compatible = "syscon";
1353 reg = <0x0 0xffad0180 0x0 0x20>;
1354 };
1355
1356 qos_vio0_vop: qos@ffad0400 {
1357 compatible = "syscon";
1358 reg = <0x0 0xffad0400 0x0 0x20>;
1359 };
1360
1361 qos_vio0_vip: qos@ffad0480 {
1362 compatible = "syscon";
1363 reg = <0x0 0xffad0480 0x0 0x20>;
1364 };
1365
1366 qos_vio0_iep: qos@ffad0500 {
1367 compatible = "syscon";
1368 reg = <0x0 0xffad0500 0x0 0x20>;
1369 };
1370
1371 qos_vio2_rga_r: qos@ffad0800 {
1372 compatible = "syscon";
1373 reg = <0x0 0xffad0800 0x0 0x20>;
1374 };
1375
1376 qos_vio2_rga_w: qos@ffad0880 {
1377 compatible = "syscon";
1378 reg = <0x0 0xffad0880 0x0 0x20>;
1379 };
1380
1381 qos_vio1_isp_r: qos@ffad0900 {
1382 compatible = "syscon";
1383 reg = <0x0 0xffad0900 0x0 0x20>;
1384 };
1385
1386 qos_video: qos@ffae0000 {
1387 compatible = "syscon";
1388 reg = <0x0 0xffae0000 0x0 0x20>;
1389 };
1390
1391 qos_hevc_r: qos@ffaf0000 {
1392 compatible = "syscon";
1393 reg = <0x0 0xffaf0000 0x0 0x20>;
1394 };
1395
1396 qos_hevc_w: qos@ffaf0080 {
1397 compatible = "syscon";
1398 reg = <0x0 0xffaf0080 0x0 0x20>;
1399 };
1400
1401 efuse: efuse@ffb40000 {
1402 compatible = "rockchip,rk3288-efuse";
1403 reg = <0x0 0xffb40000 0x0 0x20>;
1404 #address-cells = <1>;
1405 #size-cells = <1>;
1406 clocks = <&cru PCLK_EFUSE256>;
1407 clock-names = "pclk_efuse";
1408
1409 cpu_id: cpu-id@7 {
1410 reg = <0x07 0x10>;
1411 };
1412 cpu_leakage: cpu_leakage@17 {
1413 reg = <0x17 0x1>;
1414 };
1415 };
1416
1417 gic: interrupt-controller@ffc01000 {
1418 compatible = "arm,gic-400";
1419 interrupt-controller;
1420 #interrupt-cells = <3>;
1421 #address-cells = <0>;
1422
1423 reg = <0x0 0xffc01000 0x0 0x1000>,
1424 <0x0 0xffc02000 0x0 0x2000>,
1425 <0x0 0xffc04000 0x0 0x2000>,
1426 <0x0 0xffc06000 0x0 0x2000>;
1427 interrupts = <GIC_PPI 9 0xf04>;
1428 };
1429
1430 pinctrl: pinctrl {
1431 compatible = "rockchip,rk3288-pinctrl";
1432 rockchip,grf = <&grf>;
1433 rockchip,pmu = <&pmu>;
1434 #address-cells = <2>;
1435 #size-cells = <2>;
1436 ranges;
1437
1438 gpio0: gpio0@ff750000 {
1439 compatible = "rockchip,gpio-bank";
1440 reg = <0x0 0xff750000 0x0 0x100>;
1441 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1442 clocks = <&cru PCLK_GPIO0>;
1443
1444 gpio-controller;
1445 #gpio-cells = <2>;
1446
1447 interrupt-controller;
1448 #interrupt-cells = <2>;
1449 };
1450
1451 gpio1: gpio1@ff780000 {
1452 compatible = "rockchip,gpio-bank";
1453 reg = <0x0 0xff780000 0x0 0x100>;
1454 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1455 clocks = <&cru PCLK_GPIO1>;
1456
1457 gpio-controller;
1458 #gpio-cells = <2>;
1459
1460 interrupt-controller;
1461 #interrupt-cells = <2>;
1462 };
1463
1464 gpio2: gpio2@ff790000 {
1465 compatible = "rockchip,gpio-bank";
1466 reg = <0x0 0xff790000 0x0 0x100>;
1467 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1468 clocks = <&cru PCLK_GPIO2>;
1469
1470 gpio-controller;
1471 #gpio-cells = <2>;
1472
1473 interrupt-controller;
1474 #interrupt-cells = <2>;
1475 };
1476
1477 gpio3: gpio3@ff7a0000 {
1478 compatible = "rockchip,gpio-bank";
1479 reg = <0x0 0xff7a0000 0x0 0x100>;
1480 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1481 clocks = <&cru PCLK_GPIO3>;
1482
1483 gpio-controller;
1484 #gpio-cells = <2>;
1485
1486 interrupt-controller;
1487 #interrupt-cells = <2>;
1488 };
1489
1490 gpio4: gpio4@ff7b0000 {
1491 compatible = "rockchip,gpio-bank";
1492 reg = <0x0 0xff7b0000 0x0 0x100>;
1493 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1494 clocks = <&cru PCLK_GPIO4>;
1495
1496 gpio-controller;
1497 #gpio-cells = <2>;
1498
1499 interrupt-controller;
1500 #interrupt-cells = <2>;
1501 };
1502
1503 gpio5: gpio5@ff7c0000 {
1504 compatible = "rockchip,gpio-bank";
1505 reg = <0x0 0xff7c0000 0x0 0x100>;
1506 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1507 clocks = <&cru PCLK_GPIO5>;
1508
1509 gpio-controller;
1510 #gpio-cells = <2>;
1511
1512 interrupt-controller;
1513 #interrupt-cells = <2>;
1514 };
1515
1516 gpio6: gpio6@ff7d0000 {
1517 compatible = "rockchip,gpio-bank";
1518 reg = <0x0 0xff7d0000 0x0 0x100>;
1519 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1520 clocks = <&cru PCLK_GPIO6>;
1521
1522 gpio-controller;
1523 #gpio-cells = <2>;
1524
1525 interrupt-controller;
1526 #interrupt-cells = <2>;
1527 };
1528
1529 gpio7: gpio7@ff7e0000 {
1530 compatible = "rockchip,gpio-bank";
1531 reg = <0x0 0xff7e0000 0x0 0x100>;
1532 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1533 clocks = <&cru PCLK_GPIO7>;
1534
1535 gpio-controller;
1536 #gpio-cells = <2>;
1537
1538 interrupt-controller;
1539 #interrupt-cells = <2>;
1540 };
1541
1542 gpio8: gpio8@ff7f0000 {
1543 compatible = "rockchip,gpio-bank";
1544 reg = <0x0 0xff7f0000 0x0 0x100>;
1545 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1546 clocks = <&cru PCLK_GPIO8>;
1547
1548 gpio-controller;
1549 #gpio-cells = <2>;
1550
1551 interrupt-controller;
1552 #interrupt-cells = <2>;
1553 };
1554
1555 hdmi {
1556 hdmi_cec_c0: hdmi-cec-c0 {
1557 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
1558 };
1559
1560 hdmi_cec_c7: hdmi-cec-c7 {
1561 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
1562 };
1563
1564 hdmi_ddc: hdmi-ddc {
1565 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
1566 <7 RK_PC4 2 &pcfg_pull_none>;
1567 };
1568
1569 hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1570 rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
1571 <7 RK_PC4 2 &pcfg_pull_none>;
1572 };
1573 };
1574
1575 pcfg_output_low: pcfg-output-low {
1576 output-low;
1577 };
1578
1579 pcfg_pull_up: pcfg-pull-up {
1580 bias-pull-up;
1581 };
1582
1583 pcfg_pull_down: pcfg-pull-down {
1584 bias-pull-down;
1585 };
1586
1587 pcfg_pull_none: pcfg-pull-none {
1588 bias-disable;
1589 };
1590
1591 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1592 bias-disable;
1593 drive-strength = <12>;
1594 };
1595
1596 sleep {
1597 global_pwroff: global-pwroff {
1598 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
1599 };
1600
1601 ddrio_pwroff: ddrio-pwroff {
1602 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
1603 };
1604
1605 ddr0_retention: ddr0-retention {
1606 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
1607 };
1608
1609 ddr1_retention: ddr1-retention {
1610 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
1611 };
1612 };
1613
1614 edp {
1615 edp_hpd: edp-hpd {
1616 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
1617 };
1618 };
1619
1620 i2c0 {
1621 i2c0_xfer: i2c0-xfer {
1622 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
1623 <0 RK_PC0 1 &pcfg_pull_none>;
1624 };
1625 };
1626
1627 i2c1 {
1628 i2c1_xfer: i2c1-xfer {
1629 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
1630 <8 RK_PA5 1 &pcfg_pull_none>;
1631 };
1632 };
1633
1634 i2c2 {
1635 i2c2_xfer: i2c2-xfer {
1636 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
1637 <6 RK_PB2 1 &pcfg_pull_none>;
1638 };
1639 };
1640
1641 i2c3 {
1642 i2c3_xfer: i2c3-xfer {
1643 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
1644 <2 RK_PC1 1 &pcfg_pull_none>;
1645 };
1646 };
1647
1648 i2c4 {
1649 i2c4_xfer: i2c4-xfer {
1650 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
1651 <7 RK_PC2 1 &pcfg_pull_none>;
1652 };
1653 };
1654
1655 i2c5 {
1656 i2c5_xfer: i2c5-xfer {
1657 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
1658 <7 RK_PC4 1 &pcfg_pull_none>;
1659 };
1660 };
1661
1662 i2s0 {
1663 i2s0_bus: i2s0-bus {
1664 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
1665 <6 RK_PA1 1 &pcfg_pull_none>,
1666 <6 RK_PA2 1 &pcfg_pull_none>,
1667 <6 RK_PA3 1 &pcfg_pull_none>,
1668 <6 RK_PA4 1 &pcfg_pull_none>,
1669 <6 RK_PB0 1 &pcfg_pull_none>;
1670 };
1671 };
1672
1673 lcdc {
1674 lcdc_ctl: lcdc-ctl {
1675 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1676 <1 RK_PD1 1 &pcfg_pull_none>,
1677 <1 RK_PD2 1 &pcfg_pull_none>,
1678 <1 RK_PD3 1 &pcfg_pull_none>;
1679 };
1680 };
1681
1682 sdmmc {
1683 sdmmc_clk: sdmmc-clk {
1684 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
1685 };
1686
1687 sdmmc_cmd: sdmmc-cmd {
1688 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
1689 };
1690
1691 sdmmc_cd: sdmmc-cd {
1692 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
1693 };
1694
1695 sdmmc_bus1: sdmmc-bus1 {
1696 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
1697 };
1698
1699 sdmmc_bus4: sdmmc-bus4 {
1700 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
1701 <6 RK_PC1 1 &pcfg_pull_up>,
1702 <6 RK_PC2 1 &pcfg_pull_up>,
1703 <6 RK_PC3 1 &pcfg_pull_up>;
1704 };
1705 };
1706
1707 sdio0 {
1708 sdio0_bus1: sdio0-bus1 {
1709 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
1710 };
1711
1712 sdio0_bus4: sdio0-bus4 {
1713 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
1714 <4 RK_PC5 1 &pcfg_pull_up>,
1715 <4 RK_PC6 1 &pcfg_pull_up>,
1716 <4 RK_PC7 1 &pcfg_pull_up>;
1717 };
1718
1719 sdio0_cmd: sdio0-cmd {
1720 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
1721 };
1722
1723 sdio0_clk: sdio0-clk {
1724 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
1725 };
1726
1727 sdio0_cd: sdio0-cd {
1728 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
1729 };
1730
1731 sdio0_wp: sdio0-wp {
1732 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
1733 };
1734
1735 sdio0_pwr: sdio0-pwr {
1736 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
1737 };
1738
1739 sdio0_bkpwr: sdio0-bkpwr {
1740 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
1741 };
1742
1743 sdio0_int: sdio0-int {
1744 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
1745 };
1746 };
1747
1748 sdio1 {
1749 sdio1_bus1: sdio1-bus1 {
1750 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
1751 };
1752
1753 sdio1_bus4: sdio1-bus4 {
1754 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
1755 <3 RK_PD1 4 &pcfg_pull_up>,
1756 <3 RK_PD2 4 &pcfg_pull_up>,
1757 <3 RK_PD3 4 &pcfg_pull_up>;
1758 };
1759
1760 sdio1_cd: sdio1-cd {
1761 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
1762 };
1763
1764 sdio1_wp: sdio1-wp {
1765 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
1766 };
1767
1768 sdio1_bkpwr: sdio1-bkpwr {
1769 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
1770 };
1771
1772 sdio1_int: sdio1-int {
1773 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
1774 };
1775
1776 sdio1_cmd: sdio1-cmd {
1777 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
1778 };
1779
1780 sdio1_clk: sdio1-clk {
1781 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
1782 };
1783
1784 sdio1_pwr: sdio1-pwr {
1785 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
1786 };
1787 };
1788
1789 emmc {
1790 emmc_clk: emmc-clk {
1791 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
1792 };
1793
1794 emmc_cmd: emmc-cmd {
1795 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
1796 };
1797
1798 emmc_pwr: emmc-pwr {
1799 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
1800 };
1801
1802 emmc_bus1: emmc-bus1 {
1803 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
1804 };
1805
1806 emmc_bus4: emmc-bus4 {
1807 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1808 <3 RK_PA1 2 &pcfg_pull_up>,
1809 <3 RK_PA2 2 &pcfg_pull_up>,
1810 <3 RK_PA3 2 &pcfg_pull_up>;
1811 };
1812
1813 emmc_bus8: emmc-bus8 {
1814 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1815 <3 RK_PA1 2 &pcfg_pull_up>,
1816 <3 RK_PA2 2 &pcfg_pull_up>,
1817 <3 RK_PA3 2 &pcfg_pull_up>,
1818 <3 RK_PA4 2 &pcfg_pull_up>,
1819 <3 RK_PA5 2 &pcfg_pull_up>,
1820 <3 RK_PA6 2 &pcfg_pull_up>,
1821 <3 RK_PA7 2 &pcfg_pull_up>;
1822 };
1823 };
1824
1825 spi0 {
1826 spi0_clk: spi0-clk {
1827 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
1828 };
1829 spi0_cs0: spi0-cs0 {
1830 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
1831 };
1832 spi0_tx: spi0-tx {
1833 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
1834 };
1835 spi0_rx: spi0-rx {
1836 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
1837 };
1838 spi0_cs1: spi0-cs1 {
1839 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
1840 };
1841 };
1842 spi1 {
1843 spi1_clk: spi1-clk {
1844 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
1845 };
1846 spi1_cs0: spi1-cs0 {
1847 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
1848 };
1849 spi1_rx: spi1-rx {
1850 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
1851 };
1852 spi1_tx: spi1-tx {
1853 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
1854 };
1855 };
1856
1857 spi2 {
1858 spi2_cs1: spi2-cs1 {
1859 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
1860 };
1861 spi2_clk: spi2-clk {
1862 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
1863 };
1864 spi2_cs0: spi2-cs0 {
1865 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
1866 };
1867 spi2_rx: spi2-rx {
1868 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
1869 };
1870 spi2_tx: spi2-tx {
1871 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
1872 };
1873 };
1874
1875 uart0 {
1876 uart0_xfer: uart0-xfer {
1877 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
1878 <4 RK_PC1 1 &pcfg_pull_none>;
1879 };
1880
1881 uart0_cts: uart0-cts {
1882 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
1883 };
1884
1885 uart0_rts: uart0-rts {
1886 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
1887 };
1888 };
1889
1890 uart1 {
1891 uart1_xfer: uart1-xfer {
1892 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
1893 <5 RK_PB1 1 &pcfg_pull_none>;
1894 };
1895
1896 uart1_cts: uart1-cts {
1897 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
1898 };
1899
1900 uart1_rts: uart1-rts {
1901 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
1902 };
1903 };
1904
1905 uart2 {
1906 uart2_xfer: uart2-xfer {
1907 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
1908 <7 RK_PC7 1 &pcfg_pull_none>;
1909 };
1910 /* no rts / cts for uart2 */
1911 };
1912
1913 uart3 {
1914 uart3_xfer: uart3-xfer {
1915 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
1916 <7 RK_PB0 1 &pcfg_pull_none>;
1917 };
1918
1919 uart3_cts: uart3-cts {
1920 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
1921 };
1922
1923 uart3_rts: uart3-rts {
1924 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
1925 };
1926 };
1927
1928 uart4 {
1929 uart4_xfer: uart4-xfer {
1930 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
1931 <5 RK_PB6 3 &pcfg_pull_none>;
1932 };
1933
1934 uart4_cts: uart4-cts {
1935 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
1936 };
1937
1938 uart4_rts: uart4-rts {
1939 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
1940 };
1941 };
1942
1943 tsadc {
1944 otp_pin: otp-pin {
1945 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1946 };
1947
1948 otp_out: otp-out {
1949 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
1950 };
1951 };
1952
1953 pwm0 {
1954 pwm0_pin: pwm0-pin {
1955 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
1956 };
1957 };
1958
1959 pwm1 {
1960 pwm1_pin: pwm1-pin {
1961 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
1962 };
1963 };
1964
1965 pwm2 {
1966 pwm2_pin: pwm2-pin {
1967 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
1968 };
1969 };
1970
1971 pwm3 {
1972 pwm3_pin: pwm3-pin {
1973 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
1974 };
1975 };
1976
1977 gmac {
1978 rgmii_pins: rgmii-pins {
1979 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1980 <3 RK_PD7 3 &pcfg_pull_none>,
1981 <3 RK_PD2 3 &pcfg_pull_none>,
1982 <3 RK_PD3 3 &pcfg_pull_none>,
1983 <3 RK_PD4 3 &pcfg_pull_none_12ma>,
1984 <3 RK_PD5 3 &pcfg_pull_none_12ma>,
1985 <3 RK_PD0 3 &pcfg_pull_none_12ma>,
1986 <3 RK_PD1 3 &pcfg_pull_none_12ma>,
1987 <4 RK_PA0 3 &pcfg_pull_none>,
1988 <4 RK_PA5 3 &pcfg_pull_none>,
1989 <4 RK_PA6 3 &pcfg_pull_none>,
1990 <4 RK_PB1 3 &pcfg_pull_none_12ma>,
1991 <4 RK_PA4 3 &pcfg_pull_none_12ma>,
1992 <4 RK_PA1 3 &pcfg_pull_none>,
1993 <4 RK_PA3 3 &pcfg_pull_none>;
1994 };
1995
1996 rmii_pins: rmii-pins {
1997 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1998 <3 RK_PD7 3 &pcfg_pull_none>,
1999 <3 RK_PD4 3 &pcfg_pull_none>,
2000 <3 RK_PD5 3 &pcfg_pull_none>,
2001 <4 RK_PA0 3 &pcfg_pull_none>,
2002 <4 RK_PA5 3 &pcfg_pull_none>,
2003 <4 RK_PA4 3 &pcfg_pull_none>,
2004 <4 RK_PA1 3 &pcfg_pull_none>,
2005 <4 RK_PA2 3 &pcfg_pull_none>,
2006 <4 RK_PA3 3 &pcfg_pull_none>;
2007 };
2008 };
2009
2010 spdif {
2011 spdif_tx: spdif-tx {
2012 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
2013 };
2014 };
2015 };
2016};