tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm QUSB2 phy controller
9
10maintainers:
11 - Manu Gautam <mgautam@codeaurora.org>
12
13description:
14 QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
15
16properties:
17 compatible:
18 oneOf:
19 - items:
20 - enum:
21 - qcom,ipq8074-qusb2-phy
22 - qcom,msm8996-qusb2-phy
23 - qcom,msm8998-qusb2-phy
24 - items:
25 - enum:
26 - qcom,sc7180-qusb2-phy
27 - qcom,sdm845-qusb2-phy
28 - const: qcom,qusb2-v2-phy
29 reg:
30 maxItems: 1
31
32 "#phy-cells":
33 const: 0
34
35 clocks:
36 minItems: 2
37 maxItems: 3
38 items:
39 - description: phy config clock
40 - description: 19.2 MHz ref clk
41 - description: phy interface clock (Optional)
42
43 clock-names:
44 minItems: 2
45 maxItems: 3
46 items:
47 - const: cfg_ahb
48 - const: ref
49 - const: iface
50
51 vdda-pll-supply:
52 description:
53 Phandle to 1.8V regulator supply to PHY refclk pll block.
54
55 vdda-phy-dpdm-supply:
56 description:
57 Phandle to 3.1V regulator supply to Dp/Dm port signals.
58
59 resets:
60 maxItems: 1
61 description:
62 Phandle to reset to phy block.
63
64 nvmem-cells:
65 maxItems: 1
66 description:
67 Phandle to nvmem cell that contains 'HS Tx trim'
68 tuning parameter value for qusb2 phy.
69
70 qcom,tcsr-syscon:
71 description:
72 Phandle to TCSR syscon register region.
73 $ref: /schemas/types.yaml#/definitions/phandle
74
75if:
76 properties:
77 compatible:
78 contains:
79 const: qcom,qusb2-v2-phy
80then:
81 properties:
82 qcom,imp-res-offset-value:
83 description:
84 It is a 6 bit value that specifies offset to be
85 added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
86 tuning parameter that may vary for different boards of same SOC.
87 $ref: /schemas/types.yaml#/definitions/uint32
88 minimum: 0
89 maximum: 63
90 default: 0
91
92 qcom,bias-ctrl-value:
93 description:
94 It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
95 tuning parameter that may vary for different boards of same SOC.
96 $ref: /schemas/types.yaml#/definitions/uint32
97 minimum: 0
98 maximum: 63
99 default: 32
100
101 qcom,charge-ctrl-value:
102 description:
103 It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
104 tuning parameter that may vary for different boards of same SOC.
105 $ref: /schemas/types.yaml#/definitions/uint32
106 minimum: 0
107 maximum: 3
108 default: 0
109
110 qcom,hstx-trim-value:
111 description:
112 It is a 4 bit value that specifies tuning for HSTX
113 output current.
114 Possible range is - 15mA to 24mA (stepsize of 600 uA).
115 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
116 $ref: /schemas/types.yaml#/definitions/uint32
117 minimum: 0
118 maximum: 15
119 default: 3
120
121 qcom,preemphasis-level:
122 description:
123 It is a 2 bit value that specifies pre-emphasis level.
124 Possible range is 0 to 15% (stepsize of 5%).
125 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
126 $ref: /schemas/types.yaml#/definitions/uint32
127 minimum: 0
128 maximum: 3
129 default: 2
130
131 qcom,preemphasis-width:
132 description:
133 It is a 1 bit value that specifies how long the HSTX
134 pre-emphasis (specified using qcom,preemphasis-level) must be in
135 effect. Duration could be half-bit of full-bit.
136 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
137 $ref: /schemas/types.yaml#/definitions/uint32
138 minimum: 0
139 maximum: 1
140 default: 0
141
142 qcom,hsdisc-trim-value:
143 description:
144 It is a 2 bit value tuning parameter that control disconnect
145 threshold and may vary for different boards of same SOC.
146 $ref: /schemas/types.yaml#/definitions/uint32
147 minimum: 0
148 maximum: 3
149 default: 0
150
151required:
152 - compatible
153 - reg
154 - "#phy-cells"
155 - clocks
156 - clock-names
157 - vdda-pll-supply
158 - vdda-phy-dpdm-supply
159 - resets
160
161
162examples:
163 - |
164 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
165 hsusb_phy: phy@7411000 {
166 compatible = "qcom,msm8996-qusb2-phy";
167 reg = <0x7411000 0x180>;
168 #phy-cells = <0>;
169
170 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
171 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
172 clock-names = "cfg_ahb", "ref";
173
174 vdda-pll-supply = <&pm8994_l12>;
175 vdda-phy-dpdm-supply = <&pm8994_l24>;
176
177 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
178 nvmem-cells = <&qusb2p_hstx_trim>;
179 };