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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/serial/renesas,scifb.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Renesas Serial Communications Interface with FIFO B (SCIFB)
8
9maintainers:
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11
12allOf:
13 - $ref: serial.yaml#
14
15properties:
16 compatible:
17 oneOf:
18 - items:
19 - enum:
20 - renesas,scifb-r8a73a4 # R-Mobile APE6
21 - renesas,scifb-r8a7740 # R-Mobile A1
22 - renesas,scifb-sh73a0 # SH-Mobile AG5
23 - const: renesas,scifb # generic SCIFB compatible UART
24
25 - items:
26 - enum:
27 - renesas,scifb-r8a7742 # RZ/G1H
28 - renesas,scifb-r8a7743 # RZ/G1M
29 - renesas,scifb-r8a7744 # RZ/G1N
30 - renesas,scifb-r8a7745 # RZ/G1E
31 - renesas,scifb-r8a7790 # R-Car H2
32 - renesas,scifb-r8a7791 # R-Car M2-W
33 - renesas,scifb-r8a7793 # R-Car M2-N
34 - renesas,scifb-r8a7794 # R-Car E2
35 - const: renesas,rcar-gen2-scifb # R-Car Gen2 and RZ/G1
36 - const: renesas,scifb # generic SCIFB compatible UART
37
38 reg:
39 maxItems: 1
40
41 interrupts:
42 maxItems: 1
43
44 clocks:
45 maxItems: 1
46
47 clock-names:
48 enum:
49 - fck # UART functional clock
50
51 power-domains:
52 maxItems: 1
53
54 resets:
55 maxItems: 1
56
57 dmas:
58 description:
59 Must contain a list of pairs of references to DMA specifiers, one for
60 transmission, and one for reception.
61
62 dma-names:
63 minItems: 2
64 maxItems: 4
65 items:
66 enum:
67 - tx
68 - rx
69
70required:
71 - compatible
72 - reg
73 - interrupts
74 - clocks
75 - clock-names
76 - power-domains
77
78if:
79 properties:
80 compatible:
81 contains:
82 enum:
83 - renesas,rcar-gen2-scifb
84then:
85 required:
86 - resets
87
88examples:
89 - |
90 #include <dt-bindings/clock/r8a7740-clock.h>
91 #include <dt-bindings/interrupt-controller/arm-gic.h>
92 scifb: serial@e6c30000 {
93 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
94 reg = <0xe6c30000 0x100>;
95 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
96 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
97 clock-names = "fck";
98 power-domains = <&pd_a3sp>;
99 };