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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung Exynos5250 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung Exynos5250 SoC device nodes are listed in this file.
9 * Exynos5250 based board files can include this file and provide
10 * values for board specfic bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
14 * additional nodes can be added to this file.
15 */
16
17#include <dt-bindings/clock/exynos5250.h>
18#include "exynos5.dtsi"
19#include "exynos4-cpu-thermal.dtsi"
20#include <dt-bindings/clock/exynos-audss-clk.h>
21
22/ {
23 compatible = "samsung,exynos5250", "samsung,exynos5";
24
25 aliases {
26 spi0 = &spi_0;
27 spi1 = &spi_1;
28 spi2 = &spi_2;
29 gsc0 = &gsc_0;
30 gsc1 = &gsc_1;
31 gsc2 = &gsc_2;
32 gsc3 = &gsc_3;
33 mshc0 = &mmc_0;
34 mshc1 = &mmc_1;
35 mshc2 = &mmc_2;
36 mshc3 = &mmc_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 i2c8 = &i2c_8;
42 i2c9 = &i2c_9;
43 pinctrl0 = &pinctrl_0;
44 pinctrl1 = &pinctrl_1;
45 pinctrl2 = &pinctrl_2;
46 pinctrl3 = &pinctrl_3;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a15";
56 reg = <0>;
57 clocks = <&clock CLK_ARM_CLK>;
58 clock-names = "cpu";
59 operating-points-v2 = <&cpu0_opp_table>;
60 #cooling-cells = <2>; /* min followed by max */
61 };
62 cpu1: cpu@1 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a15";
65 reg = <1>;
66 clocks = <&clock CLK_ARM_CLK>;
67 clock-names = "cpu";
68 operating-points-v2 = <&cpu0_opp_table>;
69 #cooling-cells = <2>; /* min followed by max */
70 };
71 };
72
73 cpu0_opp_table: opp_table0 {
74 compatible = "operating-points-v2";
75 opp-shared;
76
77 opp-200000000 {
78 opp-hz = /bits/ 64 <200000000>;
79 opp-microvolt = <925000>;
80 clock-latency-ns = <140000>;
81 };
82 opp-300000000 {
83 opp-hz = /bits/ 64 <300000000>;
84 opp-microvolt = <937500>;
85 clock-latency-ns = <140000>;
86 };
87 opp-400000000 {
88 opp-hz = /bits/ 64 <400000000>;
89 opp-microvolt = <950000>;
90 clock-latency-ns = <140000>;
91 };
92 opp-500000000 {
93 opp-hz = /bits/ 64 <500000000>;
94 opp-microvolt = <975000>;
95 clock-latency-ns = <140000>;
96 };
97 opp-600000000 {
98 opp-hz = /bits/ 64 <600000000>;
99 opp-microvolt = <1000000>;
100 clock-latency-ns = <140000>;
101 };
102 opp-700000000 {
103 opp-hz = /bits/ 64 <700000000>;
104 opp-microvolt = <1012500>;
105 clock-latency-ns = <140000>;
106 };
107 opp-800000000 {
108 opp-hz = /bits/ 64 <800000000>;
109 opp-microvolt = <1025000>;
110 clock-latency-ns = <140000>;
111 };
112 opp-900000000 {
113 opp-hz = /bits/ 64 <900000000>;
114 opp-microvolt = <1050000>;
115 clock-latency-ns = <140000>;
116 };
117 opp-1000000000 {
118 opp-hz = /bits/ 64 <1000000000>;
119 opp-microvolt = <1075000>;
120 clock-latency-ns = <140000>;
121 opp-suspend;
122 };
123 opp-1100000000 {
124 opp-hz = /bits/ 64 <1100000000>;
125 opp-microvolt = <1100000>;
126 clock-latency-ns = <140000>;
127 };
128 opp-1200000000 {
129 opp-hz = /bits/ 64 <1200000000>;
130 opp-microvolt = <1125000>;
131 clock-latency-ns = <140000>;
132 };
133 opp-1300000000 {
134 opp-hz = /bits/ 64 <1300000000>;
135 opp-microvolt = <1150000>;
136 clock-latency-ns = <140000>;
137 };
138 opp-1400000000 {
139 opp-hz = /bits/ 64 <1400000000>;
140 opp-microvolt = <1200000>;
141 clock-latency-ns = <140000>;
142 };
143 opp-1500000000 {
144 opp-hz = /bits/ 64 <1500000000>;
145 opp-microvolt = <1225000>;
146 clock-latency-ns = <140000>;
147 };
148 opp-1600000000 {
149 opp-hz = /bits/ 64 <1600000000>;
150 opp-microvolt = <1250000>;
151 clock-latency-ns = <140000>;
152 };
153 opp-1700000000 {
154 opp-hz = /bits/ 64 <1700000000>;
155 opp-microvolt = <1300000>;
156 clock-latency-ns = <140000>;
157 };
158 };
159
160 pmu {
161 compatible = "arm,cortex-a15-pmu";
162 interrupt-parent = <&combiner>;
163 interrupts = <1 2>, <22 4>;
164 };
165
166 soc: soc {
167 sram@2020000 {
168 compatible = "mmio-sram";
169 reg = <0x02020000 0x30000>;
170 #address-cells = <1>;
171 #size-cells = <1>;
172 ranges = <0 0x02020000 0x30000>;
173
174 smp-sram@0 {
175 compatible = "samsung,exynos4210-sysram";
176 reg = <0x0 0x1000>;
177 };
178
179 smp-sram@2f000 {
180 compatible = "samsung,exynos4210-sysram-ns";
181 reg = <0x2f000 0x1000>;
182 };
183 };
184
185 pd_gsc: power-domain@10044000 {
186 compatible = "samsung,exynos4210-pd";
187 reg = <0x10044000 0x20>;
188 #power-domain-cells = <0>;
189 label = "GSC";
190 };
191
192 pd_mfc: power-domain@10044040 {
193 compatible = "samsung,exynos4210-pd";
194 reg = <0x10044040 0x20>;
195 #power-domain-cells = <0>;
196 label = "MFC";
197 };
198
199 pd_g3d: power-domain@10044060 {
200 compatible = "samsung,exynos4210-pd";
201 reg = <0x10044060 0x20>;
202 #power-domain-cells = <0>;
203 label = "G3D";
204 };
205
206 pd_disp1: power-domain@100440a0 {
207 compatible = "samsung,exynos4210-pd";
208 reg = <0x100440A0 0x20>;
209 #power-domain-cells = <0>;
210 label = "DISP1";
211 };
212
213 pd_mau: power-domain@100440c0 {
214 compatible = "samsung,exynos4210-pd";
215 reg = <0x100440C0 0x20>;
216 #power-domain-cells = <0>;
217 label = "MAU";
218 };
219
220 clock: clock-controller@10010000 {
221 compatible = "samsung,exynos5250-clock";
222 reg = <0x10010000 0x30000>;
223 #clock-cells = <1>;
224 };
225
226 clock_audss: audss-clock-controller@3810000 {
227 compatible = "samsung,exynos5250-audss-clock";
228 reg = <0x03810000 0x0C>;
229 #clock-cells = <1>;
230 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
231 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
232 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
233 power-domains = <&pd_mau>;
234 };
235
236 timer@101c0000 {
237 compatible = "samsung,exynos4210-mct";
238 reg = <0x101C0000 0x800>;
239 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
240 clock-names = "fin_pll", "mct";
241 interrupts-extended = <&combiner 23 3>,
242 <&combiner 23 4>,
243 <&combiner 25 2>,
244 <&combiner 25 3>,
245 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
246 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
247 };
248
249 pinctrl_0: pinctrl@11400000 {
250 compatible = "samsung,exynos5250-pinctrl";
251 reg = <0x11400000 0x1000>;
252 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
253
254 wakup_eint: wakeup-interrupt-controller {
255 compatible = "samsung,exynos4210-wakeup-eint";
256 interrupt-parent = <&gic>;
257 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
258 };
259 };
260
261 pinctrl_1: pinctrl@13400000 {
262 compatible = "samsung,exynos5250-pinctrl";
263 reg = <0x13400000 0x1000>;
264 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
265 };
266
267 pinctrl_2: pinctrl@10d10000 {
268 compatible = "samsung,exynos5250-pinctrl";
269 reg = <0x10d10000 0x1000>;
270 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
271 };
272
273 pinctrl_3: pinctrl@3860000 {
274 compatible = "samsung,exynos5250-pinctrl";
275 reg = <0x03860000 0x1000>;
276 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
277 power-domains = <&pd_mau>;
278 };
279
280 pmu_system_controller: system-controller@10040000 {
281 compatible = "samsung,exynos5250-pmu", "syscon";
282 reg = <0x10040000 0x5000>;
283 clock-names = "clkout16";
284 clocks = <&clock CLK_FIN_PLL>;
285 #clock-cells = <1>;
286 interrupt-controller;
287 #interrupt-cells = <3>;
288 interrupt-parent = <&gic>;
289 };
290
291 watchdog@101d0000 {
292 compatible = "samsung,exynos5250-wdt";
293 reg = <0x101D0000 0x100>;
294 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clock CLK_WDT>;
296 clock-names = "watchdog";
297 samsung,syscon-phandle = <&pmu_system_controller>;
298 };
299
300 mfc: codec@11000000 {
301 compatible = "samsung,mfc-v6";
302 reg = <0x11000000 0x10000>;
303 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
304 power-domains = <&pd_mfc>;
305 clocks = <&clock CLK_MFC>;
306 clock-names = "mfc";
307 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
308 iommu-names = "left", "right";
309 };
310
311 rotator: rotator@11c00000 {
312 compatible = "samsung,exynos5250-rotator";
313 reg = <0x11C00000 0x64>;
314 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clock CLK_ROTATOR>;
316 clock-names = "rotator";
317 iommus = <&sysmmu_rotator>;
318 };
319
320 mali: gpu@11800000 {
321 compatible = "samsung,exynos5250-mali", "arm,mali-t604";
322 reg = <0x11800000 0x5000>;
323 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
326 interrupt-names = "job", "mmu", "gpu";
327 clocks = <&clock CLK_G3D>;
328 clock-names = "core";
329 operating-points-v2 = <&gpu_opp_table>;
330 power-domains = <&pd_g3d>;
331 status = "disabled";
332
333 gpu_opp_table: gpu-opp-table {
334 compatible = "operating-points-v2";
335
336 opp-100000000 {
337 opp-hz = /bits/ 64 <100000000>;
338 opp-microvolt = <925000>;
339 };
340 opp-160000000 {
341 opp-hz = /bits/ 64 <160000000>;
342 opp-microvolt = <925000>;
343 };
344 opp-266000000 {
345 opp-hz = /bits/ 64 <266000000>;
346 opp-microvolt = <1025000>;
347 };
348 opp-350000000 {
349 opp-hz = /bits/ 64 <350000000>;
350 opp-microvolt = <1075000>;
351 };
352 opp-400000000 {
353 opp-hz = /bits/ 64 <400000000>;
354 opp-microvolt = <1125000>;
355 };
356 opp-450000000 {
357 opp-hz = /bits/ 64 <450000000>;
358 opp-microvolt = <1150000>;
359 };
360 opp-533000000 {
361 opp-hz = /bits/ 64 <533000000>;
362 opp-microvolt = <1250000>;
363 };
364 };
365 };
366
367 tmu: tmu@10060000 {
368 compatible = "samsung,exynos5250-tmu";
369 reg = <0x10060000 0x100>;
370 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clock CLK_TMU>;
372 clock-names = "tmu_apbif";
373 #thermal-sensor-cells = <0>;
374 };
375
376 sata: sata@122f0000 {
377 compatible = "snps,dwc-ahci";
378 samsung,sata-freq = <66>;
379 reg = <0x122F0000 0x1ff>;
380 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
382 clock-names = "sata", "sclk_sata";
383 phys = <&sata_phy>;
384 phy-names = "sata-phy";
385 ports-implemented = <0x1>;
386 status = "disabled";
387 };
388
389 sata_phy: sata-phy@12170000 {
390 compatible = "samsung,exynos5250-sata-phy";
391 reg = <0x12170000 0x1ff>;
392 clocks = <&clock CLK_SATA_PHYCTRL>;
393 clock-names = "sata_phyctrl";
394 #phy-cells = <0>;
395 samsung,syscon-phandle = <&pmu_system_controller>;
396 status = "disabled";
397 };
398
399 /* i2c_0-3 are defined in exynos5.dtsi */
400 i2c_4: i2c@12ca0000 {
401 compatible = "samsung,s3c2440-i2c";
402 reg = <0x12CA0000 0x100>;
403 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
404 #address-cells = <1>;
405 #size-cells = <0>;
406 clocks = <&clock CLK_I2C4>;
407 clock-names = "i2c";
408 pinctrl-names = "default";
409 pinctrl-0 = <&i2c4_bus>;
410 status = "disabled";
411 };
412
413 i2c_5: i2c@12cb0000 {
414 compatible = "samsung,s3c2440-i2c";
415 reg = <0x12CB0000 0x100>;
416 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 clocks = <&clock CLK_I2C5>;
420 clock-names = "i2c";
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c5_bus>;
423 status = "disabled";
424 };
425
426 i2c_6: i2c@12cc0000 {
427 compatible = "samsung,s3c2440-i2c";
428 reg = <0x12CC0000 0x100>;
429 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
431 #size-cells = <0>;
432 clocks = <&clock CLK_I2C6>;
433 clock-names = "i2c";
434 pinctrl-names = "default";
435 pinctrl-0 = <&i2c6_bus>;
436 status = "disabled";
437 };
438
439 i2c_7: i2c@12cd0000 {
440 compatible = "samsung,s3c2440-i2c";
441 reg = <0x12CD0000 0x100>;
442 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
444 #size-cells = <0>;
445 clocks = <&clock CLK_I2C7>;
446 clock-names = "i2c";
447 pinctrl-names = "default";
448 pinctrl-0 = <&i2c7_bus>;
449 status = "disabled";
450 };
451
452 i2c_8: i2c@12ce0000 {
453 compatible = "samsung,s3c2440-hdmiphy-i2c";
454 reg = <0x12CE0000 0x1000>;
455 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
456 #address-cells = <1>;
457 #size-cells = <0>;
458 clocks = <&clock CLK_I2C_HDMI>;
459 clock-names = "i2c";
460 status = "disabled";
461
462 hdmiphy: hdmiphy@38 {
463 compatible = "samsung,exynos4212-hdmiphy";
464 reg = <0x38>;
465 };
466 };
467
468 i2c_9: i2c@121d0000 {
469 compatible = "samsung,exynos5-sata-phy-i2c";
470 reg = <0x121D0000 0x100>;
471 #address-cells = <1>;
472 #size-cells = <0>;
473 clocks = <&clock CLK_SATA_PHYI2C>;
474 clock-names = "i2c";
475 status = "disabled";
476 };
477
478 spi_0: spi@12d20000 {
479 compatible = "samsung,exynos4210-spi";
480 status = "disabled";
481 reg = <0x12d20000 0x100>;
482 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
483 dmas = <&pdma0 5
484 &pdma0 4>;
485 dma-names = "tx", "rx";
486 #address-cells = <1>;
487 #size-cells = <0>;
488 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
489 clock-names = "spi", "spi_busclk0";
490 pinctrl-names = "default";
491 pinctrl-0 = <&spi0_bus>;
492 };
493
494 spi_1: spi@12d30000 {
495 compatible = "samsung,exynos4210-spi";
496 status = "disabled";
497 reg = <0x12d30000 0x100>;
498 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
499 dmas = <&pdma1 5
500 &pdma1 4>;
501 dma-names = "tx", "rx";
502 #address-cells = <1>;
503 #size-cells = <0>;
504 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
505 clock-names = "spi", "spi_busclk0";
506 pinctrl-names = "default";
507 pinctrl-0 = <&spi1_bus>;
508 };
509
510 spi_2: spi@12d40000 {
511 compatible = "samsung,exynos4210-spi";
512 status = "disabled";
513 reg = <0x12d40000 0x100>;
514 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
515 dmas = <&pdma0 7
516 &pdma0 6>;
517 dma-names = "tx", "rx";
518 #address-cells = <1>;
519 #size-cells = <0>;
520 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
521 clock-names = "spi", "spi_busclk0";
522 pinctrl-names = "default";
523 pinctrl-0 = <&spi2_bus>;
524 };
525
526 mmc_0: mmc@12200000 {
527 compatible = "samsung,exynos5250-dw-mshc";
528 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
529 #address-cells = <1>;
530 #size-cells = <0>;
531 reg = <0x12200000 0x1000>;
532 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
533 clock-names = "biu", "ciu";
534 fifo-depth = <0x80>;
535 status = "disabled";
536 };
537
538 mmc_1: mmc@12210000 {
539 compatible = "samsung,exynos5250-dw-mshc";
540 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 reg = <0x12210000 0x1000>;
544 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
545 clock-names = "biu", "ciu";
546 fifo-depth = <0x80>;
547 status = "disabled";
548 };
549
550 mmc_2: mmc@12220000 {
551 compatible = "samsung,exynos5250-dw-mshc";
552 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 reg = <0x12220000 0x1000>;
556 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
557 clock-names = "biu", "ciu";
558 fifo-depth = <0x80>;
559 status = "disabled";
560 };
561
562 mmc_3: mmc@12230000 {
563 compatible = "samsung,exynos5250-dw-mshc";
564 reg = <0x12230000 0x1000>;
565 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
566 #address-cells = <1>;
567 #size-cells = <0>;
568 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
569 clock-names = "biu", "ciu";
570 fifo-depth = <0x80>;
571 status = "disabled";
572 };
573
574 i2s0: i2s@3830000 {
575 compatible = "samsung,s5pv210-i2s";
576 status = "disabled";
577 reg = <0x03830000 0x100>;
578 dmas = <&pdma0 10>,
579 <&pdma0 9>,
580 <&pdma0 8>;
581 dma-names = "tx", "rx", "tx-sec";
582 clocks = <&clock_audss EXYNOS_I2S_BUS>,
583 <&clock_audss EXYNOS_I2S_BUS>,
584 <&clock_audss EXYNOS_SCLK_I2S>;
585 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
586 samsung,idma-addr = <0x03000000>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&i2s0_bus>;
589 power-domains = <&pd_mau>;
590 #clock-cells = <1>;
591 #sound-dai-cells = <1>;
592 };
593
594 i2s1: i2s@12d60000 {
595 compatible = "samsung,s3c6410-i2s";
596 status = "disabled";
597 reg = <0x12D60000 0x100>;
598 dmas = <&pdma1 12>,
599 <&pdma1 11>;
600 dma-names = "tx", "rx";
601 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
602 clock-names = "iis", "i2s_opclk0";
603 pinctrl-names = "default";
604 pinctrl-0 = <&i2s1_bus>;
605 power-domains = <&pd_mau>;
606 #sound-dai-cells = <1>;
607 };
608
609 i2s2: i2s@12d70000 {
610 compatible = "samsung,s3c6410-i2s";
611 status = "disabled";
612 reg = <0x12D70000 0x100>;
613 dmas = <&pdma0 12>,
614 <&pdma0 11>;
615 dma-names = "tx", "rx";
616 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
617 clock-names = "iis", "i2s_opclk0";
618 pinctrl-names = "default";
619 pinctrl-0 = <&i2s2_bus>;
620 power-domains = <&pd_mau>;
621 #sound-dai-cells = <1>;
622 };
623
624 usb_dwc3 {
625 compatible = "samsung,exynos5250-dwusb3";
626 clocks = <&clock CLK_USB3>;
627 clock-names = "usbdrd30";
628 #address-cells = <1>;
629 #size-cells = <1>;
630 ranges;
631
632 usbdrd_dwc3: dwc3@12000000 {
633 compatible = "synopsys,dwc3";
634 reg = <0x12000000 0x10000>;
635 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
636 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
637 phy-names = "usb2-phy", "usb3-phy";
638 };
639 };
640
641 usbdrd_phy: phy@12100000 {
642 compatible = "samsung,exynos5250-usbdrd-phy";
643 reg = <0x12100000 0x100>;
644 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
645 clock-names = "phy", "ref";
646 samsung,pmu-syscon = <&pmu_system_controller>;
647 #phy-cells = <1>;
648 };
649
650 ehci: usb@12110000 {
651 compatible = "samsung,exynos4210-ehci";
652 reg = <0x12110000 0x100>;
653 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
654
655 clocks = <&clock CLK_USB2>;
656 clock-names = "usbhost";
657 phys = <&usb2_phy_gen 1>;
658 phy-names = "host";
659 };
660
661 ohci: usb@12120000 {
662 compatible = "samsung,exynos4210-ohci";
663 reg = <0x12120000 0x100>;
664 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
665
666 clocks = <&clock CLK_USB2>;
667 clock-names = "usbhost";
668 phys = <&usb2_phy_gen 1>;
669 phy-names = "host";
670 };
671
672 usb2_phy_gen: phy@12130000 {
673 compatible = "samsung,exynos5250-usb2-phy";
674 reg = <0x12130000 0x100>;
675 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
676 clock-names = "phy", "ref";
677 #phy-cells = <1>;
678 samsung,sysreg-phandle = <&sysreg_system_controller>;
679 samsung,pmureg-phandle = <&pmu_system_controller>;
680 };
681
682 pdma0: pdma@121a0000 {
683 compatible = "arm,pl330", "arm,primecell";
684 reg = <0x121A0000 0x1000>;
685 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&clock CLK_PDMA0>;
687 clock-names = "apb_pclk";
688 #dma-cells = <1>;
689 #dma-channels = <8>;
690 #dma-requests = <32>;
691 };
692
693 pdma1: pdma@121b0000 {
694 compatible = "arm,pl330", "arm,primecell";
695 reg = <0x121B0000 0x1000>;
696 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&clock CLK_PDMA1>;
698 clock-names = "apb_pclk";
699 #dma-cells = <1>;
700 #dma-channels = <8>;
701 #dma-requests = <32>;
702 };
703
704 mdma0: mdma@10800000 {
705 compatible = "arm,pl330", "arm,primecell";
706 reg = <0x10800000 0x1000>;
707 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&clock CLK_MDMA0>;
709 clock-names = "apb_pclk";
710 #dma-cells = <1>;
711 #dma-channels = <8>;
712 #dma-requests = <1>;
713 };
714
715 mdma1: mdma@11c10000 {
716 compatible = "arm,pl330", "arm,primecell";
717 reg = <0x11C10000 0x1000>;
718 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&clock CLK_MDMA1>;
720 clock-names = "apb_pclk";
721 #dma-cells = <1>;
722 #dma-channels = <8>;
723 #dma-requests = <1>;
724 };
725
726 gsc_0: gsc@13e00000 {
727 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
728 reg = <0x13e00000 0x1000>;
729 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
730 power-domains = <&pd_gsc>;
731 clocks = <&clock CLK_GSCL0>;
732 clock-names = "gscl";
733 iommus = <&sysmmu_gsc0>;
734 };
735
736 gsc_1: gsc@13e10000 {
737 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
738 reg = <0x13e10000 0x1000>;
739 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
740 power-domains = <&pd_gsc>;
741 clocks = <&clock CLK_GSCL1>;
742 clock-names = "gscl";
743 iommus = <&sysmmu_gsc1>;
744 };
745
746 gsc_2: gsc@13e20000 {
747 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
748 reg = <0x13e20000 0x1000>;
749 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
750 power-domains = <&pd_gsc>;
751 clocks = <&clock CLK_GSCL2>;
752 clock-names = "gscl";
753 iommus = <&sysmmu_gsc2>;
754 };
755
756 gsc_3: gsc@13e30000 {
757 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
758 reg = <0x13e30000 0x1000>;
759 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
760 power-domains = <&pd_gsc>;
761 clocks = <&clock CLK_GSCL3>;
762 clock-names = "gscl";
763 iommus = <&sysmmu_gsc3>;
764 };
765
766 hdmi: hdmi@14530000 {
767 compatible = "samsung,exynos4212-hdmi";
768 reg = <0x14530000 0x70000>;
769 power-domains = <&pd_disp1>;
770 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
772 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
773 <&clock CLK_MOUT_HDMI>;
774 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
775 "sclk_hdmiphy", "mout_hdmi";
776 samsung,syscon-phandle = <&pmu_system_controller>;
777 phy = <&hdmiphy>;
778 #sound-dai-cells = <0>;
779 status = "disabled";
780 };
781
782 hdmicec: cec@101b0000 {
783 compatible = "samsung,s5p-cec";
784 reg = <0x101B0000 0x200>;
785 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clock CLK_HDMI_CEC>;
787 clock-names = "hdmicec";
788 samsung,syscon-phandle = <&pmu_system_controller>;
789 hdmi-phandle = <&hdmi>;
790 pinctrl-names = "default";
791 pinctrl-0 = <&hdmi_cec>;
792 status = "disabled";
793 };
794
795 mixer: mixer@14450000 {
796 compatible = "samsung,exynos5250-mixer";
797 reg = <0x14450000 0x10000>;
798 power-domains = <&pd_disp1>;
799 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
801 <&clock CLK_SCLK_HDMI>;
802 clock-names = "mixer", "hdmi", "sclk_hdmi";
803 iommus = <&sysmmu_tv>;
804 status = "disabled";
805 };
806
807 dp_phy: video-phy {
808 compatible = "samsung,exynos5250-dp-video-phy";
809 samsung,pmu-syscon = <&pmu_system_controller>;
810 #phy-cells = <0>;
811 };
812
813 mipi_phy: video-phy@10040710 {
814 compatible = "samsung,s5pv210-mipi-video-phy";
815 reg = <0x10040710 0x100>;
816 #phy-cells = <1>;
817 syscon = <&pmu_system_controller>;
818 };
819
820 dsi_0: dsi@14500000 {
821 compatible = "samsung,exynos4210-mipi-dsi";
822 reg = <0x14500000 0x10000>;
823 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
824 samsung,power-domain = <&pd_disp1>;
825 phys = <&mipi_phy 3>;
826 phy-names = "dsim";
827 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
828 clock-names = "bus_clk", "sclk_mipi";
829 status = "disabled";
830 #address-cells = <1>;
831 #size-cells = <0>;
832 };
833
834 adc: adc@12d10000 {
835 compatible = "samsung,exynos-adc-v1";
836 reg = <0x12D10000 0x100>;
837 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&clock CLK_ADC>;
839 clock-names = "adc";
840 #io-channel-cells = <1>;
841 io-channel-ranges;
842 samsung,syscon-phandle = <&pmu_system_controller>;
843 status = "disabled";
844 };
845
846 sysmmu_g2d: sysmmu@10a60000 {
847 compatible = "samsung,exynos-sysmmu";
848 reg = <0x10A60000 0x1000>;
849 interrupt-parent = <&combiner>;
850 interrupts = <24 5>;
851 clock-names = "sysmmu", "master";
852 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
853 #iommu-cells = <0>;
854 };
855
856 sysmmu_mfc_r: sysmmu@11200000 {
857 compatible = "samsung,exynos-sysmmu";
858 reg = <0x11200000 0x1000>;
859 interrupt-parent = <&combiner>;
860 interrupts = <6 2>;
861 power-domains = <&pd_mfc>;
862 clock-names = "sysmmu", "master";
863 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
864 #iommu-cells = <0>;
865 };
866
867 sysmmu_mfc_l: sysmmu@11210000 {
868 compatible = "samsung,exynos-sysmmu";
869 reg = <0x11210000 0x1000>;
870 interrupt-parent = <&combiner>;
871 interrupts = <8 5>;
872 power-domains = <&pd_mfc>;
873 clock-names = "sysmmu", "master";
874 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
875 #iommu-cells = <0>;
876 };
877
878 sysmmu_rotator: sysmmu@11d40000 {
879 compatible = "samsung,exynos-sysmmu";
880 reg = <0x11D40000 0x1000>;
881 interrupt-parent = <&combiner>;
882 interrupts = <4 0>;
883 clock-names = "sysmmu", "master";
884 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
885 #iommu-cells = <0>;
886 };
887
888 sysmmu_jpeg: sysmmu@11f20000 {
889 compatible = "samsung,exynos-sysmmu";
890 reg = <0x11F20000 0x1000>;
891 interrupt-parent = <&combiner>;
892 interrupts = <4 2>;
893 power-domains = <&pd_gsc>;
894 clock-names = "sysmmu", "master";
895 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
896 #iommu-cells = <0>;
897 };
898
899 sysmmu_fimc_isp: sysmmu@13260000 {
900 compatible = "samsung,exynos-sysmmu";
901 reg = <0x13260000 0x1000>;
902 interrupt-parent = <&combiner>;
903 interrupts = <10 6>;
904 clock-names = "sysmmu";
905 clocks = <&clock CLK_SMMU_FIMC_ISP>;
906 #iommu-cells = <0>;
907 };
908
909 sysmmu_fimc_drc: sysmmu@13270000 {
910 compatible = "samsung,exynos-sysmmu";
911 reg = <0x13270000 0x1000>;
912 interrupt-parent = <&combiner>;
913 interrupts = <11 6>;
914 clock-names = "sysmmu";
915 clocks = <&clock CLK_SMMU_FIMC_DRC>;
916 #iommu-cells = <0>;
917 };
918
919 sysmmu_fimc_fd: sysmmu@132a0000 {
920 compatible = "samsung,exynos-sysmmu";
921 reg = <0x132A0000 0x1000>;
922 interrupt-parent = <&combiner>;
923 interrupts = <5 0>;
924 clock-names = "sysmmu";
925 clocks = <&clock CLK_SMMU_FIMC_FD>;
926 #iommu-cells = <0>;
927 };
928
929 sysmmu_fimc_scc: sysmmu@13280000 {
930 compatible = "samsung,exynos-sysmmu";
931 reg = <0x13280000 0x1000>;
932 interrupt-parent = <&combiner>;
933 interrupts = <5 2>;
934 clock-names = "sysmmu";
935 clocks = <&clock CLK_SMMU_FIMC_SCC>;
936 #iommu-cells = <0>;
937 };
938
939 sysmmu_fimc_scp: sysmmu@13290000 {
940 compatible = "samsung,exynos-sysmmu";
941 reg = <0x13290000 0x1000>;
942 interrupt-parent = <&combiner>;
943 interrupts = <3 6>;
944 clock-names = "sysmmu";
945 clocks = <&clock CLK_SMMU_FIMC_SCP>;
946 #iommu-cells = <0>;
947 };
948
949 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
950 compatible = "samsung,exynos-sysmmu";
951 reg = <0x132B0000 0x1000>;
952 interrupt-parent = <&combiner>;
953 interrupts = <5 4>;
954 clock-names = "sysmmu";
955 clocks = <&clock CLK_SMMU_FIMC_MCU>;
956 #iommu-cells = <0>;
957 };
958
959 sysmmu_fimc_odc: sysmmu@132c0000 {
960 compatible = "samsung,exynos-sysmmu";
961 reg = <0x132C0000 0x1000>;
962 interrupt-parent = <&combiner>;
963 interrupts = <11 0>;
964 clock-names = "sysmmu";
965 clocks = <&clock CLK_SMMU_FIMC_ODC>;
966 #iommu-cells = <0>;
967 };
968
969 sysmmu_fimc_dis0: sysmmu@132d0000 {
970 compatible = "samsung,exynos-sysmmu";
971 reg = <0x132D0000 0x1000>;
972 interrupt-parent = <&combiner>;
973 interrupts = <10 4>;
974 clock-names = "sysmmu";
975 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
976 #iommu-cells = <0>;
977 };
978
979 sysmmu_fimc_dis1: sysmmu@132e0000 {
980 compatible = "samsung,exynos-sysmmu";
981 reg = <0x132E0000 0x1000>;
982 interrupt-parent = <&combiner>;
983 interrupts = <9 4>;
984 clock-names = "sysmmu";
985 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
986 #iommu-cells = <0>;
987 };
988
989 sysmmu_fimc_3dnr: sysmmu@132f0000 {
990 compatible = "samsung,exynos-sysmmu";
991 reg = <0x132F0000 0x1000>;
992 interrupt-parent = <&combiner>;
993 interrupts = <5 6>;
994 clock-names = "sysmmu";
995 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
996 #iommu-cells = <0>;
997 };
998
999 sysmmu_fimc_lite0: sysmmu@13c40000 {
1000 compatible = "samsung,exynos-sysmmu";
1001 reg = <0x13C40000 0x1000>;
1002 interrupt-parent = <&combiner>;
1003 interrupts = <3 4>;
1004 power-domains = <&pd_gsc>;
1005 clock-names = "sysmmu", "master";
1006 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
1007 #iommu-cells = <0>;
1008 };
1009
1010 sysmmu_fimc_lite1: sysmmu@13c50000 {
1011 compatible = "samsung,exynos-sysmmu";
1012 reg = <0x13C50000 0x1000>;
1013 interrupt-parent = <&combiner>;
1014 interrupts = <24 1>;
1015 power-domains = <&pd_gsc>;
1016 clock-names = "sysmmu", "master";
1017 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
1018 #iommu-cells = <0>;
1019 };
1020
1021 sysmmu_gsc0: sysmmu@13e80000 {
1022 compatible = "samsung,exynos-sysmmu";
1023 reg = <0x13E80000 0x1000>;
1024 interrupt-parent = <&combiner>;
1025 interrupts = <2 0>;
1026 power-domains = <&pd_gsc>;
1027 clock-names = "sysmmu", "master";
1028 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1029 #iommu-cells = <0>;
1030 };
1031
1032 sysmmu_gsc1: sysmmu@13e90000 {
1033 compatible = "samsung,exynos-sysmmu";
1034 reg = <0x13E90000 0x1000>;
1035 interrupt-parent = <&combiner>;
1036 interrupts = <2 2>;
1037 power-domains = <&pd_gsc>;
1038 clock-names = "sysmmu", "master";
1039 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1040 #iommu-cells = <0>;
1041 };
1042
1043 sysmmu_gsc2: sysmmu@13ea0000 {
1044 compatible = "samsung,exynos-sysmmu";
1045 reg = <0x13EA0000 0x1000>;
1046 interrupt-parent = <&combiner>;
1047 interrupts = <2 4>;
1048 power-domains = <&pd_gsc>;
1049 clock-names = "sysmmu", "master";
1050 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1051 #iommu-cells = <0>;
1052 };
1053
1054 sysmmu_gsc3: sysmmu@13eb0000 {
1055 compatible = "samsung,exynos-sysmmu";
1056 reg = <0x13EB0000 0x1000>;
1057 interrupt-parent = <&combiner>;
1058 interrupts = <2 6>;
1059 power-domains = <&pd_gsc>;
1060 clock-names = "sysmmu", "master";
1061 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1062 #iommu-cells = <0>;
1063 };
1064
1065 sysmmu_fimd1: sysmmu@14640000 {
1066 compatible = "samsung,exynos-sysmmu";
1067 reg = <0x14640000 0x1000>;
1068 interrupt-parent = <&combiner>;
1069 interrupts = <3 2>;
1070 power-domains = <&pd_disp1>;
1071 clock-names = "sysmmu", "master";
1072 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1073 #iommu-cells = <0>;
1074 };
1075
1076 sysmmu_tv: sysmmu@14650000 {
1077 compatible = "samsung,exynos-sysmmu";
1078 reg = <0x14650000 0x1000>;
1079 interrupt-parent = <&combiner>;
1080 interrupts = <7 4>;
1081 power-domains = <&pd_disp1>;
1082 clock-names = "sysmmu", "master";
1083 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1084 #iommu-cells = <0>;
1085 };
1086 };
1087
1088 thermal-zones {
1089 cpu_thermal: cpu-thermal {
1090 polling-delay-passive = <0>;
1091 polling-delay = <0>;
1092 thermal-sensors = <&tmu 0>;
1093
1094 cooling-maps {
1095 map0 {
1096 /* Corresponds to 800MHz at freq_table */
1097 cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1098 };
1099 map1 {
1100 /* Corresponds to 200MHz at freq_table */
1101 cooling-device = <&cpu0 15 15>,
1102 <&cpu1 15 15>;
1103 };
1104 };
1105 };
1106 };
1107
1108 timer {
1109 compatible = "arm,armv7-timer";
1110 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1111 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1112 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1113 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1114 /*
1115 * Unfortunately we need this since some versions
1116 * of U-Boot on Exynos don't set the CNTFRQ register,
1117 * so we need the value from DT.
1118 */
1119 clock-frequency = <24000000>;
1120 };
1121};
1122
1123&dp {
1124 power-domains = <&pd_disp1>;
1125 clocks = <&clock CLK_DP>;
1126 clock-names = "dp";
1127 phys = <&dp_phy>;
1128 phy-names = "dp";
1129};
1130
1131&fimd {
1132 power-domains = <&pd_disp1>;
1133 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1134 clock-names = "sclk_fimd", "fimd";
1135 iommus = <&sysmmu_fimd1>;
1136};
1137
1138&g2d {
1139 iommus = <&sysmmu_g2d>;
1140 clocks = <&clock CLK_G2D>;
1141 clock-names = "fimg2d";
1142 status = "okay";
1143};
1144
1145&i2c_0 {
1146 clocks = <&clock CLK_I2C0>;
1147 clock-names = "i2c";
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&i2c0_bus>;
1150};
1151
1152&i2c_1 {
1153 clocks = <&clock CLK_I2C1>;
1154 clock-names = "i2c";
1155 pinctrl-names = "default";
1156 pinctrl-0 = <&i2c1_bus>;
1157};
1158
1159&i2c_2 {
1160 clocks = <&clock CLK_I2C2>;
1161 clock-names = "i2c";
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&i2c2_bus>;
1164};
1165
1166&i2c_3 {
1167 clocks = <&clock CLK_I2C3>;
1168 clock-names = "i2c";
1169 pinctrl-names = "default";
1170 pinctrl-0 = <&i2c3_bus>;
1171};
1172
1173&prng {
1174 clocks = <&clock CLK_SSS>;
1175 clock-names = "secss";
1176};
1177
1178&pwm {
1179 clocks = <&clock CLK_PWM>;
1180 clock-names = "timers";
1181};
1182
1183&rtc {
1184 clocks = <&clock CLK_RTC>;
1185 clock-names = "rtc";
1186 interrupt-parent = <&pmu_system_controller>;
1187 status = "disabled";
1188};
1189
1190&serial_0 {
1191 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1192 clock-names = "uart", "clk_uart_baud0";
1193 dmas = <&pdma0 13>, <&pdma0 14>;
1194 dma-names = "rx", "tx";
1195};
1196
1197&serial_1 {
1198 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1199 clock-names = "uart", "clk_uart_baud0";
1200 dmas = <&pdma1 15>, <&pdma1 16>;
1201 dma-names = "rx", "tx";
1202};
1203
1204&serial_2 {
1205 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1206 clock-names = "uart", "clk_uart_baud0";
1207 dmas = <&pdma0 15>, <&pdma0 16>;
1208 dma-names = "rx", "tx";
1209};
1210
1211&serial_3 {
1212 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1213 clock-names = "uart", "clk_uart_baud0";
1214 dmas = <&pdma1 17>, <&pdma1 18>;
1215 dma-names = "rx", "tx";
1216};
1217
1218&sss {
1219 clocks = <&clock CLK_SSS>;
1220 clock-names = "secss";
1221};
1222
1223&trng {
1224 clocks = <&clock CLK_SSS>;
1225 clock-names = "secss";
1226};
1227
1228#include "exynos5250-pinctrl.dtsi"
1229#include "exynos-syscon-restart.dtsi"