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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
4 *
5 * Copyright (C) 2012 Atmel,
6 * 2012 Hong Xu <hong.xu@atmel.com>
7 */
8
9#include <dt-bindings/dma/at91.h>
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/clock/at91.h>
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 model = "Atmel AT91SAM9N12 SoC";
19 compatible = "atmel,at91sam9n12";
20 interrupt-parent = <&aic>;
21
22 aliases {
23 serial0 = &dbgu;
24 serial1 = &usart0;
25 serial2 = &usart1;
26 serial3 = &usart2;
27 serial4 = &usart3;
28 gpio0 = &pioA;
29 gpio1 = &pioB;
30 gpio2 = &pioC;
31 gpio3 = &pioD;
32 tcb0 = &tcb0;
33 tcb1 = &tcb1;
34 i2c0 = &i2c0;
35 i2c1 = &i2c1;
36 ssc0 = &ssc0;
37 pwm0 = &pwm0;
38 };
39 cpus {
40 #address-cells = <0>;
41 #size-cells = <0>;
42
43 cpu {
44 compatible = "arm,arm926ej-s";
45 device_type = "cpu";
46 };
47 };
48
49 memory {
50 device_type = "memory";
51 reg = <0x20000000 0x10000000>;
52 };
53
54 clocks {
55 slow_xtal: slow_xtal {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <0>;
59 };
60
61 main_xtal: main_xtal {
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <0>;
65 };
66 };
67
68 sram: sram@300000 {
69 compatible = "mmio-sram";
70 reg = <0x00300000 0x8000>;
71 };
72
73 ahb {
74 compatible = "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges;
78
79 apb {
80 compatible = "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 ranges;
84
85 aic: interrupt-controller@fffff000 {
86 #interrupt-cells = <3>;
87 compatible = "atmel,at91rm9200-aic";
88 interrupt-controller;
89 reg = <0xfffff000 0x200>;
90 atmel,external-irqs = <31>;
91 };
92
93 matrix: matrix@ffffde00 {
94 compatible = "atmel,at91sam9n12-matrix", "syscon";
95 reg = <0xffffde00 0x100>;
96 };
97
98 pmecc: ecc-engine@ffffe000 {
99 compatible = "atmel,at91sam9g45-pmecc";
100 reg = <0xffffe000 0x600>,
101 <0xffffe600 0x200>;
102 };
103
104 ramc0: ramc@ffffe800 {
105 compatible = "atmel,at91sam9g45-ddramc";
106 reg = <0xffffe800 0x200>;
107 clocks = <&pmc PMC_TYPE_SYSTEM 2>;
108 clock-names = "ddrck";
109 };
110
111 smc: smc@ffffea00 {
112 compatible = "atmel,at91sam9260-smc", "syscon";
113 reg = <0xffffea00 0x200>;
114 };
115
116 pmc: pmc@fffffc00 {
117 compatible = "atmel,at91sam9n12-pmc", "syscon";
118 reg = <0xfffffc00 0x200>;
119 #clock-cells = <2>;
120 clocks = <&clk32k>, <&main_xtal>;
121 clock-names = "slow_clk", "main_xtal";
122 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
123 };
124
125 rstc@fffffe00 {
126 compatible = "atmel,at91sam9g45-rstc";
127 reg = <0xfffffe00 0x10>;
128 clocks = <&clk32k>;
129 };
130
131 pit: timer@fffffe30 {
132 compatible = "atmel,at91sam9260-pit";
133 reg = <0xfffffe30 0xf>;
134 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
135 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
136 };
137
138 shdwc@fffffe10 {
139 compatible = "atmel,at91sam9x5-shdwc";
140 reg = <0xfffffe10 0x10>;
141 clocks = <&clk32k>;
142 };
143
144 sckc@fffffe50 {
145 compatible = "atmel,at91sam9x5-sckc";
146 reg = <0xfffffe50 0x4>;
147
148 slow_osc: slow_osc {
149 compatible = "atmel,at91sam9x5-clk-slow-osc";
150 #clock-cells = <0>;
151 clocks = <&slow_xtal>;
152 };
153
154 slow_rc_osc: slow_rc_osc {
155 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
156 #clock-cells = <0>;
157 clock-frequency = <32768>;
158 clock-accuracy = <50000000>;
159 };
160
161 clk32k: slck {
162 compatible = "atmel,at91sam9x5-clk-slow";
163 #clock-cells = <0>;
164 clocks = <&slow_rc_osc>, <&slow_osc>;
165 };
166 };
167
168 mmc0: mmc@f0008000 {
169 compatible = "atmel,hsmci";
170 reg = <0xf0008000 0x600>;
171 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
172 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
173 dma-names = "rxtx";
174 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
175 clock-names = "mci_clk";
176 #address-cells = <1>;
177 #size-cells = <0>;
178 status = "disabled";
179 };
180
181 tcb0: timer@f8008000 {
182 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
183 #address-cells = <1>;
184 #size-cells = <0>;
185 reg = <0xf8008000 0x100>;
186 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
187 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
188 clock-names = "t0_clk", "slow_clk";
189 };
190
191 tcb1: timer@f800c000 {
192 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
193 #address-cells = <1>;
194 #size-cells = <0>;
195 reg = <0xf800c000 0x100>;
196 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
197 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
198 clock-names = "t0_clk", "slow_clk";
199 };
200
201 hlcdc: hlcdc@f8038000 {
202 compatible = "atmel,at91sam9n12-hlcdc";
203 reg = <0xf8038000 0x2000>;
204 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
205 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
206 clock-names = "periph_clk", "sys_clk", "slow_clk";
207 status = "disabled";
208
209 hlcdc-display-controller {
210 compatible = "atmel,hlcdc-display-controller";
211 #address-cells = <1>;
212 #size-cells = <0>;
213
214 port@0 {
215 #address-cells = <1>;
216 #size-cells = <0>;
217 reg = <0>;
218 };
219 };
220
221 hlcdc_pwm: hlcdc-pwm {
222 compatible = "atmel,hlcdc-pwm";
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_lcd_pwm>;
225 #pwm-cells = <3>;
226 };
227 };
228
229 dma: dma-controller@ffffec00 {
230 compatible = "atmel,at91sam9g45-dma";
231 reg = <0xffffec00 0x200>;
232 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
233 #dma-cells = <2>;
234 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
235 clock-names = "dma_clk";
236 };
237
238 pinctrl@fffff400 {
239 #address-cells = <1>;
240 #size-cells = <1>;
241 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
242 ranges = <0xfffff400 0xfffff400 0x800>;
243
244 atmel,mux-mask = <
245 /* A B C */
246 0xffffffff 0xffe07983 0x00000000 /* pioA */
247 0x00040000 0x00047e0f 0x00000000 /* pioB */
248 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
249 0x003fffff 0x003f8000 0x00000000 /* pioD */
250 >;
251
252 /* shared pinctrl settings */
253 dbgu {
254 pinctrl_dbgu: dbgu-0 {
255 atmel,pins =
256 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
257 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
258 };
259 };
260
261 lcd {
262 pinctrl_lcd_base: lcd-base-0 {
263 atmel,pins =
264 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
265 AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
266 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */
267 AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
268 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
269 };
270
271 pinctrl_lcd_pwm: lcd-pwm-0 {
272 atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
273 };
274
275 pinctrl_lcd_rgb888: lcd-rgb-3 {
276 atmel,pins =
277 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
278 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
279 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
280 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
281 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
282 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
283 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
284 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
285 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
286 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
287 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
288 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
289 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
290 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
291 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
292 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
293 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
294 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
295 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
296 AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
297 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
298 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
299 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
300 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
301 };
302 };
303
304 usart0 {
305 pinctrl_usart0: usart0-0 {
306 atmel,pins =
307 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
308 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
309 };
310
311 pinctrl_usart0_rts: usart0_rts-0 {
312 atmel,pins =
313 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
314 };
315
316 pinctrl_usart0_cts: usart0_cts-0 {
317 atmel,pins =
318 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
319 };
320 };
321
322 usart1 {
323 pinctrl_usart1: usart1-0 {
324 atmel,pins =
325 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
326 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
327 };
328 };
329
330 usart2 {
331 pinctrl_usart2: usart2-0 {
332 atmel,pins =
333 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
334 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */
335 };
336
337 pinctrl_usart2_rts: usart2_rts-0 {
338 atmel,pins =
339 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
340 };
341
342 pinctrl_usart2_cts: usart2_cts-0 {
343 atmel,pins =
344 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
345 };
346 };
347
348 usart3 {
349 pinctrl_usart3: usart3-0 {
350 atmel,pins =
351 <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */
352 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
353 };
354
355 pinctrl_usart3_rts: usart3_rts-0 {
356 atmel,pins =
357 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
358 };
359
360 pinctrl_usart3_cts: usart3_cts-0 {
361 atmel,pins =
362 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
363 };
364 };
365
366 uart0 {
367 pinctrl_uart0: uart0-0 {
368 atmel,pins =
369 <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
370 AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */
371 };
372 };
373
374 uart1 {
375 pinctrl_uart1: uart1-0 {
376 atmel,pins =
377 <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE
378 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
379 };
380 };
381
382 nand {
383 pinctrl_nand_rb: nand-rb-0 {
384 atmel,pins =
385 <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
386 };
387
388 pinctrl_nand_cs: nand-cs-0 {
389 atmel,pins =
390 <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
391 };
392 };
393
394 mmc0 {
395 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
396 atmel,pins =
397 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
398 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
399 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
400 };
401
402 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
403 atmel,pins =
404 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
405 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
406 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
407 };
408
409 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
410 atmel,pins =
411 <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
412 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
413 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */
414 AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */
415 };
416 };
417
418 ssc0 {
419 pinctrl_ssc0_tx: ssc0_tx-0 {
420 atmel,pins =
421 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
422 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
423 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
424 };
425
426 pinctrl_ssc0_rx: ssc0_rx-0 {
427 atmel,pins =
428 <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
429 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
430 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
431 };
432 };
433
434 spi0 {
435 pinctrl_spi0: spi0-0 {
436 atmel,pins =
437 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
438 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
439 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
440 };
441 };
442
443 spi1 {
444 pinctrl_spi1: spi1-0 {
445 atmel,pins =
446 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
447 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
448 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
449 };
450 };
451
452 i2c0 {
453 pinctrl_i2c0: i2c0-0 {
454 atmel,pins =
455 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
456 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
457 };
458 };
459
460 i2c1 {
461 pinctrl_i2c1: i2c1-0 {
462 atmel,pins =
463 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE
464 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;
465 };
466 };
467
468 tcb0 {
469 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
470 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
471 };
472
473 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
474 atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
475 };
476
477 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
478 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
479 };
480
481 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
482 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
483 };
484
485 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
486 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
487 };
488
489 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
490 atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
491 };
492
493 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
494 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
495 };
496
497 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
498 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
499 };
500
501 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
502 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
503 };
504 };
505
506 tcb1 {
507 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
508 atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
509 };
510
511 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
512 atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
513 };
514
515 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
516 atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
517 };
518
519 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
520 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
521 };
522
523 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
524 atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
525 };
526
527 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
528 atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
529 };
530
531 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
532 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
533 };
534
535 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
536 atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
537 };
538
539 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
540 atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
541 };
542 };
543
544 pioA: gpio@fffff400 {
545 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
546 reg = <0xfffff400 0x200>;
547 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
548 #gpio-cells = <2>;
549 gpio-controller;
550 interrupt-controller;
551 #interrupt-cells = <2>;
552 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
553 };
554
555 pioB: gpio@fffff600 {
556 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
557 reg = <0xfffff600 0x200>;
558 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
559 #gpio-cells = <2>;
560 gpio-controller;
561 interrupt-controller;
562 #interrupt-cells = <2>;
563 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
564 };
565
566 pioC: gpio@fffff800 {
567 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
568 reg = <0xfffff800 0x200>;
569 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
570 #gpio-cells = <2>;
571 gpio-controller;
572 interrupt-controller;
573 #interrupt-cells = <2>;
574 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
575 };
576
577 pioD: gpio@fffffa00 {
578 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
579 reg = <0xfffffa00 0x200>;
580 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
581 #gpio-cells = <2>;
582 gpio-controller;
583 interrupt-controller;
584 #interrupt-cells = <2>;
585 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
586 };
587 };
588
589 dbgu: serial@fffff200 {
590 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
591 reg = <0xfffff200 0x200>;
592 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&pinctrl_dbgu>;
595 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
596 clock-names = "usart";
597 status = "disabled";
598 };
599
600 ssc0: ssc@f0010000 {
601 compatible = "atmel,at91sam9g45-ssc";
602 reg = <0xf0010000 0x4000>;
603 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
604 dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>,
605 <&dma 0 AT91_DMA_CFG_PER_ID(22)>;
606 dma-names = "tx", "rx";
607 pinctrl-names = "default";
608 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
609 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
610 clock-names = "pclk";
611 status = "disabled";
612 };
613
614 usart0: serial@f801c000 {
615 compatible = "atmel,at91sam9260-usart";
616 reg = <0xf801c000 0x4000>;
617 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
618 pinctrl-names = "default";
619 pinctrl-0 = <&pinctrl_usart0>;
620 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
621 clock-names = "usart";
622 status = "disabled";
623 };
624
625 usart1: serial@f8020000 {
626 compatible = "atmel,at91sam9260-usart";
627 reg = <0xf8020000 0x4000>;
628 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
629 pinctrl-names = "default";
630 pinctrl-0 = <&pinctrl_usart1>;
631 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
632 clock-names = "usart";
633 status = "disabled";
634 };
635
636 usart2: serial@f8024000 {
637 compatible = "atmel,at91sam9260-usart";
638 reg = <0xf8024000 0x4000>;
639 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
640 pinctrl-names = "default";
641 pinctrl-0 = <&pinctrl_usart2>;
642 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
643 clock-names = "usart";
644 status = "disabled";
645 };
646
647 usart3: serial@f8028000 {
648 compatible = "atmel,at91sam9260-usart";
649 reg = <0xf8028000 0x4000>;
650 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
651 pinctrl-names = "default";
652 pinctrl-0 = <&pinctrl_usart3>;
653 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
654 clock-names = "usart";
655 status = "disabled";
656 };
657
658 i2c0: i2c@f8010000 {
659 compatible = "atmel,at91sam9x5-i2c";
660 reg = <0xf8010000 0x100>;
661 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
662 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>,
663 <&dma 1 AT91_DMA_CFG_PER_ID(14)>;
664 dma-names = "tx", "rx";
665 #address-cells = <1>;
666 #size-cells = <0>;
667 pinctrl-names = "default";
668 pinctrl-0 = <&pinctrl_i2c0>;
669 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
670 status = "disabled";
671 };
672
673 i2c1: i2c@f8014000 {
674 compatible = "atmel,at91sam9x5-i2c";
675 reg = <0xf8014000 0x100>;
676 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
677 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>,
678 <&dma 1 AT91_DMA_CFG_PER_ID(16)>;
679 dma-names = "tx", "rx";
680 #address-cells = <1>;
681 #size-cells = <0>;
682 pinctrl-names = "default";
683 pinctrl-0 = <&pinctrl_i2c1>;
684 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
685 status = "disabled";
686 };
687
688 spi0: spi@f0000000 {
689 #address-cells = <1>;
690 #size-cells = <0>;
691 compatible = "atmel,at91rm9200-spi";
692 reg = <0xf0000000 0x100>;
693 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
694 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>,
695 <&dma 1 AT91_DMA_CFG_PER_ID(2)>;
696 dma-names = "tx", "rx";
697 pinctrl-names = "default";
698 pinctrl-0 = <&pinctrl_spi0>;
699 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
700 clock-names = "spi_clk";
701 status = "disabled";
702 };
703
704 spi1: spi@f0004000 {
705 #address-cells = <1>;
706 #size-cells = <0>;
707 compatible = "atmel,at91rm9200-spi";
708 reg = <0xf0004000 0x100>;
709 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
710 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>,
711 <&dma 1 AT91_DMA_CFG_PER_ID(4)>;
712 dma-names = "tx", "rx";
713 pinctrl-names = "default";
714 pinctrl-0 = <&pinctrl_spi1>;
715 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
716 clock-names = "spi_clk";
717 status = "disabled";
718 };
719
720 watchdog@fffffe40 {
721 compatible = "atmel,at91sam9260-wdt";
722 reg = <0xfffffe40 0x10>;
723 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
724 clocks = <&clk32k>;
725 atmel,watchdog-type = "hardware";
726 atmel,reset-type = "all";
727 atmel,dbg-halt;
728 status = "disabled";
729 };
730
731 rtc@fffffeb0 {
732 compatible = "atmel,at91rm9200-rtc";
733 reg = <0xfffffeb0 0x40>;
734 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
735 clocks = <&clk32k>;
736 status = "disabled";
737 };
738
739 pwm0: pwm@f8034000 {
740 compatible = "atmel,at91sam9rl-pwm";
741 reg = <0xf8034000 0x300>;
742 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
743 #pwm-cells = <3>;
744 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
745 status = "disabled";
746 };
747
748 usb1: gadget@f803c000 {
749 compatible = "atmel,at91sam9260-udc";
750 reg = <0xf803c000 0x4000>;
751 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
752 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 7>;
753 clock-names = "pclk", "hclk";
754 status = "disabled";
755 };
756 };
757
758 usb0: ohci@500000 {
759 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
760 reg = <0x00500000 0x00100000>;
761 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
762 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
763 clock-names = "ohci_clk", "hclk", "uhpck";
764 status = "disabled";
765 };
766
767 ebi: ebi@10000000 {
768 compatible = "atmel,at91sam9x5-ebi";
769 #address-cells = <2>;
770 #size-cells = <1>;
771 atmel,smc = <&smc>;
772 atmel,matrix = <&matrix>;
773 reg = <0x10000000 0x60000000>;
774 ranges = <0x0 0x0 0x10000000 0x10000000
775 0x1 0x0 0x20000000 0x10000000
776 0x2 0x0 0x30000000 0x10000000
777 0x3 0x0 0x40000000 0x10000000
778 0x4 0x0 0x50000000 0x10000000
779 0x5 0x0 0x60000000 0x10000000>;
780 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
781 status = "disabled";
782
783 nand_controller: nand-controller {
784 compatible = "atmel,at91sam9g45-nand-controller";
785 ecc-engine = <&pmecc>;
786 #address-cells = <2>;
787 #size-cells = <1>;
788 ranges;
789 status = "disabled";
790 };
791 };
792 };
793
794 i2c-gpio-0 {
795 compatible = "i2c-gpio";
796 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
797 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
798 >;
799 i2c-gpio,sda-open-drain;
800 i2c-gpio,scl-open-drain;
801 i2c-gpio,delay-us = <2>; /* ~100 kHz */
802 #address-cells = <1>;
803 #size-cells = <0>;
804 status = "disabled";
805 };
806};