tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2019 Intel Corporation
4 */
5
6#ifndef __INTEL_PM_H__
7#define __INTEL_PM_H__
8
9#include <linux/types.h>
10
11#include "i915_reg.h"
12#include "display/intel_bw.h"
13
14struct drm_device;
15struct drm_i915_private;
16struct i915_request;
17struct intel_atomic_state;
18struct intel_crtc;
19struct intel_crtc_state;
20struct intel_plane;
21struct skl_ddb_entry;
22struct skl_pipe_wm;
23struct skl_wm_level;
24
25void intel_init_clock_gating(struct drm_i915_private *dev_priv);
26void intel_suspend_hw(struct drm_i915_private *dev_priv);
27int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
28void intel_update_watermarks(struct intel_crtc *crtc);
29void intel_init_pm(struct drm_i915_private *dev_priv);
30void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
31void intel_pm_setup(struct drm_i915_private *dev_priv);
32void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
33void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
34void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
35void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
36u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
37void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
38 struct skl_ddb_entry *ddb_y,
39 struct skl_ddb_entry *ddb_uv);
40void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
41void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
42 struct skl_pipe_wm *out);
43void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
44void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
45bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
46 const struct intel_bw_state *bw_state);
47int intel_enable_sagv(struct drm_i915_private *dev_priv);
48int intel_disable_sagv(struct drm_i915_private *dev_priv);
49void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
50void intel_sagv_post_plane_update(struct intel_atomic_state *state);
51bool skl_wm_level_equals(const struct skl_wm_level *l1,
52 const struct skl_wm_level *l2);
53bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
54 const struct skl_ddb_entry *entries,
55 int num_entries, int ignore_idx);
56void skl_write_plane_wm(struct intel_plane *plane,
57 const struct intel_crtc_state *crtc_state);
58void skl_write_cursor_wm(struct intel_plane *plane,
59 const struct intel_crtc_state *crtc_state);
60bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
61void intel_init_ipc(struct drm_i915_private *dev_priv);
62void intel_enable_ipc(struct drm_i915_private *dev_priv);
63
64bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
65
66#endif /* __INTEL_PM_H__ */