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Linux kernel mirror (for testing)
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linux
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#ifndef __DML2_DISPLAY_MODE_VBA_H__
28#define __DML2_DISPLAY_MODE_VBA_H__
29
30struct display_mode_lib;
31
32void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib);
33
34#define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
35
36dml_get_attr_decl(clk_dcf_deepsleep);
37dml_get_attr_decl(wm_urgent);
38dml_get_attr_decl(wm_memory_trip);
39dml_get_attr_decl(wm_writeback_urgent);
40dml_get_attr_decl(wm_stutter_exit);
41dml_get_attr_decl(wm_stutter_enter_exit);
42dml_get_attr_decl(wm_dram_clock_change);
43dml_get_attr_decl(wm_writeback_dram_clock_change);
44dml_get_attr_decl(wm_xfc_underflow);
45dml_get_attr_decl(stutter_efficiency_no_vblank);
46dml_get_attr_decl(stutter_efficiency);
47dml_get_attr_decl(urgent_latency);
48dml_get_attr_decl(urgent_extra_latency);
49dml_get_attr_decl(nonurgent_latency);
50dml_get_attr_decl(dram_clock_change_latency);
51dml_get_attr_decl(dispclk_calculated);
52dml_get_attr_decl(total_data_read_bw);
53dml_get_attr_decl(return_bw);
54dml_get_attr_decl(tcalc);
55dml_get_attr_decl(fraction_of_urgent_bandwidth);
56dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
57
58#define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
59
60dml_get_pipe_attr_decl(dsc_delay);
61dml_get_pipe_attr_decl(dppclk_calculated);
62dml_get_pipe_attr_decl(dscclk_calculated);
63dml_get_pipe_attr_decl(min_ttu_vblank);
64dml_get_pipe_attr_decl(vratio_prefetch_l);
65dml_get_pipe_attr_decl(vratio_prefetch_c);
66dml_get_pipe_attr_decl(dst_x_after_scaler);
67dml_get_pipe_attr_decl(dst_y_after_scaler);
68dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
69dml_get_pipe_attr_decl(dst_y_per_row_vblank);
70dml_get_pipe_attr_decl(dst_y_prefetch);
71dml_get_pipe_attr_decl(dst_y_per_vm_flip);
72dml_get_pipe_attr_decl(dst_y_per_row_flip);
73dml_get_pipe_attr_decl(xfc_transfer_delay);
74dml_get_pipe_attr_decl(xfc_precharge_delay);
75dml_get_pipe_attr_decl(xfc_remote_surface_flip_latency);
76dml_get_pipe_attr_decl(xfc_prefetch_margin);
77dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
78dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
79dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
80dml_get_pipe_attr_decl(refcyc_per_vm_req_flip);
81
82unsigned int get_vstartup_calculated(
83 struct display_mode_lib *mode_lib,
84 const display_e2e_pipe_params_st *pipes,
85 unsigned int num_pipes,
86 unsigned int which_pipe);
87
88double get_total_immediate_flip_bytes(
89 struct display_mode_lib *mode_lib,
90 const display_e2e_pipe_params_st *pipes,
91 unsigned int num_pipes);
92double get_total_immediate_flip_bw(
93 struct display_mode_lib *mode_lib,
94 const display_e2e_pipe_params_st *pipes,
95 unsigned int num_pipes);
96double get_total_prefetch_bw(
97 struct display_mode_lib *mode_lib,
98 const display_e2e_pipe_params_st *pipes,
99 unsigned int num_pipes);
100unsigned int dml_get_voltage_level(
101 struct display_mode_lib *mode_lib,
102 const display_e2e_pipe_params_st *pipes,
103 unsigned int num_pipes);
104
105void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
106
107bool Calculate256BBlockSizes(
108 enum source_format_class SourcePixelFormat,
109 enum dm_swizzle_mode SurfaceTiling,
110 unsigned int BytePerPixelY,
111 unsigned int BytePerPixelC,
112 unsigned int *BlockHeight256BytesY,
113 unsigned int *BlockHeight256BytesC,
114 unsigned int *BlockWidth256BytesY,
115 unsigned int *BlockWidth256BytesC);
116
117struct vba_vars_st {
118 ip_params_st ip;
119 soc_bounding_box_st soc;
120
121 int maxMpcComb;
122 bool UseMaximumVStartup;
123
124 double WritebackDISPCLK;
125 double DPPCLKUsingSingleDPPLuma;
126 double DPPCLKUsingSingleDPPChroma;
127 double DISPCLKWithRamping;
128 double DISPCLKWithoutRamping;
129 double GlobalDPPCLK;
130 double DISPCLKWithRampingRoundedToDFSGranularity;
131 double DISPCLKWithoutRampingRoundedToDFSGranularity;
132 double MaxDispclkRoundedToDFSGranularity;
133 bool DCCEnabledAnyPlane;
134 double ReturnBandwidthToDCN;
135 unsigned int TotalActiveDPP;
136 unsigned int TotalDCCActiveDPP;
137 double UrgentRoundTripAndOutOfOrderLatency;
138 double StutterPeriod;
139 double FrameTimeForMinFullDETBufferingTime;
140 double AverageReadBandwidth;
141 double TotalRowReadBandwidth;
142 double PartOfBurstThatFitsInROB;
143 double StutterBurstTime;
144 unsigned int NextPrefetchMode;
145 double NextMaxVStartup;
146 double VBlankTime;
147 double SmallestVBlank;
148 double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
149 double EffectiveDETPlusLBLinesLuma;
150 double EffectiveDETPlusLBLinesChroma;
151 double UrgentLatencySupportUsLuma;
152 double UrgentLatencySupportUsChroma;
153 unsigned int DSCFormatFactor;
154
155 bool DummyPStateCheck;
156 bool DRAMClockChangeSupportsVActive;
157 bool PrefetchModeSupported;
158 bool PrefetchAndImmediateFlipSupported;
159 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only
160 double XFCRemoteSurfaceFlipDelay;
161 double TInitXFill;
162 double TslvChk;
163 double SrcActiveDrainRate;
164 bool ImmediateFlipSupported;
165 enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only
166
167 bool PrefetchERROR;
168
169 unsigned int VStartupLines;
170 unsigned int ActiveDPPs;
171 unsigned int LBLatencyHidingSourceLinesY;
172 unsigned int LBLatencyHidingSourceLinesC;
173 double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
174 double MinActiveDRAMClockChangeMargin;
175 double InitFillLevel;
176 double FinalFillMargin;
177 double FinalFillLevel;
178 double RemainingFillLevel;
179 double TFinalxFill;
180
181 //
182 // SOC Bounding Box Parameters
183 //
184 double SRExitTime;
185 double SREnterPlusExitTime;
186 double UrgentLatencyPixelDataOnly;
187 double UrgentLatencyPixelMixedWithVMData;
188 double UrgentLatencyVMDataOnly;
189 double UrgentLatency; // max of the above three
190 double WritebackLatency;
191 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support
192 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support
193 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support
194 double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support
195 double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support
196 double NumberOfChannels;
197 double DRAMChannelWidth;
198 double FabricDatapathToDCNDataReturn;
199 double ReturnBusWidth;
200 double Downspreading;
201 double DISPCLKDPPCLKDSCCLKDownSpreading;
202 double DISPCLKDPPCLKVCOSpeed;
203 double RoundTripPingLatencyCycles;
204 double UrgentOutOfOrderReturnPerChannel;
205 double UrgentOutOfOrderReturnPerChannelPixelDataOnly;
206 double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData;
207 double UrgentOutOfOrderReturnPerChannelVMDataOnly;
208 unsigned int VMMPageSize;
209 double DRAMClockChangeLatency;
210 double XFCBusTransportTime;
211 bool UseUrgentBurstBandwidth;
212 double XFCXBUFLatencyTolerance;
213
214 //
215 // IP Parameters
216 //
217 unsigned int ROBBufferSizeInKByte;
218 double DETBufferSizeInKByte;
219 double DETBufferSizeInTime;
220 unsigned int DPPOutputBufferPixels;
221 unsigned int OPPOutputBufferLines;
222 unsigned int PixelChunkSizeInKByte;
223 double ReturnBW;
224 bool GPUVMEnable;
225 bool HostVMEnable;
226 unsigned int GPUVMMaxPageTableLevels;
227 unsigned int HostVMMaxPageTableLevels;
228 unsigned int HostVMCachedPageTableLevels;
229 unsigned int OverrideGPUVMPageTableLevels;
230 unsigned int OverrideHostVMPageTableLevels;
231 unsigned int MetaChunkSize;
232 double MinPixelChunkSizeBytes;
233 double MinMetaChunkSizeBytes;
234 unsigned int WritebackChunkSize;
235 bool ODMCapability;
236 unsigned int NumberOfDSC;
237 unsigned int LineBufferSize;
238 unsigned int MaxLineBufferLines;
239 unsigned int WritebackInterfaceLumaBufferSize;
240 unsigned int WritebackInterfaceChromaBufferSize;
241 unsigned int WritebackChromaLineBufferWidth;
242 enum writeback_config WritebackConfiguration;
243 double MaxDCHUBToPSCLThroughput;
244 double MaxPSCLToLBThroughput;
245 unsigned int PTEBufferSizeInRequestsLuma;
246 unsigned int PTEBufferSizeInRequestsChroma;
247 double DISPCLKRampingMargin;
248 unsigned int MaxInterDCNTileRepeaters;
249 bool XFCSupported;
250 double XFCSlvChunkSize;
251 double XFCFillBWOverhead;
252 double XFCFillConstant;
253 double XFCTSlvVupdateOffset;
254 double XFCTSlvVupdateWidth;
255 double XFCTSlvVreadyOffset;
256 double DPPCLKDelaySubtotal;
257 double DPPCLKDelaySCL;
258 double DPPCLKDelaySCLLBOnly;
259 double DPPCLKDelayCNVCFormater;
260 double DPPCLKDelayCNVCCursor;
261 double DISPCLKDelaySubtotal;
262 bool ProgressiveToInterlaceUnitInOPP;
263 // Pipe/Plane Parameters
264 int VoltageLevel;
265 double FabricClock;
266 double DRAMSpeed;
267 double DISPCLK;
268 double SOCCLK;
269 double DCFCLK;
270
271 unsigned int NumberOfActivePlanes;
272 unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
273 unsigned int ViewportWidth[DC__NUM_DPP__MAX];
274 unsigned int ViewportHeight[DC__NUM_DPP__MAX];
275 unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
276 unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
277 unsigned int PitchY[DC__NUM_DPP__MAX];
278 unsigned int PitchC[DC__NUM_DPP__MAX];
279 double HRatio[DC__NUM_DPP__MAX];
280 double VRatio[DC__NUM_DPP__MAX];
281 unsigned int htaps[DC__NUM_DPP__MAX];
282 unsigned int vtaps[DC__NUM_DPP__MAX];
283 unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
284 unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
285 unsigned int HTotal[DC__NUM_DPP__MAX];
286 unsigned int VTotal[DC__NUM_DPP__MAX];
287 unsigned int VTotal_Max[DC__NUM_DPP__MAX];
288 unsigned int VTotal_Min[DC__NUM_DPP__MAX];
289 int DPPPerPlane[DC__NUM_DPP__MAX];
290 double PixelClock[DC__NUM_DPP__MAX];
291 double PixelClockBackEnd[DC__NUM_DPP__MAX];
292 bool DCCEnable[DC__NUM_DPP__MAX];
293 bool FECEnable[DC__NUM_DPP__MAX];
294 unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
295 unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
296 enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
297 enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
298 bool WritebackEnable[DC__NUM_DPP__MAX];
299 unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX];
300 double WritebackDestinationWidth[DC__NUM_DPP__MAX];
301 double WritebackDestinationHeight[DC__NUM_DPP__MAX];
302 double WritebackSourceHeight[DC__NUM_DPP__MAX];
303 enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
304 unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
305 unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
306 unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
307 unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
308 double WritebackHRatio[DC__NUM_DPP__MAX];
309 double WritebackVRatio[DC__NUM_DPP__MAX];
310 unsigned int HActive[DC__NUM_DPP__MAX];
311 unsigned int VActive[DC__NUM_DPP__MAX];
312 bool Interlace[DC__NUM_DPP__MAX];
313 enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
314 unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
315 bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
316 int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
317 unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
318 double DCCRate[DC__NUM_DPP__MAX];
319 double AverageDCCCompressionRate;
320 enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX];
321 double OutputBpp[DC__NUM_DPP__MAX];
322 bool DSCEnabled[DC__NUM_DPP__MAX];
323 unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
324 enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
325 enum output_encoder_class Output[DC__NUM_DPP__MAX];
326 unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
327 bool SynchronizedVBlank;
328 unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
329 unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
330 unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
331 bool XFCEnabled[DC__NUM_DPP__MAX];
332 bool ScalerEnabled[DC__NUM_DPP__MAX];
333
334 // Intermediates/Informational
335 bool ImmediateFlipSupport;
336 double DETBufferSizeY[DC__NUM_DPP__MAX];
337 double DETBufferSizeC[DC__NUM_DPP__MAX];
338 unsigned int SwathHeightY[DC__NUM_DPP__MAX];
339 unsigned int SwathHeightC[DC__NUM_DPP__MAX];
340 unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
341 double LastPixelOfLineExtraWatermark;
342 double TotalDataReadBandwidth;
343 unsigned int TotalActiveWriteback;
344 unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
345 unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
346 double BandwidthAvailableForImmediateFlip;
347 unsigned int PrefetchMode[DC__VOLTAGE_STATES + 1][2];
348 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES + 1][2];
349 unsigned int MinPrefetchMode;
350 unsigned int MaxPrefetchMode;
351 bool AnyLinesForVMOrRowTooLarge;
352 double MaxVStartup;
353 bool IgnoreViewportPositioning;
354 bool ErrorResult[DC__NUM_DPP__MAX];
355 //
356 // Calculated dml_ml->vba.Outputs
357 //
358 double DCFCLKDeepSleep;
359 double UrgentWatermark;
360 double UrgentExtraLatency;
361 double WritebackUrgentWatermark;
362 double StutterExitWatermark;
363 double StutterEnterPlusExitWatermark;
364 double DRAMClockChangeWatermark;
365 double WritebackDRAMClockChangeWatermark;
366 double StutterEfficiency;
367 double StutterEfficiencyNotIncludingVBlank;
368 double NonUrgentLatencyTolerance;
369 double MinActiveDRAMClockChangeLatencySupported;
370
371 // These are the clocks calcuated by the library but they are not actually
372 // used explicitly. They are fetched by tests and then possibly used. The
373 // ultimate values to use are the ones specified by the parameters to DML
374 double DISPCLK_calculated;
375 double DPPCLK_calculated[DC__NUM_DPP__MAX];
376
377 unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
378 double VUpdateWidthPix[DC__NUM_DPP__MAX];
379 double VReadyOffsetPix[DC__NUM_DPP__MAX];
380
381 unsigned int TotImmediateFlipBytes;
382 double TCalc;
383
384 display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
385 unsigned int cache_num_pipes;
386 unsigned int pipe_plane[DC__NUM_DPP__MAX];
387
388 /* vba mode support */
389 /*inputs*/
390 bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
391 double MaxHSCLRatio;
392 double MaxVSCLRatio;
393 unsigned int MaxNumWriteback;
394 bool WritebackLumaAndChromaScalingSupported;
395 bool Cursor64BppSupport;
396 double DCFCLKPerState[DC__VOLTAGE_STATES + 1];
397 double DCFCLKState[DC__VOLTAGE_STATES + 1][2];
398 double FabricClockPerState[DC__VOLTAGE_STATES + 1];
399 double SOCCLKPerState[DC__VOLTAGE_STATES + 1];
400 double PHYCLKPerState[DC__VOLTAGE_STATES + 1];
401 double DTBCLKPerState[DC__VOLTAGE_STATES + 1];
402 double MaxDppclk[DC__VOLTAGE_STATES + 1];
403 double MaxDSCCLK[DC__VOLTAGE_STATES + 1];
404 double DRAMSpeedPerState[DC__VOLTAGE_STATES + 1];
405 double MaxDispclk[DC__VOLTAGE_STATES + 1];
406 int VoltageOverrideLevel;
407
408 /*outputs*/
409 bool ScaleRatioAndTapsSupport;
410 bool SourceFormatPixelAndScanSupport;
411 double TotalBandwidthConsumedGBytePerSecond;
412 bool DCCEnabledInAnyPlane;
413 bool WritebackLatencySupport;
414 bool WritebackModeSupport;
415 bool Writeback10bpc420Supported;
416 bool BandwidthSupport[DC__VOLTAGE_STATES + 1];
417 unsigned int TotalNumberOfActiveWriteback;
418 double CriticalPoint;
419 double ReturnBWToDCNPerState;
420 bool IsErrorResult[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
421 bool prefetch_vm_bw_valid;
422 bool prefetch_row_bw_valid;
423 bool NumberOfOTGSupport;
424 bool NonsupportedDSCInputBPC;
425 bool WritebackScaleRatioAndTapsSupport;
426 bool CursorSupport;
427 bool PitchSupport;
428 enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES + 1];
429
430 double WritebackLineBufferLumaBufferSize;
431 double WritebackLineBufferChromaBufferSize;
432 double WritebackMinHSCLRatio;
433 double WritebackMinVSCLRatio;
434 double WritebackMaxHSCLRatio;
435 double WritebackMaxVSCLRatio;
436 double WritebackMaxHSCLTaps;
437 double WritebackMaxVSCLTaps;
438 unsigned int MaxNumDPP;
439 unsigned int MaxNumOTG;
440 double CursorBufferSize;
441 double CursorChunkSize;
442 unsigned int Mode;
443 double OutputLinkDPLanes[DC__NUM_DPP__MAX];
444 double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only
445 double ImmediateFlipBW[DC__NUM_DPP__MAX];
446 double MaxMaxVStartup[DC__VOLTAGE_STATES + 1][2];
447
448 double WritebackLumaVExtra;
449 double WritebackChromaVExtra;
450 double WritebackRequiredDISPCLK;
451 double MaximumSwathWidthSupport;
452 double MaximumSwathWidthInDETBuffer;
453 double MaximumSwathWidthInLineBuffer;
454 double MaxDispclkRoundedDownToDFSGranularity;
455 double MaxDppclkRoundedDownToDFSGranularity;
456 double PlaneRequiredDISPCLKWithoutODMCombine;
457 double PlaneRequiredDISPCLKWithODMCombine;
458 double PlaneRequiredDISPCLK;
459 double TotalNumberOfActiveOTG;
460 double FECOverhead;
461 double EffectiveFECOverhead;
462 double Outbpp;
463 unsigned int OutbppDSC;
464 double TotalDSCUnitsRequired;
465 double bpp;
466 unsigned int slices;
467 double SwathWidthGranularityY;
468 double RoundedUpMaxSwathSizeBytesY;
469 double SwathWidthGranularityC;
470 double RoundedUpMaxSwathSizeBytesC;
471 double EffectiveDETLBLinesLuma;
472 double EffectiveDETLBLinesChroma;
473 double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES + 1][2];
474 double PDEAndMetaPTEBytesPerFrameY;
475 double PDEAndMetaPTEBytesPerFrameC;
476 unsigned int MetaRowBytesY;
477 unsigned int MetaRowBytesC;
478 unsigned int DPTEBytesPerRowC;
479 unsigned int DPTEBytesPerRowY;
480 double ExtraLatency;
481 double TimeCalc;
482 double TWait;
483 double MaximumReadBandwidthWithPrefetch;
484 double MaximumReadBandwidthWithoutPrefetch;
485 double total_dcn_read_bw_with_flip;
486 double total_dcn_read_bw_with_flip_no_urgent_burst;
487 double FractionOfUrgentBandwidth;
488 double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output
489
490 /* ms locals */
491 double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES + 1][2];
492 unsigned int NoOfDPP[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
493 int NoOfDPPThisState[DC__NUM_DPP__MAX];
494 enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
495 double SwathWidthYThisState[DC__NUM_DPP__MAX];
496 unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
497 unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
498 unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX];
499 double VRatioPreY[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
500 double VRatioPreC[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
501 double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
502 double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
503 double RequiredDPPCLK[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
504 double RequiredDPPCLKThisState[DC__NUM_DPP__MAX];
505 bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
506 bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
507 bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES + 1][2];
508 bool PrefetchSupported[DC__VOLTAGE_STATES + 1][2];
509 bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES + 1][2];
510 double RequiredDISPCLK[DC__VOLTAGE_STATES + 1][2];
511 bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES + 1][2];
512 bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES + 1][2];
513 unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES + 1][2];
514 unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES + 1][2];
515 bool ModeSupport[DC__VOLTAGE_STATES + 1][2];
516 double ReturnBWPerState[DC__VOLTAGE_STATES + 1][2];
517 bool DIOSupport[DC__VOLTAGE_STATES + 1];
518 bool NotEnoughDSCUnits[DC__VOLTAGE_STATES + 1];
519 bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
520 bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
521 double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES + 1];
522 bool ROBSupport[DC__VOLTAGE_STATES + 1][2];
523 bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES + 1][2];
524 bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES + 1][2];
525 double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES + 1][2];
526 double PrefetchBW[DC__NUM_DPP__MAX];
527 double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
528 double MetaRowBytes[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
529 double DPTEBytesPerRow[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
530 double PrefetchLinesY[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
531 double PrefetchLinesC[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
532 unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
533 unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
534 double PrefillY[DC__NUM_DPP__MAX];
535 double PrefillC[DC__NUM_DPP__MAX];
536 double LineTimesForPrefetch[DC__NUM_DPP__MAX];
537 double LinesForMetaPTE[DC__NUM_DPP__MAX];
538 double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
539 double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
540 double SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
541 double BytePerPixelInDETY[DC__NUM_DPP__MAX];
542 double BytePerPixelInDETC[DC__NUM_DPP__MAX];
543 bool RequiresDSC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
544 unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
545 double RequiresFEC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
546 double OutputBppPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
547 double DSCDelayPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
548 bool ViewportSizeSupport[DC__VOLTAGE_STATES + 1][2];
549 unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
550 unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
551 unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
552 unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
553 double MaxSwathHeightY[DC__NUM_DPP__MAX];
554 double MaxSwathHeightC[DC__NUM_DPP__MAX];
555 double MinSwathHeightY[DC__NUM_DPP__MAX];
556 double MinSwathHeightC[DC__NUM_DPP__MAX];
557 double ReadBandwidthLuma[DC__NUM_DPP__MAX];
558 double ReadBandwidthChroma[DC__NUM_DPP__MAX];
559 double ReadBandwidth[DC__NUM_DPP__MAX];
560 double WriteBandwidth[DC__NUM_DPP__MAX];
561 double PSCL_FACTOR[DC__NUM_DPP__MAX];
562 double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
563 double MaximumVStartup[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
564 unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
565 unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
566 double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
567 double AlignedYPitch[DC__NUM_DPP__MAX];
568 double AlignedCPitch[DC__NUM_DPP__MAX];
569 double MaximumSwathWidth[DC__NUM_DPP__MAX];
570 double cursor_bw[DC__NUM_DPP__MAX];
571 double cursor_bw_pre[DC__NUM_DPP__MAX];
572 double Tno_bw[DC__NUM_DPP__MAX];
573 double prefetch_vmrow_bw[DC__NUM_DPP__MAX];
574 double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
575 double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
576 double final_flip_bw[DC__NUM_DPP__MAX];
577 bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES + 1][2];
578 double WritebackDelay[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
579 unsigned int vm_group_bytes[DC__NUM_DPP__MAX];
580 unsigned int dpte_group_bytes[DC__NUM_DPP__MAX];
581 unsigned int dpte_row_height[DC__NUM_DPP__MAX];
582 unsigned int meta_req_height[DC__NUM_DPP__MAX];
583 unsigned int meta_req_width[DC__NUM_DPP__MAX];
584 unsigned int meta_row_height[DC__NUM_DPP__MAX];
585 unsigned int meta_row_width[DC__NUM_DPP__MAX];
586 unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
587 unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX];
588 unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX];
589 unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
590 unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX];
591 bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
592 double meta_row_bw[DC__NUM_DPP__MAX];
593 double dpte_row_bw[DC__NUM_DPP__MAX];
594 double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX]; // WM
595 double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX]; // WM
596 double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX];
597 double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX];
598 enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES + 1][2];
599 double UrgentBurstFactorCursor[DC__NUM_DPP__MAX];
600 double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX];
601 double UrgentBurstFactorLuma[DC__NUM_DPP__MAX];
602 double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX];
603 double UrgentBurstFactorChroma[DC__NUM_DPP__MAX];
604 double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX];
605
606
607 bool MPCCombine[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
608 double SwathWidthCSingleDPP[DC__NUM_DPP__MAX];
609 double MaximumSwathWidthInLineBufferLuma;
610 double MaximumSwathWidthInLineBufferChroma;
611 double MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
612 double MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
613 enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX];
614 double dummy1[DC__NUM_DPP__MAX];
615 double dummy2[DC__NUM_DPP__MAX];
616 double dummy3[DC__NUM_DPP__MAX];
617 double dummy4[DC__NUM_DPP__MAX];
618 double dummy5;
619 double dummy6;
620 double dummy7[DC__NUM_DPP__MAX];
621 double dummy8[DC__NUM_DPP__MAX];
622 unsigned int dummyinteger1ms[DC__NUM_DPP__MAX];
623 double dummyinteger2ms[DC__NUM_DPP__MAX];
624 unsigned int dummyinteger3[DC__NUM_DPP__MAX];
625 unsigned int dummyinteger4[DC__NUM_DPP__MAX];
626 unsigned int dummyinteger5;
627 unsigned int dummyinteger6;
628 unsigned int dummyinteger7;
629 unsigned int dummyinteger8;
630 unsigned int dummyinteger9;
631 unsigned int dummyinteger10;
632 unsigned int dummyinteger11;
633 unsigned int dummyinteger12;
634 unsigned int dummyintegerarr1[DC__NUM_DPP__MAX];
635 unsigned int dummyintegerarr2[DC__NUM_DPP__MAX];
636 unsigned int dummyintegerarr3[DC__NUM_DPP__MAX];
637 unsigned int dummyintegerarr4[DC__NUM_DPP__MAX];
638 bool dummysinglestring;
639 bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
640 double PlaneRequiredDISPCLKWithODMCombine2To1;
641 double PlaneRequiredDISPCLKWithODMCombine4To1;
642 unsigned int TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES + 1][2];
643 bool LinkDSCEnable;
644 bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES + 1];
645 enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX];
646 double SwathWidthCThisState[DC__NUM_DPP__MAX];
647 bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
648 double AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
649 double AlignedDCCMetaPitchC[DC__NUM_DPP__MAX];
650
651 unsigned int NotEnoughUrgentLatencyHiding;
652 unsigned int NotEnoughUrgentLatencyHidingPre;
653 int PTEBufferSizeInRequestsForLuma;
654 int PTEBufferSizeInRequestsForChroma;
655
656 // Missing from VBA
657 int dpte_group_bytes_chroma;
658 unsigned int vm_group_bytes_chroma;
659 double dst_x_after_scaler;
660 double dst_y_after_scaler;
661 unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
662
663 /* perf locals*/
664 double PrefetchBandwidth[DC__NUM_DPP__MAX];
665 double VInitPreFillY[DC__NUM_DPP__MAX];
666 double VInitPreFillC[DC__NUM_DPP__MAX];
667 unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
668 unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
669 unsigned int VStartup[DC__NUM_DPP__MAX];
670 double DSTYAfterScaler[DC__NUM_DPP__MAX];
671 double DSTXAfterScaler[DC__NUM_DPP__MAX];
672 bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
673 bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
674 double VRatioPrefetchY[DC__NUM_DPP__MAX];
675 double VRatioPrefetchC[DC__NUM_DPP__MAX];
676 double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
677 double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
678 double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
679 double MinTTUVBlank[DC__NUM_DPP__MAX];
680 double BytePerPixelDETY[DC__NUM_DPP__MAX];
681 double BytePerPixelDETC[DC__NUM_DPP__MAX];
682 double SwathWidthY[DC__NUM_DPP__MAX];
683 double SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
684 double CursorRequestDeliveryTime[DC__NUM_DPP__MAX];
685 double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX];
686 double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
687 double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
688 double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
689 double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
690 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
691 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
692 double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
693 double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
694 double MetaRowByte[DC__NUM_DPP__MAX];
695 double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
696 double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX];
697 double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX];
698 double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
699 double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
700 double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
701 double DSCCLK_calculated[DC__NUM_DPP__MAX];
702 unsigned int DSCDelay[DC__NUM_DPP__MAX];
703 unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
704 double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
705 double DPPCLK[DC__NUM_DPP__MAX];
706 unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX];
707 unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX];
708 unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX];
709 double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX];
710 unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
711 unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
712 unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
713 unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
714 double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
715 double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
716 double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
717 double XFCTransferDelay[DC__NUM_DPP__MAX];
718 double XFCPrechargeDelay[DC__NUM_DPP__MAX];
719 double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
720 double XFCPrefetchMargin[DC__NUM_DPP__MAX];
721 unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX];
722 unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX];
723 double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; // WM
724 double FullDETBufferingTimeC[DC__NUM_DPP__MAX]; // WM
725 double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX];
726 double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX];
727 double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX];
728 double TimePerMetaChunkNominal[DC__NUM_DPP__MAX];
729 double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX];
730 double TimePerMetaChunkFlip[DC__NUM_DPP__MAX];
731 unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX];
732 unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX];
733 unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX];
734 unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX];
735 unsigned int PTERequestSizeY[DC__NUM_DPP__MAX];
736 unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX];
737 unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX];
738 unsigned int PTERequestSizeC[DC__NUM_DPP__MAX];
739 double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX];
740 double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX];
741 double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX];
742 double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX];
743 double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX];
744 double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX];
745 double TimePerVMGroupVBlank[DC__NUM_DPP__MAX];
746 double TimePerVMGroupFlip[DC__NUM_DPP__MAX];
747 double TimePerVMRequestVBlank[DC__NUM_DPP__MAX];
748 double TimePerVMRequestFlip[DC__NUM_DPP__MAX];
749 unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
750 unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
751 unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
752 unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
753 double LinesToFinishSwathTransferStutterCriticalPlane;
754 unsigned int BytePerPixelYCriticalPlane;
755 double SwathWidthYCriticalPlane;
756 double LinesInDETY[DC__NUM_DPP__MAX];
757 double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
758
759 double SwathWidthSingleDPPC[DC__NUM_DPP__MAX];
760 double SwathWidthC[DC__NUM_DPP__MAX];
761 unsigned int BytePerPixelY[DC__NUM_DPP__MAX];
762 unsigned int BytePerPixelC[DC__NUM_DPP__MAX];
763 unsigned int dummyinteger1;
764 unsigned int dummyinteger2;
765 double FinalDRAMClockChangeLatency;
766 double Tdmdl_vm[DC__NUM_DPP__MAX];
767 double Tdmdl[DC__NUM_DPP__MAX];
768 unsigned int ThisVStartup;
769 bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX];
770 double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX];
771 double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX];
772 double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX];
773 double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX];
774 unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX];
775 unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX];
776 unsigned int DCCCIndependent64ByteBlock[DC__NUM_DPP__MAX];
777 double VStartupMargin;
778 bool NotEnoughTimeForDynamicMetadata;
779
780 /* Missing from VBA */
781 unsigned int MaximumMaxVStartupLines;
782 double FabricAndDRAMBandwidth;
783 double LinesInDETLuma;
784 double LinesInDETChroma;
785 unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
786 unsigned int LinesInDETC[DC__NUM_DPP__MAX];
787 unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
788 double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
789 double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
790 double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES + 1];
791 bool UrgentLatencySupport[DC__VOLTAGE_STATES + 1][2];
792 unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
793 unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
794 double qual_row_bw[DC__NUM_DPP__MAX];
795 double prefetch_row_bw[DC__NUM_DPP__MAX];
796 double prefetch_vm_bw[DC__NUM_DPP__MAX];
797
798 double PTEGroupSize;
799 unsigned int PDEProcessingBufIn64KBReqs;
800
801 double MaxTotalVActiveRDBandwidth;
802 bool DoUrgentLatencyAdjustment;
803 double UrgentLatencyAdjustmentFabricClockComponent;
804 double UrgentLatencyAdjustmentFabricClockReference;
805 double MinUrgentLatencySupportUs;
806 double MinFullDETBufferingTime;
807 double AverageReadBandwidthGBytePerSecond;
808 bool FirstMainPlane;
809
810 unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX];
811 unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX];
812 double HRatioChroma[DC__NUM_DPP__MAX];
813 double VRatioChroma[DC__NUM_DPP__MAX];
814 int WritebackSourceWidth[DC__NUM_DPP__MAX];
815
816 bool ModeIsSupported;
817 bool ODMCombine4To1Supported;
818
819 unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
820 unsigned int SurfaceWidthC[DC__NUM_DPP__MAX];
821 unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
822 unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
823 unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
824 unsigned int WritebackVTaps[DC__NUM_DPP__MAX];
825 bool DSCEnable[DC__NUM_DPP__MAX];
826
827 double DRAMClockChangeLatencyOverride;
828
829 double GPUVMMinPageSize;
830 double HostVMMinPageSize;
831
832 bool MPCCombineEnable[DC__NUM_DPP__MAX];
833 unsigned int HostVMMaxNonCachedPageTableLevels;
834 bool DynamicMetadataVMEnabled;
835 double WritebackInterfaceBufferSize;
836 double WritebackLineBufferSize;
837
838 double DCCRateLuma[DC__NUM_DPP__MAX];
839 double DCCRateChroma[DC__NUM_DPP__MAX];
840
841 double PHYCLKD18PerState[DC__VOLTAGE_STATES + 1];
842
843 bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
844 bool NumberOfHDMIFRLSupport;
845 unsigned int MaxNumHDMIFRLOutputs;
846 int AudioSampleRate[DC__NUM_DPP__MAX];
847 int AudioSampleLayout[DC__NUM_DPP__MAX];
848
849 int PercentMarginOverMinimumRequiredDCFCLK;
850 bool DynamicMetadataSupported[DC__VOLTAGE_STATES + 1][2];
851 enum immediate_flip_requirement ImmediateFlipRequirement;
852 double DETBufferSizeYThisState[DC__NUM_DPP__MAX];
853 double DETBufferSizeCThisState[DC__NUM_DPP__MAX];
854 bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX];
855 bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
856 int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
857 int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX];
858 double UrgLatency[DC__VOLTAGE_STATES + 1];
859 double VActiveCursorBandwidth[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
860 double VActivePixelBandwidth[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
861 bool NoTimeForPrefetch[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
862 bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
863 double dpte_row_bandwidth[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
864 double meta_row_bandwidth[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
865 double DETBufferSizeYAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
866 double DETBufferSizeCAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
867 int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
868 int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
869 bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES + 1][2];
870 unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
871 unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
872 unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
873 unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
874 double TotalDPTERowBandwidth[DC__VOLTAGE_STATES + 1][2];
875 double TotalMetaRowBandwidth[DC__VOLTAGE_STATES + 1][2];
876 double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES + 1][2];
877 double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES + 1][2];
878 double WritebackDelayTime[DC__NUM_DPP__MAX];
879 unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX];
880 unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX];
881 unsigned int dummyinteger15;
882 unsigned int dummyinteger16;
883 unsigned int dummyinteger17;
884 unsigned int dummyinteger18;
885 unsigned int dummyinteger19;
886 unsigned int dummyinteger20;
887 unsigned int dummyinteger21;
888 unsigned int dummyinteger22;
889 unsigned int dummyinteger23;
890 unsigned int dummyinteger24;
891 unsigned int dummyinteger25;
892 unsigned int dummyinteger26;
893 unsigned int dummyinteger27;
894 unsigned int dummyinteger28;
895 unsigned int dummyinteger29;
896 bool dummystring[DC__NUM_DPP__MAX];
897 double BPP;
898 enum odm_combine_policy ODMCombinePolicy;
899 bool UseMinimumRequiredDCFCLK;
900 bool AllowDramClockChangeOneDisplayVactive;
901};
902
903bool CalculateMinAndMaxPrefetchMode(
904 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
905 unsigned int *MinPrefetchMode,
906 unsigned int *MaxPrefetchMode);
907
908double CalculateWriteBackDISPCLK(
909 enum source_format_class WritebackPixelFormat,
910 double PixelClock,
911 double WritebackHRatio,
912 double WritebackVRatio,
913 unsigned int WritebackLumaHTaps,
914 unsigned int WritebackLumaVTaps,
915 unsigned int WritebackChromaHTaps,
916 unsigned int WritebackChromaVTaps,
917 double WritebackDestinationWidth,
918 unsigned int HTotal,
919 unsigned int WritebackChromaLineBufferWidth);
920
921#endif /* _DML2_DISPLAY_MODE_VBA_H_ */